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Constraints imposed by advanced IC process technologies, modern electronic system requirements, and the economics of circuit integration have created new challenges in analog circuit design. With the advancement of CMOS process technologies and the increasing popularity of battery-powered mobile electronic systems comes the demand for lower-voltage analog circuit designs. In addition, the drive to reduce system costs is forcing the integration of both analog and digital circuitry onto a single die. Both of these changes have a detrimental impact on analog circuit performance. With a reduction in power supply voltage comes a decrease in both the peak SNR and the dynamic range of an analog circuit. Integrating analog circuitry and noisy digital circuitry on the same die further degrades analog performance due to noise injection through a common power supply and/or power distribution network, the die substrate, and/or capacitive coupling between conductors. Many analog design techniques and methodologies have been devised to enable high performance analog signal processing in today's environment. Fully differential analog signal processing is one technique that has become widespread because it reduces the problems associated with both reduced signal swings and noise coupling. Using a differential design technique effectively doubles the maximum signal swing in the circuit. Also, all external noise sources that influence both signal paths of a balanced differential system in the same way, to a first order approximation, will be rejected. This is due to the fact that, in a differential system, the signal of interest is the difference between the signals in the two signal paths. Thus any noise common to both signal paths will be subtracted away. For the same reason, the total harmonic distortion of the circuit due to non-linear elements can be reduced. Each distortion component at a frequency that is an even harmonics of the fundamental signal frequency will be subtracted away from the differential signal because it is a common in both signal paths .Operational amplifiers are the backbone for many analog circuit designs. It is a fundamental building block for many circuit designs that utilize its high gain, high input impedance, low output impedance, high bandwidth and fast settling time. Operational amplifier (Op-Amp) is one of the basic and important circuits which have a wide application in several analog circuits such as switched-capacitor filters, algorithmic, pipelined and sigma-delta A/D converters, sample-and hold amplifiers etc. The speed and accuracy of these circuits depend on the bandwidth and DC gain of the Op-amp. Larger the bandwidth and gain, higher the speed and accuracy of the amplifier . Operational amplifiers are a critical element in analog sampled-data circuits, such as SC filters, modulators. Higher and higher clock frequency requirement for these circuits translates directly to higher frequency requirement for the Op-amp. A high gain bandwidth (GBW) is essential for accurate dynamic charge transfer in a switch-capacitor (SC) circuit in a short sampling period. Applications of the high speed op-amp range from video amplifiers to sampling circuits. Many fibre optic applications also require analog drivers and receivers operating in the megahertz range wide-band op-amps are necessary. In recent years, CMOS analog-digital converters (ADC) are expected to achieve a high gain and unity gain frequency, and a fast settling time. However, the problem is that high speed and high open-loop gain are two contradictory demands . An integrated, fully-differential amplifier is very similar in architecture to a standard, voltage feedback operational amplifier. Fully differential amplifiers have differential outputs, while a standard operational amplifier's output is single-ended. There is typically one feedback path from the output to the negative input in a standard operational amplifier. A fully-differential amplifier has multiple feedback paths.
II. OP - AM P AR C H I T E C T U RE
Fig.1 shows the block diagram of bandwidth enhanced UWB op-amp. In Fig 2 shows full design of op-amp In It is a fully differential two stage miller op amp which has a cascoded, high gain first stage and a Class AB output-stage similar to a CMOS inverter. The compensation network uses miller compensation with nulling resistance for pole-zero cancelation. The cascode device bias employs a high swing cascode current mirror bias with startup circuit and triple MOS diode-stack bias generator for Bias1 and Bias2 respectively. The proposed op-amp has several features which make it very suitable for high bandwidth, high output swing and high gain op-amp design.
Fig1.Block Diagram of op-amp
Fully-differential (FD) operation is used to achieve large output swing and signal to noise ratio , particularly in low VDD regimes. FD architecture substantially eliminates common mode supply- line noise and switching noise coupled via the substrate and alleviates even-order harmonic distortion issues. However, they require common-mode level control circuits which requires additional power and may limit output swing, output stage gain and stability. The proposed op-amp uses an improved complementary sensing common mode feedback circuit (CSA CMFB) originally proposed in . The advantage of using this CMFB circuit is its ability to ensure fast continuous time level control, high output swing, while not loading the output stage significantly as opposed to resistive-sensing based or switched capacitor (S/C) CMFB circuits.
III. FR E QU E N C Y CO M P E N S AT I O N
A N D OU T P UT STAG E
The proposed design uses a high gain input stage for noise and power considerations. The key to enhanced bandwidth lies in use of a class-AB CMOS inverter amplifier output stage. This output stage nearly doubles the output transconductance (Gm0) with respect to the widely used class-A output stage as both the NMOS and PMOS devices contribute to Gm0. The output pole is given by
which is nearly twice as much as
for the PMOS (or NMOS) of a class-A output stage. Note that both PMOS and NMOS transconductance are designed to be equal. Since both output devices operate in saturation region the small-signal output resistance is rdsN|| rdsP, which is less than the class- A common source output resistance by a factor of ~ 2. The increased Gm0 compensates almost exactly for the decrease in resistance and gives the same DC gain as the class-A output stage op-amp. The overall low-frequency gain of the op-amp is AVo, given by:
Fig 2. Proposed operational amplifier (A) first and second stages along with CSA-CMFB circuit (B) Tracking bias circuit
Where A1 first stage gain or differential stage gain, A2 push-pull amplifier gain and overall gain product of A1 and A2, gdsi represent the channel output conductances and gmi represent the device transconductances. All pairs of symmetric devices are matched with same dimensions throughout the design. The unity gain bandwidth (UGB) is determined by gm1/Cc, where Cc is the compensation capacitor. Thus the input transistors M1-M2 must be sized large for high
Gm1, required for the large bandwidth. Pole-zero compensation is achieved using a Miller capacitance added in series with dual PMOS resistor (Rz),formed by P1-P4 devices ,biased by a tracking bias circuit for accurate compensation .The widely used paradigm in class-A output stage is to push the nulling zero (Z1), equal to , to infinity (by choosing ) to avoid in-band frequency doublets arising from inaccurate in-band pole-zero compensation, leaving p2 as the first non-dominant pole. In the proposed design due to the increased output stage gm , shifting the output pole much beyond the UGB is easily realized. Further, the output pole, p2 is canceled using the left-half-plane nulling zero, z1, arising from the compensation network. The advantage of pushing the output pole beyond the UGB is that any small mismatch in pole-zero cancelation would give rise to a pole-zero doublet situated much beyond the UGB, which has negligible impact on the step response and settling time of the op-amp. Hence it is effectively 'doublet-free' cancelation. Also cancelation of the pole ensures better control of phase margin, i.e. the second and third non-dominant poles (parasitic poles) can be much closer to the UGB, enabling reduction in bias current for the same phase margin. Thus we see that this strategy is more robust to higher order non- dominant parasitic poles and achieves a very wide UGB in excess of 2 GHz. With p2 canceled by z1, p3 becomes the first non-dominant pole,
Given by .For 60o phase margin p3 is placed around 1.73 times the UGB.
IV. SIMULATED RESULTS
Simulation performed on CADENCE IC design platform. Fig 3 shows that the op-amp achieves a UGC 1.8GHz with 600 phase margin and a DC gain of 85dB while operating from a 1.8V VDD .It also has 145dB CMRR .Fig 4 shows common mode voltage gain in negative in dBs. The dc input and output levels are at VDD/2 for ease of voltage feedback, maximizing the single ended output swing and to reduce systematic DC offset. Fig 5 shows the differential output swing of 1.5v to -1.5V. The critical performance parameters of the UGB op-amp shown in table 1
PERFORMANCE SUMMARY OF THE OP-AMP
0.18ï CMOS Technology
Unity Gain Bandwidth
Differential Output Swing
1.5 V to -1.5 V
150 V/ï€ ïs for 1pF capacitive load
Input quiescent Level
Output quiescent Level
Fig 3. Gain and Phase plots Vs frequency. UGB of 1.2GHz is observed
Fig 4. In common mode configuration common mode input, common mode output and common mode gain
This paper presented a fully differential ultra-wide band width operational amplifier realizing a UGB of 1.2GHz with high DC gain of 85dB, by using a CMOS inverter output stage and 'doublet free' pole-zero cancelation scheme. The op-amp exhibits a CMRR of 145 dB and has overall good performance for most applications, which include high speed sigma-delta modulators, data converter, precision SC applications, Video drivers and RF-ADCs.
Fig 5. Measured differential output swing for 10MHz frequency.
This work has been carried out in SMDP VLSI laboratory of the Electronics and Instrumentation department of Shri G. S. Institute of Technology and Science, Indore, India. The author is thankful to the ministry for facilities provided.
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