Fram Based Tmr Triple Modular Redundancy For Fault Tolerance Implementation Computer Science Essay

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The main objective of this paper is to design a Triple modular redundancy test bench using FRAM based memory module for OBDH (On Board Data Handling) system of LEO Satellite that enables the fast detection of error when implied with FPGA and provides more realistic and tolerant way of fault finding for Single Event Upset (SEU) in highly radiated space environment. The scope of paper embraces an implementation of test bench, software algorithms, functional simulation, timing simulation and conclusion of comparison of FRAM based memory module with EPROM and Flash Memories for fault finding and tolera.

Fault tolerance is the capability of a system to cope with inside errors and achieve its task correctly. The idea of fault tolerance is to boost the dependency of a system. A complementary but separate approach for rising reliability is fault deterrence. inherent in the explanation of fault tolerance is the postulation that there is a specification of what makes up correct performance. A collapse occurs when a real running system diverges from this particular behavior. The reason of collapse is called an error. An error characterizes an invalid system state, one that is not acceptable by the system behavior requirements. The error itself is the outcome of a failing in the system or fault.

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Accordingly, fault is the core cause of a system failure. That means an error is merely the sign of a fault. A fault might not essentially result in an error, but the same fault may outcomes in numerous errors. Similarly a single error may escort to numerous failures.

on the road to clarify triple-modular redundancy, it is initially necessary to explain the idea of triple redundancy, originally envisaged by Von Neumann. [4]The idea is shown in Fig. 1, where the three boxes taged with A, B and C respectively are identical units or black boxes that have a single output and hold digital equipment. (A black box may be a complete Personal Computer, or it can be a much less complex device, e.g. an adder or a gate.) The ring labeled Voter is termed a "majority organ" by Von Neumann. It is refered as a voting circuit since it admits the input by the three sources and brings out the majority estimation as an output. Since the outputs of the three boxes are binary and the number of inputs is odd, there is bound to be an explicit majority opinion. The three systems perform a procedure and the result is processed by a voting system to create a single output. If any one of the three systems falls short, the other two systems can correct and cover the fault. The error circuit turns high whenever any one of the output diverges from the other two; its output can be processed to command an auto refresher circuit that corrects the error by changing the contents of the individual box generating an error.

Figure 1 : Block diagram of a TMR circuit [4].

Why FRAM

The reasons to use FRAM as a storage in memory module of OBDH system can be inferred from attributes of comparison between FRAM, EPROM and Flash that are depicted in table-1 which describes, FRAM (Ferroelectric random) access memory combines fast read/write access nature of Dynamic RAM (DRAM) with the ability to remain non-volatile and ultra low power consumption (compared to EEPROM and FLASH). In spite of the name, FRAM is not affected by magnetic field because there is no ferrous (iron) material present in the chip. FRAM is being used in several applications especially in space industry because of the robust nature of FRAM compared to other two memories i.e. FLASH and EEPROM , as shown in table-1; one can easily get the idea of optimal reliability, speed, security and low power consumption of FRAM[1][5].

Table 1: Attributes of comparasion

Purpose of TMR Redundancy in OBDH

Since the TMR scheme will be deployed in the LEO Satellite OBDH system, the main OBDH driver is present in the FRAM that is controlling the overall operations of OBDH system and OBDH subsystem itself is collecting the monitoring data of all other subsystems using this driver. So it is much needed to regularly maintain the sanctity and correctness of driver data present in the FRAM, and here arise the concept of triple modular redundancy that is implemented through the development of this TMR test bench.

Hardware description.

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The Block diagram of whole TMR prototype test bench is depicted in figure-2; from the figure we can see that the test bench is divided in three sub blocks

Microcontroller block/Microprocessor block.

FPGA block

Memory block

Microprocessor/Microcontroller block

For the development of main test bench we have to use Microprocessor block, but for the sake of simulation we have used Microcontroller board instead of Microprocessor board. We are using PIC18f8086 for this test bench. The Controller is mounted on a female header over the main controller board, also the main board have six female headers on which level converter PCBs are mounted because FPGA and FRAM both are not tolerant to 5V Therefore level converter PCBs convert 5V to 3V and vice versa _______________________________________________________________________

FPGA Block

FPGA block is used between Microcontroller and FRAM blocks, because it is acting as a mediator to execute the developed combinational logic of voting circuit and error detector circuitry. The FPGA block is collecting the stored driver data from FRAM, and then checks the correctness of supplied data using the implemented combinational logic (Voting and error detection).

Combinational Logic implementation

As discussed above we have to design two logic circuits in FPGA, a voter circuit and an error circuit, so we start with the development of a "truth table", and then reduce the output expressions using "Karnaugh Map". The final step would be the implementation of logic from the simplified output expression and execution on FPGA using Verilog code.

Truth Table:

A

B

C

V

E

0

0

0

0

0

0

0

1

0

1

0

1

0

0

1

0

1

1

1

1

1

0

0

0

1

1

0

1

1

1

1

1

0

1

1

1

1

1

1

0

Figure 3 : Truth table showing logic states of the voter and error circuit

Figure 3 shows the output of the voter (V) and error circuit (E) for all the possible input conditions (A,B,C). The voter circuit produces the correct output by checking majority input arrivals i.e. the output over which two or more systems producing same output, if any of them disagrees the error circuit depicts the error by producing a high.

The simplified expression for voter circuit is:

V = AB+BC+AC-------(1)

The simplified expression for error circuit is:

E = A B + A C + B C--------(2)

FPGA acquires three input control Signals alongwith bidirectional Read/Write (data) signal from controller board , while 27 Pins of FPGA are being used to connect 8-bit I/O data pins and 3 control pins to each of three FRAMs.

Memory Block

Memory block consist of 3 FRAMs, each comprising of 512KB memory size. Memory block is taking common control signal from FPGA and for each memory chip a separate data bus is interfaced with FPGA. The common control signal generated by FPGA is controlling the read/write operation of three memory blocks. The main memory board comprises of three female headers over which three FM22L16 FRAMs are mounted.

Figure 2: TMR Design

Software and Program Description

Again consider here the picture shown in Figure-2. The processor module and FPGA module require firmware driver and verilog code design respectively. Flow chart of software description of Firmware is elucidated in general flow diagram in figure-5. In this algorithm, Processor unit (controller unit) initializes its variable and waits for data packet through serial port from PC As soon as the controller gets the command data from Computer, and decides whether it is a read command or a write command? Suppose if finds it a read command from computer then processor unit generates read, write and chip select control signals and sends them to FPGA for reading of data from the specified locations defied in the read command from PC. The data packet that was sent from PC contain information about start of packet, command of operation , starting address from where data would be started to store in memory or read from memory, length of memory addresses to be read from FRAM, data bytes (for write operation) and terminator(Packet End) ad shown in figure-4

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START

Initialization

Condition

Read Command

Write Command

Wait for

Input Data

Figure -5: General Flow Chart for Firmware demo

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Figure 4: Data packets for write and read operation

TMR operation is done during the read cycle of operation. A verilog code is implpemented for TMR operation of the design logic i.e.; for read operation data coming from all three memories are gathered in FPGA which then are compared amongst each other by performing bit wise comparison as defined in equation (1) and (2) and transfers correct data to processor unit, which then sends the result to Computer display. In case of write operation, FPGA will acquire data from processor unit and simply store at particular memory location.

Write cycle comparison

A functional simulation using Verilog is shown in figure-6, it can be seen from figure 6 that for write cycle the transmission delay of FPGA is nothing and we could be deceived from the response that transmission delay is zero.

Figure 6: FPGA functional simulation of write cycle where as in figure-7 (timing simulation) it can easily be seen that the transmission delay is 9050 ps (9.05ns).

Figure7: Verilog Timing simulation of write cycle

Read Cycle Comparison

Similarly for read operation of functional simulation no transmission delay is shown in figure 8. where as in timing simulation of Read cycle operation the delay produced by FPGA is approx 9797ps (9.7ns) as shown in figure 10

Figure8: functional simulation of read cycle

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Figure10: timing simulation of read cycle

Conclusion.

In this paper we have developed an FRAM based TMR testbench for testing the sanctity of OBDH driver present in FRAM, each FRAM contains the same driver data , this testbench checks the correctness of OBDH driver data in FRAM block and if found that any of the input provided from three input systems (FRAMs) is different than other two inputs, it halts the controller and alarm for false input present at any one of the input, then it takes the correct driver data from last saved driver information at some other memory location and put the data on false founded address locations of FRAM, thus giving us a way of rectifying an error and smooth operation of driver data. The main combinational logic for checking the data is implemented using FPGA based voting and error detection mechanism. The PIC controller block was used to collect the testing commands from PC. This paper provides a suitable and simplest architecture of TMR of memory module that could be used in radiated space environment and also implication of FPGA in a triple modular system (TMR) makes it possible to implement a fault tolerant technique of "majority" voting system, error detection and correction and still maintain fast read write cycle of FRAM easily as well. From the analysis of above functional and timing simulations provide the proof that the transmission delay of FPGA is Much less then memory access time which is 55ns [5],[6],[7] maintain TMR operation and fast read write cycle performed accurately and correctly by this TMR design.