FPGAs Systems Hardware

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RLSI Essay: Systems Engineering with FPGAs


Field Programmable Gate Arrays (FPGAs) have come up as a very practical technology for designing and prototyping of digital systems. Re-programmable gate array introduced as an entirely new approach to computing. Their arrival changed the perception of hardware as the rigid counter-part of flexible software. In this essay we have discussed system engineering with FPGAs, its relevant issues and the methodology associated with it.

Key Computing Challenges

The key challenges faced by the industry to provide high performance computing solutions as discussed in the lecture were

Obsolescence - The main cause of obsolescence in any electronic sector is the decreasing introduction time between successive iterations of applications. Global competitiveness and the financial benefits of manufacturing components for the high volume electronics industries is also one of the reasons.

Implementation: cost/time to implement applications - there is a direct proportion between the complexity and the development effort of the product, where the effort in the development increases exponentially with complexity. Also the development time must reduce to cope with the time-to-market. Hence the development platform must be flexible enough to adapt to changes in specifications without losing on the time factor.

Power Consumption, Size/weight - it is quite difficult for a designer to constrain size, weight and power consumption and at the same time accelerate development.

Performance - the rising demands for large-scale increases in computing performance are difficult to meet.


FPGAs (Field Programmable Gate Arrays) have grown from a device that was primarily used for glue logic to a large capacity device that is applied to a multitude of applications that use it as a computing processor to a fully system integrated solution.

FPGAs are capable of implementing sequential as well as complex combinatorial logic and are considered as an alternative to custom integrated circuits. FPGAs have an array of programmable logic components called “logic blocks” and programmable interconnects. The FPGAs have a large number of input-output (I/O) pins which fit in as a complete row or column in the arrays. The newest FPGA technology provides multi-gigabit I/O signalling with speeds up to 6.5 Gbits/s for a differential pair. These technologies use PCB and connectors to overcome the signal degradation. Coarse-grain and fine-grained are the two kinds of FPGA architectures; based on the logic block complexity. The difference between these two architectures is, coarse-grain architecture has complex blocks in smaller numbers while fine-grain architectures have large number of simple blocks. The latest development is to form a complete "system on a programmable chip” which combines coarse grained FPGAs along with microprocessor and relevant peripherals.

But recently in order to achieve increased performance 6-input LUT are being used. The CMOS technology currently used is 65nm; this reduction in size means more gates, more I/O and more features.

An HDL (Hardware Descriptive Language) is used to define the behaviour of the FPGAs. In order to accomplish faster design cycles for FPGAs languages like SystemC, System Verilog, etc that combine concurrency models with high level languages are being promoted by leading manufacturers.

The Application specific integrated circuits (ASICs) are a bit faster than the FPGAs. The unit cost of the FPGAs is more than that of the ASICs. But the FPGAs are more cost effective than the ASICs as there are no NRE (non recurring engineering) costs. Also they have a shorter time to market with an added advantage of reprogram-ability to fix any bugs even after manufacture. The FPGA reinitializes itself every time power is applied; this feature enables it to make the relevant changes in case it is reprogrammed.

There are various design challenges with the FPGAs; the Nallatech and other tool suites reduce the design effort involved. A few of these challenges and their solutions is given below

  • Interface with various peripheral devices - Library of optimized IP cores delivers consistent and reliable user interface to all peripheral devices
  • Communicate between algorithmic blocks and across multiple FPGAs - Use DIMEtalk to quickly build and adapt a proven communications network across multiple FPGAs and to processor.
  • Efficiently develop and implement algorithms - Select from leading 3rd party FPGA programming tools or Nallatech's C-to-VHDL function generator.

FPGAs provide a wide range of applications which includes digital signal processing, software-defined radio, aerospace and defence systems, ASIC prototyping, medical imaging, computer vision, speech recognition, cryptography, bioinformatics, computer hardware emulation etc.

Systems Engineering

An interdisciplinary approach that encompasses the entire technical effort, and evolves into and verifies an integrated and life cycle balanced set of system people, products, and process solutions that satisfy customer needs. (EIA Standard IS-632, Systems Engineering, December 1994). It helps build the final product or service as closer to the perceived need as possible. Systems engineering is fundamentally related, not just with the technical aspects but also to the management side of the project. The basic problems of any faction of engineering are complexity, communications and understanding. Systems engineering addresses these problems by adapting to a methodology which minimises complexity, increases effective communication and understands the system along with its environment.

The design methodology chosen in the system engineering process must consider the following,

System Level Analysis Required

At this stage technical as well as management considerations are made to evaluate factors like progress, selecting alternatives, and document data and decisions. Here decisions regarding various trade-offs and alternative advancements best suited for the main objectives are taken.

Design re-use

With progress in technology there is an increase in the complexity of designs. With time to market getting shorter by the day there is a need to reduce the product cycle time and the associated cost. Therefore it becomes necessary to reuse pre-defined designs. This helps reducing the design cycle which saves precious time.

Hardware/Software co-design

The Hardware/Software co-design is a very important aspect in terms of estimating the system performance in FPGA systems. To provide an optimum hardware software partition is the main purpose of the Hardware/Software co-design. This ends up in deciding the cost and performance of the target system.

DFT (Design for Test)

In order to overcome the difficulties, design engineers tend to add some testability features that could ease the design validation. This way the design engineers can make sure that there are no defects, affecting the functioning of the product. DFT plays a vital role in the development of test programs and as an interface for test application and diagnostics.

Top-down design Methodology

In the Top-down approach we consider the system as a black-box. We understand all the issues before going into detail. Specification of subsystems is then done. Once the subsystems are specified each subsystem in dealt individually in depth. This process goes on till the most basic elements are labelled.

Bottom up and middle out designs are not favourable for FPGA systems since environmental factors often overlooked, economic factors often overlooked, show stoppers found late in design. But in practice Top-down approach is used with a bit of bottom-up.

System Partitioning

The system partitioning process is a very important process in systems engineering with FPGAs, for any form of engineering for that matter. Here for software/FPGA systems early definition of the partition is quite necessary. This process requires experts in each field of partitioning to discuss possibilities. Allocation of system functionality to various hardware and software resources is carried out in this process. When a system is partitioned, scheduling is necessary for exclusive access to the shared resources. This needs robust communication architecture. Designing a suitable infrastructure considering all possibilities is one of the main goals of the system partitioning process. Getting this wrong is very costly and time consuming.

Nallatech Applications- FHPCA ‘Maxwell'

The motivation behind Maxwell was to check if the FPGA hardware can support standard HPC applications regarding it as the primary compute platform. The Xilinx Virtex-4 devices in Maxwell are of two types namely XC4VFX100 parts are on the Alpha Data cards while XC4VLX160 are on the Nallatech cards. Maxwell uses Xeon-based rack servers. It uses Linux variant CentOS and all standard Gnu/Linux tools. There are various libraries used like MPI, BLAS and SCALAPACK to built ‘legacy' software. It offers Sun Grid Engine as a batch scheduling system and MPI for inter-process communication. Initial performance results show that it has not suffered too badly from its ‘general purpose' nature, and indeed suggest that ‘general purpose FPGA computer' is at least not an oxymoron!


Writing this essay was a very good experience. It was quite interesting and difficult than I thought. The lecture on “Systems Engineering with FPGA's” by Malachy Devlin helped a lot. I have discussed the points from the lecture slides which I believed were important.


1. Maxwell - a 64 FPGA Supercomputer: http://www.fhpca.org/download/RSSI07-Maxwell.pdf




3. http://ieeexplore.ieee.org/iel5/7722/21171/00982673.pdf?tp=&arnumber=982673&isnumber=21171

4. FPGA Design Methodology for Industrial Control Systems—A Review


5. http://en.wikipedia.org/wiki/fpga

6. http://en.wikipedia.org/wiki/DFT

7. http://en.wikipedia.org/wiki/systems_engineering

8. http://en.wikipedia.org/wiki

9. Electronic Components Obsolescence

Lloyd W. Condra, Amir A. Anissipour, Dennis D. Mayfield,

and Michael G. Pecht, Fellow, IEEE


10. Trusted Design in FPGAs


High-Performance FPGA's,Brian Von Herzen.

12. Enhancement of Hardware-Software Partition for Embedded Multiprocessor FPGA Systems