Fpga Based Control Model With Derivative Filter For Converter Computer Science Essay

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In this paper, the control model for a digitally controlled DC-DC converter is presented along with derivative filter. The digital implementation of this model gives the detailed description about the gain and phase responses of each block in the digital controller loop. Key problem such as quantization resolution of digital pulse width modulator (DPWM), steady state limit cycle oscillations and loop delay of the controller are discussed and presented the corresponding solution. The controller is implemented in an altera Quartus II 9.0 tool and simulated with an inbuilt simulator. It is observed that the controller utilizes less resource and consumes less power, means that the cost of the controller can be reduced.

Index Terms-DC-DC converter, digital controller, DPWM, quantization resolution, loop delay.

INTRODUCTION

In recent years, DC-DC switched mode power supplies (SMPS) has been extensively used in various products. Because of its simplicity, most of the SMPS are operated with analog circuit controllers. Until now analog feed back control techniques show good performance in low power and high frequency SMPS. For instance, for a 100 MHz SMPS, 80% peak efficiency, 20 MHz regulation bandwidth is presented in [1]. But, considering the future trends of large size of components, lack of flexibility, low reliability, lower output voltage, downsize, and lower power losses. In addition, it is difficult to design control algorithms with high performance by using the analog control method[2]. Because of this high frequency digital control techniques will be considered more important. Using digital controller would have so many merits: reducing analog parts, space, and more easy of tuning the control parameters, avoiding uncertainties of parameters in analog devices and lower power consumption[3].

Recent publications [4-7] show that the implementation of digital controllers for low power SMPS is a feasible alternative to analog solutions. They demonstrate novel low-power hardware-efficient architectures that can support operation at switching frequencies exceeding tens of MHz [6].They have inherently lower sensitivity to process parameter variations. High frequency digital pulse width modulation can largely reduce the passive component size for miniaturization of portable electronic equipment demanding down-size, smaller and lighter weight power supplies. Therefore, digital control systems are less susceptible to environmental variations. Consequently it is possible implement more sophisticated control schemes that are impractical in analog consideration.

In this paper, key problems such as quantization resolution, limit cycle and loop delay are addressed. Attention is given to fast analog-to-digital converter (ADC) and high resolution DPWM which are necessary to improve the performance of the controller. In small-power DC-DC converter most of the controllers are PID controllers due to cost/complexity constraints. The organization of this paper is as follows: In section II, modeling of the DC-DC converter in two modes is presented. The classical digital PID controller is discussed in section III. In section IV the key issues about the design of digital controlled DC-DC converter such as quantization resolution, limit cycle and loop delay are discussed and the corresponding solutions are proposed. The simulations results are presented in sections V to verify the performance of the converter.

MODELING OF DIGITALLY CONTROLLED DC-DC CONVERTER

Fig. 1 shows the circuit level implementation of digital controller algorithm with DC-DC converter as a closed loop circuit. The digital controller embedded within the Field Programmable Gate Array (FPGA) senses the output voltage through the ADC. The output voltage is then filtered using a moving average filter [8] and converted it into digital form using ADC and compared with the reference voltage in the FPGA. The voltage difference results in an error signal. The Proportional Integral Derivative (PID) compensator generates the corresponding duty cycle based on the error signal. The high frequency DPWM generates control signal which is fed back to the analog circuit, which is the dc-dc converter.

There are two state variables in the converter: inductor current IL and capacitor voltage VC. In our design since converter operates in continuous current mode (CCM) and hence converter operates in two modes.

Fig. 1. Block diagram of digital controlled DC-DC converter.

The state space equations for each mode are described as follows:

Mode 1: Switch is on, Diode is off

The input voltage Vd is connected to L, the state variable equations for the circuit are

(1)

(2)

Mode 2: Switch is off, Diode is on

The input voltage Vd is disconnected from L, the inductor current flows through load and diode. The state variable equations are

(3)

(4)

The output voltage Vd is given by

(5)

DESIGN OF DIGITAL CONTROLLER

The block diagram of control model of a digital controller with dc-dc converter under closed-loop condition is shown in Fig. 2. There are four major blocks in the system: dc-dc converter, ADC, digital PID controller and DPWM.H is the output voltage gain controller block. The models of the major blocks are described as fallows.

ADC Block:

The transfer function of the ADC in continuous time domain is

(6)

Where KADC is the gain, where n is the number of bits, TADC is the conversion time of ADC, is the sensing voltage of the ADC. The values of TADC, n, can be found from data sheet.

Digital PID Controller Block:

The general format of the continuous-time PID controller can be expressed as

Fig. 2. Control model of a digital controller with dc-dc converter.

(7)

Where Kp = proportional gain, Td = derivative time constant, Ti = integral time constant, e(t) = error signal, u(t) = output of the controller. The (7) is not adopted in practical cases because of few problems with derivative action and reference signal weighting, which are explained below.

i. Problem with derivative action #1:

Let us consider a measured noise is a sinusoidal signal given by the equation

(8)

Where A is amplitude of the noise, w=2πf, f=frequency of the noise. If the derivative action is only considered in the controller then the output of the controller is

(9)

Where KdAw is the amplitude of the controller

Equation (9) shows that the derivative action is responsible for the amplification of the noise, means that when the frequency of the noise is high the amplification effect is high. In practical cases a very noisy control variable can cause damage to the actuator. This problem can be solved by filtering the derivative action with at least first order low pass filter.

ii. Problem with derivative action #2:

When a stepwise change in the reference signal occurs, due to the very large derivative action a spike appears in the control variable known as derivative kick, which is undesirable. A simple solution to avoid this problem is to apply the derivative action only to the process instead of the control error [9]. With only the derivative action without filter u(t) becomes

(10)

Where e(t)=Vref(t)-Vo(t) with no reference signal Vref(t) becomes zero and e(t)=-Vo(t) hence (10) becomes

(11)

It is worth noting that when the reference signal is constant applying the derivative term to the error signal or to the process variable is same.

iii. Problem with reference signal weighting:

A typical problem with the design of a feedback controller is to achieve at the same time a high performance both in reference signal and in the load disturbance rejection performance. But with a high gain controller a fast load disturbance rejection can be achieved, which gives an oscillatory reference signal step response on the other side. This problem can be achieved by weighting the reference signal for the proportional action of the PID controller as shown in Fig. 3, i.e. to define the proportional as in (12).

(12)

Where the value of β is between 0 and 1.

Fig. 3. Reference signal weighting for the proportional action Kp.

To overcome all the above said problems (7) has to be modified as (13) is known as ISA-PID control law [10].

(13)

Where Vref(s), Vo(s) and u(s) are the Laplace transform of the reference converter output and control signal respectively. Kp is the proportional gain, Ti is the integral time constant, Td is the derivative time constant, N is the ratio between Td and the time constant of additional pole introduced to assure the performance of the controller. Parameters β and γ are called reference signal weights and constitute a simple way to obtain a 2-DOF (degree-of-freedom) controller. As their choice does not affect the feedback properties of the resulting controller with no loss of generality we have assume β=γ=1. The transfer function of the controller is given by

(14)

Effect of Derivative Filter on PID Controller Action:

It is interesting to evaluate how the presence of a derivative filter changes the location of the zeros in the PID controller. That is with the filter applied to the PID controller does not alter the position of the zeros of the controller. To explain this let us consider the transfer function c(s) of the controller in it's ideal form without filter

(15)

The zeros of the (15) are the solution of the equation

(16)

Let z1,2 are the zeros of the equation, they can be derived as

(17)

Let zf1,2 are the zeros of the solution of the equation with filter, they can be derived as

(18)

In order to evaluate the influence of the derivative filter parameter N on he location of zeros a sensitivity analysis [11] can be performed as follows.

The relative perturbation of the ith zero can be calculated as

(19)

It can be seen from the Fig. 4 that the relative error is greater than or nearly equal to 30% and a high value appears when Ti=4Td or Td/Ti =0.25. i.e. when the two zeros are real and coincident.

Fig. 4. Relative error due to zeros z1 (above) and z2 (below) with derivative filter for various N.

Implementation of Digital PID Controller:

We cannot implement continuous-time PID controller directly in an FPGA, it is necessary to approximating continuous-time into its digital equivalent. In the literature several methods have been proposed to do so, but in this paper we proposed to use Bilinear Transformation (BLT) method or Tustin's approximation [12] since it is simpler and gives better approximations of continuous-time.

(20)

Substitute (20) in (14), we get

(21)

To implement (21) in FPGA first covert it into time domain using inverse z-transformation with, we get

(22)

Where u(n) is present output and e(n) is present error input of the controller, u(n-1) to u(n-4) and e(n-1) to e(n-4) are the past values of the output and error input of the controller respectively.

Realization of Digital PID Controller:

Different realization techniques are discussed in [12], we have used direct-form I realization [13] to realize fourth order Fast IIR filter in its look-ahead interleaving time domain mode [14] as shown in Fig. 5 it consists of nine multipliers, four delay elements and five adders block.

Fig. 5. Direct-form I realization of PID controller.

Where b0=44.43, b1=-114.41, b2=199.95, b3=-154.38, b4=24.4 and a1=-4, a2=-6, a3=-4, a4=-1

DPWM Block:

The transfer function of leading edge DPWM is

(23)

Where KDPWM =1/2q is the gain, where q is the resolution of DPWM, TDPWM is the delay time of DPWM which is normally equal to one clock cycle of FPGA and DTs is the on-time of the converter.

Converter Block:

The converter model includes the control to output transfer function [14] Gvd(s) is

(24)

Where,,

Overall Transfer Function:

The overall transfer function in s-domain is

(25)

On substituting (14) and (24) in (25), we get

(26)

Where Tloop =TADC + TPID + TDPWM + Tdriver+ DTs (27)

Tdriver is the delay time of gate driver.

QUANTIZATION RESOLUTION, LIMIT CYCLE AND LOOP DELAY

ADC is required to convert output voltage into it's digital form, to control the switch in the converter at the computed duty ratio a digital pulse-width modulator (DPWM) is required. The DPWM serves as a DAC in the control loop. In order to obtain a precise output voltage, a high resolution of ADC and DPWM is required. So, it is of interest to examine the required resolution of ADC and DPWM. The resolution of the ADC has to enable error lower than that the allowed variation of the output voltage. ΔVo [15].

(28)

Where = output voltage gain

Vref =reference voltage

Vo = output voltage

ΔVo = ripple voltage

n = The resolution of the ADC

ΔVADC = Maximum allowable output voltage of the ADC

On simplification, the required resolution of the ADC given by

(29)

Where n takes the upper rounded integer value. Supposing that the value of the n is of higher value, which requires even more higher resolution of DPWM. If DPWM resolution is not high enough, the output voltage will not be well regulated in a satisfying manner. Thus higher resolution is necessary and consequently it requires higher clock frequency fclock of the FPGA. In order to achieve n-bit resolution at the switching frequency fclk, the clock frequency of the FPGA must be equal

Fig. 6. FPGA clock requirement for various switching frequencies.

to fclk/Dq, where Dq is duty cycle resolution of the digital controller quantized to several values. In Fig. 6 the clock frequency requirement of FPGA to achieve 3 mv output voltage resolution for different switching frequencies with constant input voltage of 12v is shown. As we can observe in the graph, even for 500 kHz switching frequency, clock frequency has to be 2GHz to meet the resolution requirement. This leads to more difficult timing constraints and implementation of such DPWM becomes impractical due to large power consumption. The situation becomes even worse when switching frequency goes higher and higher.

If the resolution of the DPWM is lower than the resolution of ADC, there will be no DPWM level that matches the ADC value for the reference voltage. The ADC value at this instant will be referred to as zero-error value. This means that, in a steady state the feedback controller will attempt to track to the zero error value. If the desired output voltage value does not belong to one of the value of DPWM levels, the controller will switch among two or more levels of the DPWM around the zero-error value. This leads to a non-equilibrium phenomenon known as steady-state limit cycling [16].

The effect of overall loop delay Tloop of (27) on the control-to-output transfer function is shown in Fig. 7.

Fig. 7 Effect of Tloop on control-to-output transfer function.

SIMULATION AND FPGA IMPLEMENTATION RESULTS

Simulation Results

The model was verified using matlab 7.6 simulation tool. It is infeasible to simulate the transfer function of each block, because some blocks (for example, in ADC block the input is analog and the output is digital) cannot be measured individually. The occurrence of limit cycle oscillation in the output voltage because of the resolution of DPWM (7-bits) is less than the resolution of ADC (8-bits) is shown in Fig. 8. Similarly no limit cycle oscillation in the output voltage with the resolution of DPWM (10-bits) is greater than the resolution of ADC (8-bits) is shown in Fig. 9. In Fig. 10 the Waveforms of o/p voltage, inductor current and PWM pulses are recorded. .

Fig. 8 Limit cycle oscillations in the o/p voltage with ADC resolution = 8

bits and DPWM resolution = 7 bits

Fig. 9 No Limit cycle oscillations in the o/p voltage with ADC resolution = 8

bits and DPWM resolution = 10 bits

Fig. 10 Waveforms of o/p voltage, inductor current and PWM pulses

FPGA Implementation Results

Having obtained the discrete time equation, now our focus is on its implementation. In this work we have implemented (22) using Altera FPGA. In this FPGA, First the controller was implemented using VHDL language with Altera Quartus II 9.0 as a foundation tool [17] and logic synthesis was carried out to optimize the design and the placement and routing were carried out automatically to generate the FPGA implementation file i.e. sop file. The file is targeted to a Altera Cyclone EP1C12Q240C8 with a speed grade of 8. The output response of PID controller with filter to a step input of 3V is shown in Fig. 11. The timing analysis and resource utilization summary are shown in Fig. 12 and Fig. 13 respectively. The FPGA takes 20.053ns to process and consumes 80mW of power with a clock frequency of 48 MHz.

Fig. 11 Output response of PID controller with filter to a step input of 3V

Fig. 12 Summary of timing analyzer

Fig. 13 Analysis and synthesis resource usage summary

CONCLUSION

In this paper, the control model of a digitally controlled dc-dc converter is presented. The model gives the detailed time delays due to the digital implementation of the PID controller with derivative filter. The effects of quantization, limit cycle oscillation and loop delay on the output have been analyzed and to minimize them the necessary conditions are proposed. The digital PID controller is implemented on altera FPGA using Fast IIR filter in its look-ahead interleaving time domain mode. The results for power consumption, speed, and number of logic elements used by the controller are recorded.

It is observed that the controller utilizes less resource and consumes less power, means that the cost of the controller can be reduced.

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