Fpga Based Cascaded Multilevel Single Phase Inverter Computer Science Essay

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This article describes pulse width modulation based Field Programmable Gate Array controller algorithm for cascaded multilevel single phase inverter fed adjustable speed of induction motor drive applications. The cascaded inverter is constructed by the conventional of three full H-bridges for reduce the output of harmonic content. In PWM voltage source inverter should maintain the variation of both voltages to frequency simultaneously and keep their ratio constant for control of speed. In this investigation focus a simple novel control circuit is adopted using FPGA devices for the hardware implementation. It can be accommodated in a single chip that provides high computation speed that facilitates producing accurate control signals for higher output voltages and currents with fewer harmonics. VHDL language is used to model the inverter switching strategies. The proposed controller generates 12 control signals to cascaded multilevel inverter switches for 7- level output voltage. Matlab/System generator and XILINX are used with hardware-co-simulation and compiler architecture of control circuit embedded in FPGA.

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Pulse width modulation technique based cascaded multilevel inverters has been focus of important research in electrical systems and many significant improvements in the past few years. These power converters design implementation depends on application and power levels [1]. The literature covered three main types of transform less multilevel inverter topologies; flying capacitor inverter, diode clamped inverter and the cascaded H-bridge inverter. Among these inverter topologies, the flying capacitor inverter is difficult to be realized because each capacitor must be charged with different voltages as the voltage level increases. Moreover, the clamped inverter also known as a neutral clamped converter is difficult to be expanded to multilevel because of the natural problem of the DC link voltage unbalancing. The cascaded has the disadvantage to need separate dc sources, due to these cascaded inverter has been widely applied to such applications as HVDC, high-power motor drive, variable speed drive, UPS and APLC and so on [2-4]. Mostly analog devices used to implementing PWM control schemes for switching strategies and it's requiring a high sampling rate for wide-bandwidth performance and more complexity. To overcome these problems digital control techniques are becoming the most widespread resolution in modern power electronics controllers. The microprocessors, DSP processor and application specific integrated circuits (ASIC) are responsible for better performance of the power converters [5]. Yet the design of digitally controlled power electronics is affected by several problems, such as sampling rate, software portability, re-usability, peripheral devices, complicate design and register settings specific for each microprocessor. Suppose change of the microprocessor or the need of better performance requires a huge revision of the project in order to fit with the new system. These problems can be mitigated by Field Programmable Gate Array circuits (FPGA) designs [6].

Very large scale integration (VLSI) technology and electronic design automation (EDA) techniques are created an opportunity for the development of complex and compact high-performance controllers [7]. FPGA is a programmable logic device (PLD), compressing thousands of logic gates in a single chip and some of them are combined to form a configurable logic block (CLB). The FPGA benefits of using portable high level hardware description language (HDLs) to encompass the holistic modeling of industrial FPGA design environment that allows concurrent operation, minimizing the time, easy and fast circuit modification and low cost for complex circuitry. Maximizing operational performance in order to achieve high efficiency and power quality while simultaneously allowing the rapid prototyping of digital controller makes it an ASIC [8].

This article investigated the proposed a novel FPGA based control algorithm for 7-level cascaded multilevel single phase inverter fed adjustable speed of induction motor drives. The output of the inverter is controlled by sinusoidal PWM techniques. The modulation index can be varied by changing the amplitude of the reference signal and the ratio of voltage to frequency is maintained constant for speed control of motor drives. The proposed FPGA controller algorithm has provided better modulation index range and reduces harmonic content. This controller experimented with Xilinx/SPARTAN3E device FPGA board using hardware-co-simulation.

Cascaded multilevel inverter topology

A cascaded multilevel inverter is constructed by the conventional of H-bridges. Three H-bridges are connected in cascaded method for 7-level output voltage in the single phase inverter. Each H-bridge is connected a battery or fuel cell for dc supply source and the output voltage is as shown in fig 1. The cascaded multilevel inverter connected with resistive and inductive (RL load) load instead of induction motor. Sinusoidal PWM technique is used for generating gate pulses for drive the inverter switches and the output of the inverter fed the motor. The SPWM is most widely used method of voltage control inverters for motor drive applications.

Vdc

G1

G2

G3

G4

G5

G6

G7

G8

G9

G10

G11

G12

Vdc

Vdc

R

L

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Fig 1 Cascaded multilevel PWM single phase inverter

The cascaded multilevel inverter switching operation is performs by sinusoidal pulse width modulation technique based FPGA digital controller. The PWM based cascaded inverter applies to motor control is a way of delivering energy through a succession of pulses rather than an analog varying signal. By increasing or decreasing pulse width, the controller regulates energy flow to the motor shaft. The motor's own inductance acts like a filter storing energy during the ON cycle while releasing it at a rate corresponding to the input or reference signal. The widths of the pulses depend upon the amplitude of reference sine wave; if amplitude is increased width also increase. The ratio of reference signal amplitude such as sinusoidal waveforms and carrier signal amplitude such as sawtooth waveforms is called modulation index. It's defined as

Here adjust the modulation index; we can control the output of the inverter. The modulation index can be varied by changing the amplitude of the reference signal. The rms value of the output voltage inverter depends upon the width of the pulses, it's given as

Here the number of pulses p (per half cycle) depends upon frequency of the carrier. It's given as

Here is frequency modulation ratio. The sinusoidal pulse width modulation (SPWM) eliminates all the harmonics less than the dc source for the in case of p=3, the lowest harmonics present will be (2x3-1) =5, thus 2nd, 3rd, 4th harmonics will be absent. Thus it's desirable to use more number of pulses to eliminate more harmonics. But more number of pulses increases the switching losses in the devices; hence the optimum value of the pulses is selected.

The cascaded multilevel inverter output voltage of the first, second and third H-bridges are denoted by V1, V2 and V3 respectively. So that the output voltage of the converter is written as

By ON and OFF the switches of first H-bridge output voltage can be made equal to, and Similarly the second and third H-bridge output voltage can be made equal to, and Therefore, the output voltage of the inverter is a combination of first, second and third H-bridge supply source

The proposed FPGA based controller algorithm for 7-level fundamental switching scheme topology to regulate the voltage and to guarantee the output power quality. This switching scheme uses a possible cycle output ,,,,, and voltage levels. In 7-level fundamental frequency switching control is a good method for the hybrid cascaded H-bridge single phase multilevel inverter. The switching signals and output voltage are shown in table 1.

Table 1 Gate switching signal for cascaded multilevel inverter

SA

SB

SC

SD

Sa

Sb

Sc

Sd

output

0

1

1

0

1

0

0

1

0

1

1

0

1

0

1

0

0

1

1

0

0

1

1

0

0

0

0

0

0

0

0

0

1

0

0

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

0

1

0

1

1

0

proposed FPGA based SPWM controller

The proposed block diagram shown in fig 2, the FPGA controller based cascaded multilevel inverter fed adjustable speed drive induction motor. The desired reference value or required speed rpm value applied to the analog to digital converter (ADC) for design the digital FPGA controller. The digitized fixed reference speed value 1500 is multiply with gain 1.666 for set the amplitude 2500 V. The digitized fixed reference speed value again involves the accumulator operation for set the frequency range. Here the 16-bit up-counter compared with 16-bit constant value for generate pulse signal to run the enable port of 16-bit accumulator. The result of accumulator is generating sawtooth frequency and it's divided by 8-bit shifter and also recovers to accumulator reset port through feedback loop connection. The feedback loop is makes the amplitude and frequency ratio constant. The frequency range directly committed with 14-bit ROM device and also 1800 phase shift operation for generate two sine signals. The 14-bit ROM output of frequency sine signal adds with amplitude and it makes the ratio constant. This V/F ratio is controls the output voltage of the cascaded multilevel single phase inverter.

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Diode bridge rectifier

Cascaded single phase inverter

Adjustable speed IM

ADC

Amplitude and Frequency setting

Sinusoidal PWM controller

Reference Speed rpm

Matlab/Simulimk

[Xilinx Block set]

AC

CDC

3-Carrier signals (sawtooth signals)

System generator

Gate signal generator

Design synthesis and Implementation

VHDL program code

Verification and Xilinx device programming

FPGA chip

12-channel signal

Opto isolator and Driver

Xilinx/Spartan3E

FPGA controller

Reference signal generator (sine and inverse sine signal

(Or)

Fig 2 proposed block diagram of FPGA controller based cascaded multilevel inverter fed adjustable speed drive induction motor

The three carrier signals (sawtooth waves) generated using up-counter design. The first sawtooth carrier signal produced from 20-bit up-counter and this output signals send to 1200 phase shift for second sawtooth carrier signals and 2400 phase shift for third sawtooth carrier signals respectively. The two reference signals, sine wave and 1800 phase shift sine wave separately compared with three sawtooth carrier waves for generate 6-gate signals. The widths of the pulses depend upon the amplitude of reference sine waves. The ratio of reference and carrier amplitude is called modulation index and its control the output voltage of the inverter. This is working as a sinusoidal PWM controller technique, so the references sine waves of frequency and amplitude can be easily adjust and vary the modulation index. The distribution unit of NOT gates deal with the 6-gate signals (produced from reference and carrier signals comparator) and it is generated the 12-gate signals [g1, g2, g3, g4, g5, g6, g7, g8, g9, g10, g11, and g12] for drive the cascaded multiple single phase PWM inverter. The digital controller can be tested and implemented to FPGA processor hardware in two different ways using system generator [9-10]; the proposed controller is verified both (1) Hardware-co-simulation and (2) ISE-iMPACT.

Hardware-co-simulation:

System generator provides the Xilinx/Spartan3e device FPGA hardware directly interfacing to run the design with the simulink. The compilation targets automatically create a bit stream file and dump to FPGA kit. When the proposed controller design is simulated, the compilation portion is tested successfully through the JTAG connection to FPGA hardware implementation in real time process.

ISE-iMPACT:

The VHDL program code generated from the system generator after verification and simulation of the control design. The VHDL program is synthesized using Xilinx-ISE 10.1 software. The ISETM (Integrated Software Environment) based FPGA design flow comprises the following steps:

1) Design entry - it should assign constraints such as timing, pin location, area constraints and user constraints (UCF) file.

2) Design synthesis- Synthesize the project design.

3) Design implementation- Implement the design which includes the Translate, Map, Place and Route.

4) Design verification- includes both functional verification (also known as RTL simulation) and timing verification.

5) Xilinx® device programming- Create a programming BIT file program debugging or to download to target device of XILINX/SPARTAN-3E processor kit, use iMPACT to program the device with a programming cable.

Once the programs dump to FPGA kit, it acts as a Sinusoidal PWM based FPGA controller and generate gate drive signals. These signals are connected to optoisolator circuit for preventing the ground sharing between the FPGA chip and H-bridge power module. The output of optoisolator is connected through driver to each switching devices for control the PWM single phase inverter.

result and analysis

The proposed cascaded multilevel PWM single phase inverter is simulated by using Matlab/Simulink® and XILINX simulation software. The simulink/Xilinx Block set is a powerful graphical modeling system which allows digital complex systems to be designed using a block diagram methodology. The system generator for which allows the modeling of digitized systems which can be transformed into VHDL code and targeted at a Xilinx/Spartan3e FPGA board. Automatic generation of the bit stream is supported with the synthesis and implementation tools run within the simulink as well as Xilinx environment; it is verified and tested both Hardware-co-simulation and ISE-iMPACT. The system is investigated by resistive and inductive (RL-load) loads. The waveforms of output voltage signals and load currents are obtained less harmonics and the simulated results are investigated and show satisfactory results.

The desired reference speed rms value is converting to digital fixed point for FPGA design. The digital reference value multiply with a gain 1.666 for set the amplitude and also involves the accumulator operation for set the frequency according to voltage and frequency ratio. The amplitude and frequency with 14-bit ROM device blocks are generates two reference sine signals and maintain the voltage to frequency ratio constant for control the output voltage of inverter. The fig 3 showed the sine wave and 1800 phase shift sine wave (inverse sine wave) as a reference signals. The pulse width of modulation index depends on the amplitude of the reference sine signal. So we can vary the modulation index, adjust the reference sine amplitude that control the output of the inverter.

Fig 3 sine wave and 1800 phase shift sine wave (inverse sine wave) signals generated from the amplitude and frequency.

The three carrier signals (such as sawtooth waves) generated using up-counter design. The first sawtooth carrier signal produced from 20-bit up-counter and these signals send to 1200 phase shift for second sawtooth carrier signals and the second sawtooth carrier signal send to another 1200 phase shift for third sawtooth carrier signals respectively. The fig 4 shown each sawtooth waves start from different amplitude and 1200 phase shift [sawtooth waves amplitude start from -2500 V, -800 V, and +900 V to +2500 V and 1200 phase shift frequency]

Fig 4Three carrier sawwtooth signals generated from up-counter and each signals have 1200 phase shift frequency.

The first reference sine signal compared with the three sawtooth carrier signals, similarly the second 1800 phase shift reference sine signal also compared with the same three sawtooth carrier signals. The two sine signals are separately compared with three sawtooth signals for generate 6-gate signals. The distribution unit of NOT gates deal with the 6- signals, that are generated the 12-gate signals for drive the IGBTs switches. The Very large scale integrated Hardware Description Language (VHDL) that can be used to model a digital system at many levels of abstraction, ranging from the algorithmic level to gate level with high degree of complexity. The PWM technique handles the reference sine signals according to the voltage to frequency ratio and carrier signals. The fig 5 has shown the decimal value and bit waveforms of ADC reference speed value, amplitude and frequency values, sine wave and 1800 phase shift sine wave (inverse sine) for reference signals, up-counter and 1200 phase shift up-counter and 2400 phase shift up-counter for carrier sawtooth signals.

Fig 5 VHDL behavioral simulation signals of ADC reference speed value, amplitude, frequency, sine wave, 1800 phase shift sine wave or inverse sine wave, sawtooth signal, 1200 phase shift sawtooth signal and 2400 phase shift sawtooth signal.

The 12-channel gate control signals generated from the comparison of two references sine signals and three carrier sawtooth signals. The VHDL program generated from the system generator block using simulink platform. The fig 6 shown 12-gates signals and according to the clock signals for drive the cascaded multilevel signal phase inverter for 7-level output voltage.

Fig 6 VHDL behavioral simulation signals of clock and 12-channel gate drive signals generated from PWM technique controller.

The VHDL program of 12-channel gate signal code executed and summarizes resulting synthesis of the System on Chip design shown in table 2. The speed performance of the device minimum period is 21.476ns (Maximum Frequency: 46.564 MHz) and maximum combinational path delay: 20.059ns. The selected target configurable device is 3s500efg320-4.

Table 2 summarized FPGA design synthesis report

Logic utilization

Used logic cells for cascaded inverter

Available logic cells

No of Slices

283

4656

No of Slices FFs

80

9312

No of 4 input LUTs

523

9312

No of bonded IOBs

200

232

No of BRAMs

2

20

No of MULT18x18SIOs

2

20

No of GCLKs

1

24

The experimental setup using hardware-co-simulation is shown in fig 7. The system generator is provides the Xilinx/SPARTAN3E device interface through JTAG chain and Xilinx programming USB cable to be able to program the FPGA. The JTAG options choose the boundary scan position is 1 and detect the IR length such as 6, 8 and 8. The platform USB cable speed is 12 MHz The compilation targets automatically create a bit stream file and dump to FPGA kit. This hardware co simulation system clock frequency is set 50 MHz at pin location C9. The proposed controller design is simulated and compilation portion is tested successfully through the FPGA hardware implementation in real time process.

Fig 7 Experimental setup using Hardware-co-simulation

The proposed sinusoidal PWM controller design is implemented to Spartan3e device FPGA board and tested using hardware-co-simulation. The FPGA board is generating 12-channel gate signals that drive the cascaded single phase multilevel voltage source inverter IGBT switches and produce 7-level output voltage as shown in fig 8. The output voltage levels are,,,,,and here each phase output voltage is Vdc=50 V. This proposed controller and suitable cascaded inverter topology claim less total harmonic distortion.

Fig 8 seven level output voltage of cascaded multilevel single phase inverter

The 7-level cascaded single phase multilevel voltage source inverter output current shown in fig 9. This topology provides nearly sinusoidal current waveforms that claim low distortion and less switching losses.

Fig 9 seven level output current of cascaded multilevel single phase inverter.

The Fourier analysis of the cascaded multilevel inverter output voltage signal manipulated one cycle of the fundamental frequency. The Fourier can be calculating the magnitude and the fundamental or any harmonic component of the signal, that a signal can be expressed by a Fourier series of the form

Where n represents the order of the harmonics (n=1 corresponds to the fundamental component). The fig 10 shown in cascaded multilevel single phase PWM inverter output voltage of order of the harmonic measured with respect to the fundamental frequency.

Fig 10 order of harmonic measured with respect to the magnitude of the fundamental frequency for cascaded single phase voltage source inverter

The cascaded multilevel single phase voltage source inverter of the total harmonic distortion calculated of a periodic distorted signal. The current and voltage of the THD is measured as shown in table 3.

Table 3 THD measured of the cascaded single phase VSI

THD

Cascaded single phase VSI

Voltage

19.31%

Current

3.854%

Conclutions

The FPGA based sinusoidal pulse width modulation technique controller switching patterns are adopted and applied to the cascaded multilevel inverter switches to generate 7-level output voltages. This controller design is simulated and compilation portion is tested successfully through the FPGA hardware implementation in real time process using hardware-co-simulation. The FPGA enables to make easy, fast and flexible design of the control circuit for hardware implementation. It can effectively adjust the modulation index range for varying speed control of induction motor drives. The effective controller maintains the voltage to frequency ratio constant. The experimental and simulation results demonstrate quality voltage and current waveform shapes with fewer harmonics at the output of the inverter. These inverter topologies with proposed control circuit can be used for speed control of induction motor and other industrial applications.