This essay has been submitted by a student. This is not an example of the work written by our professional essay writers.
The Double-Edge Triggered Flip Flop or Double Data Rate flip flop latches the data at both edges of the clock. Using this design, the data rate can be kept constant while frequency of clock can be reduced to half. This paper describes various designs of DETFFs, their working principles and its comparison with Single Edge Triggered Flip Flop (SETFF).
Index Terms-double edge triggering, dual data rate, flip flop, merged feedback, pulse triggered
FLIP flops and latches are used as elements of data storage in sequential logic. Edge triggered flip flops capture the input only at an edge of the clock. Input can be captured at rising edge (positive-edge triggered) or at falling edge (negative-edge triggered) of clock. Double-edge triggered flip-flop (DETFF) is a device that samples and stores the input data at both clock edges. A latch can be in storage state or input state depending on the high or low level of clock. If the device is in storage state, then the input path is switched off and the input data is lost. If the device is in input state, then the input signal is sent to the output terminals. In contrast, a Double-Edge Triggered (DET) flip flop processes two values in one clock period and hence it is used in Double Data Rate Synchronous Random Access Memory (DDR SDRAM).
Fig. 1. Input-Output Waveforms for a DET D-flip flop
DDR SDRAM is a class of memory integrated circuits used in computers. It is well-suited to notebook computers because it doubles the memory chip's data throughout and also consumes less power. It is also used in high-speed memory systems in workstations and servers. In addition, small DET flip flop can be used to build fast shift registers.
Efficient power consumption in conjunction with high-speed and complex functionality is the need of the hour which can be achieved with a DETFF. The DET flip flop reduces the clock frequency by half while keeping the input data rate constant. Hence dynamic power dissipation due to clock transitions can be reduced by half. Such a clock system with frequency halved can be used in low power applications.
The DET flip flop can be designed in various ways with a crude structure using a multiplexer and two D flip flops. A more efficient design using a single latch is also possible. Among others are the ones using merged feedback or a pulsed clock signal. Depending on the purpose and specifications of power and speed, appropriate choice is to be made.
CIRCUIT DESIGN USING MULTIPLEXER
(2) The state equations for a positive and negative level-sensitive latch can be respectively expressed as:
Qnext=D·CLK + Qnow·CLK
Qnext=D·CLK + Qnow·CLK
Fig. 2. Implementation using M1: 2-1 MUX, D1: positive-edge triggered flip flop and D2- negative edge triggered flip flop (Credits: )
(3)The multiplexer is described by the equation:
y=dos + d1s
At the positive edge of the clock, input is passed by D1 to its output Q and MUX selects the input line d1 as clock becomes high. Similarly, at the negative edge of the clock, input is passed by D2 to its output Q and MUX selects the input line d0. Thus, the device shown in Fig. 2. stores data at either edge- rising or falling edge of the clock signal and is a DETFF. However, it is recommended to avoid such a structure as the clock appears in the data path and can cause problems when doing the clock timing analysis .
SINGLE LATCH DETFF
A DET flip flop can be implemented using a single negative-edge triggered D-flip flop and an exclusive OR gate.
Fig. 3. Single latch DETFF (Credits: )
Fig. 4. Clock Driver Circuit (Credits: )
X and Y are generated by a clock driver circuit. The clock driver-the circuit is essentially a delay line for the clock signal X. It consists of an appropriate number of inverters according to the delay to be produced. The output of the XOR gate would be a constant 1 if there is no delay between X and Y. However, because of the delay between them, the signals X and Y are equal for a short period of time after each edge of the clock . The signal X Y is an asymmetric signal. If the delay is chosen correctly, consecutive falling edges of the signal X Y coincide with consecutive edges of the clock and hence, the input is transferred at every edge of clock.
Fig. 5. Comparison of power dissipation (Credits: )
A, B and C are sequences such that sequence A changes input at every rising clock edge. Sequence B changes input at every falling clock edge and sequence C is constant with few glitches in between.
Transistor level analysis shows that a total of ten transistors are required in the circuit not including those in clock driver. The delay between the signals X and Y should be sufficient to turn on the PMOS device Q5 and to allow the input D to charge or discharge through the first inverter G6 . In comparison to the MUX implemented DETFF, this device requires lesser silicon area and also has lower power dissipation which is illustrated by Fig. 5.
static and dynamic detff
The main drawback of DET flip flop is the increase in the number of transistors used. The following two circuits have been designed for maximum logic excursion, high-speed operation, and prevention of metastability and race problems for the static and dynamic circuits respectively . The number of MOSFETs used in the following circuits is less as compared to other designs of DETFFs.
Fig. 6. Static DET flip flop (Credits: )
Referring to Fig. 6., the block consisting of inverters IN1, IN2 and PMOS TR2 is a memory element which stores the value at CLK=T=0. Similarly, the lower memory block stores the value at CLK=1. When clock is low, NMOS TR3 is active and hence the value corresponding to upper memory block is passed to the output and the input value is written to the lower memory block. Similarly, when clock is high, NMOS TR6 is active, input is written to upper memory block and output is read from lower memory block. Thus, the input is transferred to the output at both edges of clock.
Fig. 7. Dynamic DET flip flop (Credits: )
The guiding principle behind static latches is the principle of regeneration. An input sent to the memory block of the static circuit (cross coupled inverters) would regenerate using the positive feedback of the loop. This state is retained until a new disturbance is introduced. In contrast, in dynamic circuits, the logic value is stored in the form of a capacitor .
The power consumed by the dynamic DETFF is much lower than that consumed by static DETFF at high frequencies of data input.
Fig. 8. Power Dissipation in the static and Dynamic DETFF
MERGED FEEDBACK DETFF
The above DET flip flops were constructed by either complete latches or flip flops or by minor optimizations to reduce the number of transistors. The philosophy behind the construction of Merged Feedback (MF) DETFF is to reduce the inherent multi-stage delay which is present in latches and flip flops by analyzing the circuit based on the relative phases of the clock and input (high/low or low/high) separately.
. Fig. 9. MF DETFF with PP/PN stage (Credits: )
The circuit is designed such that the different stages are active only for a particular value of input and clock. Stage I is low when clock is high and input is high. Stage II is low when clock is low and input is high. Similarly, stage III is high when input is low and clock is high while stage IV is high when input is low and clock is low. Thus, each input is transferred to the output depending on the clock edge.
Consider an example of a low input and high clock. Stage III drives Y1 to high (switching on M3) and leaves it floating for all other combinations of input and clock. Now, when the clock changes phase stage IV would drive node V and since M3 is on, node Y1 can capacitively couple with any voltage changes at the output as well as with node V. To avoid this charge coupling, the PP/PN stage feedback is used.
The PP/PN stage is formed by merging a precharged p-state (PP) and a precharged n-state (PN). The usefulness of the feedback can be understood by considering a case that the input goes high when clock is low. When clock is low, Z1 is high. With clock low, if input goes high, X2 becomes low. If the clock changes its phase to high with input remaining high, X1 becomes low as well. In this situation, Z1 remains floating but X2 is kept to low by the transistors M5 and M6. Hence, X2 is prevented from coupling with node U and output. Thus, the MF DETFF does not suffer from charge sharing problems as seen in the dynamic DETFF previously. The power dissipation in an MF DETFF is high but it can operate at high clock frequencies of more than 500 MHz and voltage of around 3 volts . The area occupied by it is comparable with other DET flip flops.
PULSE DET FLIP FLOP
The number of transistors used in the circuit can be reduced significantly if the circuit is driven by a clock pulse.
Fig. 10. Pulse triggered DETFF (Credits: )
The circuit shown in Fig. 10. uses only 8 transistors which is much less in comparison to those used in the previous circuits. The clock applied is a short pulse train generated by a pulse-clock generator circuit which uses an XNOR block to generate the pulse. The pulse train is basically a waveform which is formed by sampling the clock signals only at its positive and negative edges and adding a delay. The area consumed and the power dissipated is less than previously proposed DETFF circuits. It is possible to achieve much higher speeds with PDET and at the same time power consumption can be kept low. The area consumed by the pulse-generator circuit is not included since it is external to the main circuit and can be used to feed multiple PDET flip flops and other devices.
POWER DISSIPATION IN DETFF v/s SETFF
(4) The total power dissipated in a clock network is given by the equation:
Pclk = Vdd2 [fclk (Cclk+ Cff;clk) +fdata Cff, data]
fclk= clock frequency;
fdata= average data rate;
Cclk= total capacitance seen by the clock network;
Cff;clk= capacitance of the clock path seen by the flip-flop;
Cff,data= capacitance of the data path seen by the flip-flop.
If the capacitive loads are assumed to be constant, power dissipation becomes a function of fclk and fdata. Since DET flip flop halves the frequency rate while keeping the data rate same, power dissipation in DET flip flop is half of that in a SET flip flop. At low frequencies, power dissipated in SET is close to 45% more than that dissipated in DET flip flop. However, as frequency increases, the loss in DETFF increases because it has more number of transistors.
Fig. 11. Dissipation as a function of alpha= fdata/ fclk (Credits: )
Double-edge triggered flip flops have been demonstrated to be suitable for high speed and low power VLSI applications. A double-edge triggered flip flop can be implemented using two latches and a multiplexer or using only a single latch. Design optimisations can be done by a merged feedback or using a fully differential signal and gated clocks. The main focus is to reduce power dissipation while keeping area consumption low and achieve high speed of operation. It finds applications in DDR SDRAM which have been further developed into DDR2 SDRAM and DDR3 SDRAM.
The author Mayank Sarawagi thanks professors Dr. S. Chatterjee and Dr. A. Dhawan for providing the incentive to research on the topic and get an insight into the practical applications of Digital Electronics.