Digitally Controlled Delay Lines Computer Science Essay

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Digitally Controlled Delay Lines play a key role in many applications like all-digital PLL, all-digital DLL, all-digital spread-spectrum clock generators etc. A NAND-based DCDL, free from glitches is proposed in this paper. The proposed NAND based DCDL circuit is composed of equal delay elements each composed of NAND gates. Here there are two sets of control bits in order to control the DCDL. The glitch free operation of DCDL can be obtained with a three step switching mechanism. Depending upon the control bits encoding, each Delay Element (DE) can be in one of the three possible states i.e., pass, turn and pass-turn. The previously proposed NAND based DCDL presents a glitching problem which will limit their employ in various applications. But this paper presents a glitch free NAND based DCDL which overcomes this limitation in various applications.

This design will be simulated in Cadence Virtuoso using TSMC 45nm CMOS cell library.

Keywords:- All-digital delay-locked loop (A DDLL), all-digital phase-locked loop (ADPLL), Digitally Controlled Oscillator (DCO), Digitally Controlled Delay Lines (DCDLs) , spread-spectrum clock generator (SSCG).

I. Introduction

Delay may refer to latency or response time. The first delay effects were achieved using tape loops which were developed on reel-to-reel magnetic recording systems. A digital delay line is a discrete element in digital filter theory, which allows a signal to be delayed by a number of samples. If the delay is an integer multiple of samples digital delay lines are often implemented as circular buffers. This means that integer delays can be computed very efficiently.

A digital delay generator is a piece of electronic test equipment that provides precise delays for triggering, synchronizing, delaying and gating events. These generators are used in many types of experiments, controls and processes where electronic timing of a single event or multiple events to a common timing reference is needed. The digital delay generator may initiate a sequence of events or to be triggered by an event. It differentiates from ordinary electronic timing by the synchronicity of its outputs to each other and to the initiating event. The digital delay generator is similar to a pulse generator in function but the timing resolution is much finer and the delay and width of jitter is much less. Some delay generators provide precise delays (edges) to trigger devices. Others provide precise delays and widths to also allow a gating function. Some delay generators provide a single channel of timing while others provide multiple channels of timing.

Digital delay generators are usually the main block of the timing for larger systems and experiments. Generally users create a GUI,( graphical user interface) to provide a single control to the entire system or experiment. Nowadays, DCDLs play a major role in many applications like all digital spread-spectrum clock generators (SSCGs), all digital PLL (ADPLL), all-digital DLL (ADDLL), ultra-wide band(UWB) and also bioSoC applications.

In traditional approach [6], the proposed DCDL is also based on series of equal delay elements, this allows a designing of simple layout. Delay element is constructed by using inverting multiplexer and inverter. Because of the inverter and Mux, it presents two drawbacks. The first is due to the mismatch between odd and even control-codes in the multiplexer and different delays of the inverter. The second disadvantage is due to maximum delay of the multiplexer, which provides a resolution greater than the resolution of both NAND based DCDLs and TINV-based DCDLs.

In [1],[2],[3],[4],[5] to construct a DCDL with the help of chain based delay cells and a MUX is used to select the desired cell output. In MUX based DCDLs, as the number of cells increases the delay of the MUX increases. This ultimately results in tradeoff between the range of the delay and minimum delay (tmin) of DCDL. It is important to remember that tmin is the critical design parameter in many of the applications. APDLL/ADDLL are the applications od DCDL, the minimum delay determines the maximum output frequency of the circuit. The above property satisfies for all the spread-spectrum cock generators (SSCG) [6], where the synchronization with DCDL is obtained only when minimum delay is lower than one half input clock period. In MUX based DCDLs, large tmin can be reduced by using a tree-based multiplexer topology[1]. This ultimately results in irregular structure which complicates the layout design, besides nonlinearity of DCDL increases. In [16] MUX-based DCDLs are proposed. The DCDL is constructed by series of equal delay elements [7]-[10]. The minimum delay is low and becomes independent of the number of cells because as the multiplexer of previous DCDL is conceptually spread among the cells. Each DE is constructed by using only NAND gates, this result in a very good linearity and resolution. Here each element is constructed using three-state inverters (TINV), which obtains resolution. In [10] and [11] DCDL topology again uses a delay cells chain. In this method, each cell is constructed by using NAND gates which is differently from other above approaches. This gradually solves the trade concerned to MUX of previous structures. As glitching is common problem in any systems employing DCDLs and most common applications are used to processes clock signals, hence glitch free operation is required. In order to avoid the glitch problem, there are few condition to be followed in control code switching. In ADDLL topologies glitching is filtered by phased detector and harmonic locking circuitry during lock phase[7]-[10]. But in mux-based DCDLs, to avoid glitching, many approaches are known [12]-[14]. A distributed MUX -based structure is formed by the topologies of [11] and [6]. Thermometer code for control-bits is used to avoid glitching in those particular topologies or it can also be avoided by using the approach of [23]. Later on a novel glitch free NAND-based DCDL is presented. In present paper NAND- based DCDL allows to achieve a resolution, which is similar to the NAND-based DCDL of [7]-[10].

This paper is setup as follows. In [7]-[10], the NAND-based DCDL is discussed and analyzed in section II. In present paper, the glitch free NAND based DCDL is presented in section III. In section IV presents the obtained simulation results for a 45-nm CMOS technology.

II. Previously Proposed NAND based DCDL

The NAND-based DCDL of [7]-[10] is shown in Fig 1. It consists of chain of equal DEs and each DE contains four NAND gates among which one is a dummy gate for load balancing. Here all the NAND gates present the same load i.e. two NAND gates. Hence it presents the same delay. In this circuit the delay is controlled by controlling bits 'Ki' and these encode the control code 'c' with thermometric code. Thermometric code is given as Ki=0 for i < c and Ki=1 for i ≥ c. Each delay element can be in two different states by using the above encoding i.e., when Ki=0, pass state and when Ki=1, turn state. The delay is given by the equation below:

Delay= 2tNAND (1+ c)

where tNAND = (tNAND LH +tNAND HL)/2, tNAND LH and tNAND HL are the rise time and fall time of each NAND gate respectively. Minimum delay is obtained when the control code c=0.

1

Fig1: NAND based DCDL [7]-[10].

In order to prevent the appearance of the glitches in the output of the DCDL, in many of its applications the input signal and the delay control bits are switched at the same instant. If the control bits arrive earlier than the input signal of the first DE, glitching can be avoided. But the above condition is not sufficient to achieve glitch free operation for the DCDL in Fig1. Let us assume the vector K= [K0, K1…] of the control bits of DCDL. Initially it is assumed that In=0 and the control code is switched from 1(K=[0,1,1,1…]) to 2(K=[0,0,1,1,1…]). This produces the output glitch as the switching of K and its complement results in two different paths. It can be observed in Fig2. When input In is 1 and the control code is increased by 1 starting from an even value, the same glitching phenomena occurs as shown by Fig 3.

1

Fig 2: Glitching problem of NAND based DCDL of Fig 1 with Input zero

2

Fig 3: Glitching problem of NAND based DCDL of Fig 1 with Input one

Severe glitching problem was observed when the control codes were increased by more than one. The waveforms in Fig 4 were obtained under the condition In=0 and control code varies from 1 to 3. Under this condition multiple glitches are produced as four paths propagate within the structure.

a

Fig 4: Glitching problem when control code is increased by more than one.

III. Present NAND based DCDL

In this paper, the DCDL architecture has a lattice structure, which comprises of cascading of identical sub circuits called delay cells and each provide 1/N of the total delay. These delay cells are composed only with NAND gates and each delay cell contains six NAND gates out of which two are dummy cells. Then the present DCDL is shown in Fig 5 (a).

2

Fig 5(a): Inverting topology for a glitch free DCDL

To control DCDL, two sets of control bits 'Ki' and 'Li', encode the control code 'c', where Ki is the thermometric code and Li is the one cold code corresponding to the control code c. It is given as LC+1=0, Li=1, for i ≠ C+1. For the given control code, thermometric code and one cold code summarized below in Table1.

Control Code 'c'

Decimal (i) Binary

Thermometric Code (K)

K3 K2 K1 K0

One Cold Code (L)

L3 L2 L1 L0

0 00

1 1 0 1

1 1 1 1

1 01

1 0 1 1

1 1 1 0

2 10

0 1 1 1

1 1 0 0

3 11

1 1 1 1

1 1 0 0

Table1: Thermometric Code and One Cold Code for the given Control Code.

Each DE can be in three possible states, based on the encoding of control codes. The DEs will be in pass-state when Ki=0, Li=1 (i˂c). In this state, the signal propagation in lower NAND gates chain is enabled. When Ki=1, Li=1 (i=c), the DE will be in turn state. When Ki=1, Li=0 (i=c+1), the DE is in post turn state. In this case the output of the lowest NAND gate is stuck at one, which allows the propagation in the preceding DE which is in turn state. The cells with i>c+1 are again in turn state. The logic states of DEs are shown in the below Table 2.

Si

Ti

State of DEs

0

1

Pass

1

1

Turn

1

0

Pass-turn

Table2: Logic states of DEs

In the present paper, the intermediate signals between each DE cell are considered to be 'µi' and 'λi'. For the first DE cell, input itself is considered as µ0 and the output signal from the second DE cell to the first DE cell is given as λ0. Similarly the output signal of the first DE cell is given to the next DE cell as µ1, and this process continues for remaining DE cells and the signals are represented as [µ2, µ3….]. The output of the Nth DE cell is given to (N-1)th DE cell and it is represented as λN-1 and this process continues for the remaining DE cells and those intermediate signals are given as λN-2, λN-3, …, λ1, λ0. In the initial state the intermediate signals depend upon the input i.e. µ2i=λ2i =In also µ2i+1 = λ2i+1 = , provided with the only exception of λx which is stuck at 1. Consider when delay control-code switches from c=x to c=y.

3

Fig 5(b): Non-inverting topology for a glitch free DCDL

When the (x+1)th DE is switched from post turn state to turn state, λx which is the input to the lowest NAND gate, switches from 1 to µx. The other input of the NAND gate is stuck-at µx. So the output of the NAND gate remains the same as the previous condition (x), resulting in no glitch. All the DE cells will be either in turn state or pass state, after (x+1)th DE switching. Now changing the states of the DE from pass state to turn state or vice versa does not affect the logic state of the signals λi and µi. Next the (y+1)th DE is switched from turn state to post turn state, which is also a glitch free switching, as only λy signals switches from µh to 1.This three-step switching gives a glitch free output. The resolution time (tR) for inverting circuit is given as

tNAND LH + t NAND HL = 2-tNAND

But the minimum delay tmin for inverting circuit is approximately equal to the 3-tNAND. One of the things has to be clearly observed is, in inverting DCDL, the first DE cell will not be in post turn state. Hence L0 is always 1. So we can modify the first DE in Fig5(a) as shown in Fig5 (b). The modified circuit is obtained by deleting the first two NAND gates along with the signal L0. In modified DCDL circuit (non-inverting) the input signal In is equal to the µ1, therefore the entire operation is non-inverting. Even this circuit maintains the same resolution time (tR) as the inverting circuit which is 2-tNAND. The performance of non-inverting DCDL is as same as the inverting DCDL, as the minimum delay 2-tNAND which was equal to the minimum delay of inverting DCDL.

SIMULATION RESULTS

The glitch free delay line circuit has been designed for the 45nm CMOS technology with 1V supply voltage. Aspect ratio for all the NAND gate is chosen as WP/WN.=0.75, where WP is the width of the pmos and WN is the width of nmos.

3step switching

Fig 6: Three step switch of the control code (c1 to c2)

We have analyzed the cases when the control code is increased by one, two and more than two. For the inverting DCDL, when the above three cases were applied without three step switching, when c was varied from 1 to 2 glitches were observed. But when three step switching was carried out for the same condition operation was glitch free. The obtained waveform is shown in Fig 6. The Fig 7 (a), 7(b), 7(c) shows the waveforms obtained when the control code is increased from c=0 to c=1; c=0 to c=2; c=0 to c=3 for the inverting DCDL topology respectively.

rep c0 to c1

Fig 7 (a) : (Inverting) control code switching from c=0 to c=1

c0 to c2

Fig 7 (b) : (Inverting) control code switching from c=0 to c=2

c0 to c3

Fig 7 (c) : (Inverting) control code switching from c=0 to c=3

Similarly, the simulation results for non-inverting DCDL topology is shown below in Fig 8(a) , 8(b) and 8(c)

c0 to c1

Fig 8(a): (Non-Inverting)control code form c=0 to c=1

c0 to c2

Fig 8(b): (Non-Inverting)control code form c=0 to c=2

c0 to c3

Fig 8(a): (Non-Inverting)control code form c=0 to c=3

Table 3 compares the performance of the DCDL in 45nm technology. For all the cases the length of the line is chosen as the four DEs.

TR (ps)

tmin HL (ps)

tmin LH (ps)

tp (ps)

NAND- based

Present Inverting

Present non-inverting

CONCLUSION

The glitching problem of the previous circuits [7]-[10] was analyzed in detail. Switching of the control signal 'K' and its complement leads to glitches in the output. As a solution to this problem, a modified NAND based delay line is designed in which the control code is encoded by two different sets of codes. The two topologies i.e. inverting and non - inverting topologies for the modified circuit was designed. A three step switching mechanism was opted for switching the control codes to avoid glitches in the output. Simulation results confirm the correctness of the modified circuit.

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