Digital Phase Locked Loop Computer Science Essay

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The PLL is a major component that is often found in communication systems. PLL is used to provide clock with in the blocks of system that is in phase to the system clock. Another common application of PLL is clock recovery in communication. So the design of good PLL system is important. However, analog PLL's occupy larger chip area due to the use of capacitors in the feed-forward path. It has some other disadvantages such as sensitive to noise and difficulty in converting to different process, and etc. With the aim of overcoming the above stated problems the design of an all digital PLL was studied. A PLL is a feedback system that compares the output phase with the input phase. The aim of this paper is to present Digital phase locked loop (D-PLL) with improved acquisition time and power efficiency. The implemented D-PLL can operate from 6.54MHz to 105MHz .The power dissipation of the D-PLL is 7.763µW (at 210MHz) with 1.2V supply voltage. The D-PLL is synthesized using cadence RTL compiler in 45nm CMOS process technology.

Keywords: Digital PLL, Digital Phase/Frequency detector, NCO (time to digital converter plus digitally controlled oscillator), Divide by N counter.


PHASE LOCKED loops are widely used in frequency synthesis applications [2], [4], [5]-[7]. For many portable applications the acquisition time of PLL is very important so the design of PLLs with minimum acquisition time is the primary goal of this work .A Phase Locked Loop (PLL) is a feedback system that compares the output phase with the input phase to produce an output signal that has the same phase as that of an input signal. PLL's are found in many applications such as reference generation, frequency synthesis, frequency multiplication, FM demodulation...etc. As the frequency of operation increases, the need of generating signals that are in phase lock with input (i.e. fast varying signals) is becoming a problem. There are two types of PLL's 1) Analog PLL 2) Digital PLL .Traditional PLL's are analog PLL's as shown in fig.1

Fig.1 Block diagram of Analog PLL

It uses phase detector to compare the input phase with the output phase. Loop filter is used to reduce the ripples on the control voltage of VCO. VCO is used to adjust the output frequency such that the loop is locked and the output signal is the replica of the input signal. However, analog PLL's are bulky and less immune to noise. Whereas D-PLL's are compact and high immune to noise. Moreover D-PLL's are easily programmable (i.e. easy process conversion).

D-PLL Architecture

The block diagram representation of a D-PLL is shown in fig.2. The below architecture is simple and easy to implement.

Fig.2 Block diagram of D-PLL

The D-PLL architecture shown above has four major blocks, namely the phase/frequency detector (PFD), the time to digital converter (TDC), the accumulator and the number control oscillator (NCO). The NCO is implemented by using frequency divider circuit. The PFD detects the phase or frequency difference between the reference clock and output clock. The output of the PFD is given to TDC which is continuous in time. The time to digital converter generates a count value which is proportional to the phase error. The average value (DC value) of the PFD is accumulated by the accumulator block. The accumulated value determines the control word for the NCO to oscillate with an appropriate frequency.

Analysis of Individual Blocks

Phase Detector:

The Phase detector (PD) is a circuit that compares the phase difference between the two input signals. It generates an output signal whose average value is linearly proportional to the phase difference between the two input signals. There are number of ways in which a Phase Detector can be realized, but we mostly consider two types. They are 1) XOR-gate 2) PFD.

XOR-Gate Phase Detector:

The XOR-gate (from Fig.3) produces an output when both the input's are unequal, otherwise zero.

Fig.3 XOR-Gate

I:\pd wave.png

Fig.3.1 Output waveform of XOR-Gate.

The XOR-gate produces output both at the rising edge and falling edge of a cycle. The below equation gives from the input-output relationship of an XOR-gate Phase Detector.



Fig.4 Input-Output characteristics of XOR-Gate Phase Detector

As it can be seen from the above characteristics, the problem of XOR-gate Phase Detector is its linearity range is limited to π. when the phase difference is greater than π then its average output value decreases. So we go for flip-flop base phase Detector or Phase Frequency Detector.

Phase Frequency Detector(PFD):

Fig.6 Block diagram of PFD


Fig.7 Output waveforms of PFD

The circuit shown in fig.6 can serve as both phase/frequency detector. It has three states, initially both and equal to zero. If input A leads input B, first goes high at the rising edge of input A (since is connected to logic 1), then goes high at the rising edge of input B(since is also connected to logic 1), causing the output of the NAND gate to go to low , thereby resetting both and .Similarly if input B leads input A then goes high first.The circuit consists of two positive edge triggered, negative edge resettable D-flip-flop having tied their inputs to logical 1. The input's of interest serves as a clock to flip-flop.The input output characteristics of the Phase Frequency Detector is shown below:

Fig.8 Input-Output characteristics of PFD

From fig.8, it is clear that the main advantage of Phase Frequency Detector is that it's improved linearity range and the ability to act as a frequency detector as well.


The integrator block consists of time to digital converter plus discrete time accumulator (1 tap IIR filter).

Time To Digital Converter:

The time to digital converter block is used to convert the output of the Phase Frequency Detector which is continuous into a digital number. The time to digital conversion can be achieved simply by using a counter which is capable of counting up and down. The following analysis has shown that the output count value is proportional to the input Phase Difference.


Fig.9. Time to Digital Converter (TDC) implemented with Counters.

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Fig.10. Output Waveforms of Time to Digital Converter (TDC).

Let C= Counter Output;

C (t) = time varying state of Up/Down counter.

=Counter clock period.

T=time period of input or phase detector cycle period.

C= ----- (1)

If is very small i.e. if ƒ 0 then ∑ becomes integration.

C=------- (2)

If there are N1 cycles in T seconds then

= --------- (3)

Where =counter clock frequency.

= .T



= ------ (4)

From equation (4) it is clear that the output count value C is proportional to the input phase difference.

Accumulator (Discrete time integrator):

The accumulator block is used to provide a constant number (control_word) to the Number Control Oscillator (NCO). The accumulator block is analogous to the LPF (integrator) in analog PLL.

Number Control Oscillator (NCO)

The Output frequency of the NCO is numerically controlled by using a binary word instead of voltage. That is the NCO generates an output signal whose frequency is proportional to the input control word (binary format). There are many ways to implement NCO block but the simplest way to implement NCO is counter based approach. The NCO consists of counter capable of dividing the input clock based on its control word. The applicability of this device as NCO is explained below.

* Control word ------ (1)

----- (2)

Where k= Resolution = , n= Number of bits in counter.

The resolution of NCO increases by increasing the number of bits. The higher the control word, higher the frequency and vice-versa.

Fig.11 Block diagram of NCO

Fig.12 Internal block diagram of NCO

Fig.13 Input- output characteristics of NCO

From equation (1), it is clear that the NCO can be implemented using counter, whose output frequency is based on the Control word. The maximum input frequency that can be locked depends on the NCO resolution (k=).The counter based NCO frequency range is

Experimental results

C:\Users\mssk2_000\Desktop\pll waveform.png

Fig.14 Output waveforms of PLL at 210MHz

Fig .14 shows the Output waveforms of the PLL where the reference clock is 52.35MHz. The D-PLL is synthesized using cadence RTL compiler in 45nm CMOS process. The D-PLL is implemented with following specifications:


Maximum NCO frequency = 209.42 MHz

Free running frequency of NCO = 130.8MHz.

NCO resolution = = 6.54MHz; n=5 bit.

Input Frequency = 7MHz.

Performance Parameter







0.35µm CMOS

0.25µm CMOS

0.60µm CMOS


All digital

All-digital cell based



Power dissipation





Minimum Frequency





Maximum Frequency





Supply voltage





Max. acquisition time

<18 cycles

<46 cycles

<720 cycles

<16 cycles

Table 1. Performance comparisons

From the above comparison table it is clear that power dissipation of the proposed D-PLL is minimal compared to that of All Digital cell based PLL [1], Analog PLL [2], Semi-Digital PLL [3]. The acquisition time of proposed D-PLL is less than Digital cell based PLL[1] and analog PLL[2] i.e. proposed D-PLL is faster than the other two PLLs proposed in [1],[2].


In the paper a D-PLL is presented. The D-PLL is implemented with standard cells in a 0.045µm technology and can operate from 6.54MHz to 105MHz. The presented D-PLL architecture is simple and easy to implement.