Digital Phase Locked Loop Architecture Computer Science Essay

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For Integrated Circuits, one of the essential figure of merit is its data conversion technique used to communicate with analog world. For the same the requirement is, minimum internal noise generation as well as maximum external jitter cancellation. Data conversion technique used for analog signal to process it in digital domain consumes most of the power and silicon area of the chip. Digital Phase Locked loop (DPLL) could prove to be better replacement for conventional Analog Phase Locked Loop (PLL). Analog components of conventional PLL could be replaced by digital version so that data conversion could be simplified. This project shall try to analyze current available digital components and try to find best match that could be used to make it work at GHz speed.


High data rate demand in communication is increasing over days. Currently in storage PCIe 3.0 is working at 8GT/s, which leads us to handle high data rate at physical layer of chip. To meet this high bandwidth requirement, serial data transfer protocol is developed. Serial data transceiver is commonly known as Serializer-Derserialzer (SerDes). The main function of SerDes is to transmit and receive high rate serial data over differential pair of wired interconnect. As Complementary metal-oxide-semiconductor (CMOS) technology is scaled in deep sub-micron region, digital logic gates has been improvised in timing accuracy, power, and density of digital logic gates. While, analog communication circuits suffer from reduced supply voltage and increased gate leakage. As a result, some traditionally analog-only circuits have progressed to digitally assisted designs, and more recently all-digital designs, that utilize the precise time control and sophisticated digital signal processing. This approach shows a room for improvement in conventional analog phase locked loops in terms of area, scalability, testability, and programmability.

The general concept of Phase Locked Loop:

Phase locked loop is a module that locks the phase of the output to the input. It does this by a feedback control system that controls the phase of a voltage controlled oscillator (VCO). The input signal is applied to one input of a phase detector. The other input of the phase detector is connected to the output of a VCO. Normally the frequencies of both signals will be nearly the same. The phase variation observed between two signals is proportional to the output of the phase detector's voltage. Loop filter removes the square term detected by phase detector and shapes the correction term. It is the loop filter that determines the dynamic characteristics of the PLL. The correction term signal controls the VCO. Note that the output of the VCO is at a frequency that is N times the input supplied to the frequency reference input.

Figure Conventional Analog PLL Block DiagramPhase Detector

Loop Filter

Voltage Controlled Oscillator

Recovered Clock

Rx Data In


Background - Analyze the Analog component of the PLL system:

Phase Detector: The phase variation is detected by mixed signal component i.e. phase detector. As the CMOS technology shrinks in deep sub-micron region, to meet stringent phase noise requirement high resolution Time-to-Digital Converter (TDC) turns out to be appropriate substitute to Phase Detector [1].

Loop Filter: PLL filter is needed to remove any unwanted high frequency component that might pass out of the phase variation measurement and appear in VCO correction factor. This unwanted high frequency component would affect the output of VCO as spur. Filter also plays role in changing the loop frequency as quickly as possible. The loop filter also governs the stability of the loop. If the filter is not designed correctly then oscillations can build up around the loop, and large signals will appear on the tune line. This will result in the VCO being forced to sweep over wide bands of frequencies. The proper design of the filter will ensure that this cannot happen under any circumstances. As its analog in nature, it consumes most of the area along with VCO. Scalability as well is major concern for analog PLL. Thus, stability can be achieved by using digital loop filter. The proposed architecture tries to find the suitable replacements for these analog components.

Voltage Controlled Oscillator: The performance of the VCO is of utmost important in PLL. This is because the VCO's performance determines many of the characteristics of the overall PLL. Designing a precise VCO is not always easy due to its precise design requirement. Since VCO design is process dependent, thus redesign of VCO is only option available in order to migrate it to lower technology node. This scalability and process dependence are some of the issues in VCO design. The Digital controlled oscillator is a key component in PLL, which is a replacement of the conventional voltage or current controlled oscillator in the fully digital phase licked loops. They are more flexible and usually more robust than the conventional VCO. Furthermore, the design compromise for the frequency gain in voltage or current controlled oscillator is not necessary in DCOs because the immunity of their control input is very high.

Literature Search -

Time to Digital Converter (TDC) - In deep sub-micron region, intrinsic gain of single Metal Oxide Semiconductor (MOS) transistor decreases. This is due to parasitic short channel effect and also due to fundamental result from MOS physics. The countermeasure to cope with this decreasing transistor gain is available. For instance, cascade transistor increases the output resistance of analog component to deal with scalability, but is also adds at least one VDsat to DC supply voltage. In general, technology scaling along with supply reduction leads to reduced signal levels. This reduced signal level in voltage domain cannot be handled by mixed-signal components. Thus, working in voltage-domain signal with shrinking technology node is a challenge. An implantation of time-domain analysis of signal would take advantage of technology scaling again. TDC works as enabler for time-domain processing of continuous signal.

The traditional approach to time-to- digital conversion is first to convert time interval into voltage. Second, quantize/ digitize this voltage, so that further signal processing can be handled in digital domain. Three of the factors of TDC to be considered for high performance All Digital PLL (ADPLL) designs are resolution, linearity and conversion range. This proposal tries to categorize TDC based on this figure of merit.

TDC concept is relies mostly on ADC configuration. We shall try to analyze few TDC configurations, which can suit our requirement.

Flash TDC - It is analogues to flash Analog-to- Digital Converter (ADC). As in line with Flash ADC, this type of TDC converts time domain to digital domain in just one clock cycle. Fastest conversion time is one of the advantages of Flash TDC. It is ideal for requiring large bandwidth. High bandwidth is one of eh requirement in High speed ADPLL. It also needs to serve the high speed time to digital conversion. Thus, Flash TDC as shown in figure 2, is apt for replacement for phase detector [12].

Flash TDC does time encoding and operates by comparing an input signal edge with respect to various reference edges all displaced in time. Voltage controlled Delay Unit (VCDU) is used to displace the reference clock uniformly. This VCDU chain produces Ï„ delay. D flip flop works as comparator between reference clock and input signal. D-type Flip-flop should have low setup time so that it can measure small amount of time variations. To ensure that Ï„ is known reasonably accurately, the delay chain is often implemented and stabilized by calibration circuitry. [13]

To determine the time difference ΔT between the rising edges of pulses Input and Ref Clock by the eight-level delay chain converter in Figure 2, each flip-flop working as comparator measures difference in time between the delayed Ref Clock to that of the Input signal. As in case of Flash architecture, the thermometer-encoded output indicates the value of time variation, ΔT.

Figure 2 Flash TDC Based ArchitectureAlong with more area consumption one of the drawbacks of this implementation is the temporal resolution can be no higher than the delay through a single gate. In short resolution is dependent on VCDU, and thus becomes process dependent. Flash TDC Architecture is well suited for use in on-chip timing measurement systems, because they are capable of performing a measurement on every clock cycle and can be operated at relatively high speeds. In addition, they can easily be constructed in any standard CMOS process, because they are composed solely of digital components.

Vernier Flash TDC - The resolution of TDC in Flash architecture is closely related to process. The minimum resolvable time quantity is proportional to one-inverter delay of VCDU. The Vernier delay chain is frequently considered circuit technique to overcome the technology related limitation on the time resolution.

To make TDC resolution process independent, VCDU is replaced by vernier delay line in Flash TDC Architecture, as shown in Figure 3. This architecture achieves a resolution of τ1 − τ2, where τ1 > τ2. Likewise Flash ADC, two calibration circuitry [13] is implemented for vernier delay lines to make them reasonably accurate. This TDC composed of modified flash TDC along with vernier delay line. The time variation is quantized by different delays introduced by the VCDU [14]. The Start and Stop pulses enable the TDC operation. The comparator based on D Flip-Flop, measure the time difference between these two signals by detecting the instant one edge catches up with the other. Due to its small size and relatively high temporal resolution, the Vernier TDC based architecture is acquiescent for use in on-chip test systems. Phase lock calibration of delay elements using a DLL [13] can correct for any process variations and temperature effects in the delay of VCDU. This feature is used to overcome the temporal uncertainties caused by component variation in the delay lines of Vernier delay flash TDC.

Figure 3 Vernier Flash TDC ArchitectureOne disadvantage of this architecture, however, is that it takes many cycles to complete a single measurement (i.e., it has long conversion time). Compared to flash converters that can make a measurement every cycle, the Vernier oscillator requires a long conversion time along with high power consumption.

Cyclic Vernier TDC - Fig. 4 shows the block diagram of the cyclic Vernier TDC [15] [16]. The goal of the TDC is to measure the time difference between the rising-edges of the 'Start' and 'Stop' signals. When the 'Start' signal is asserted, the slow digitally controlled oscillator (DCO) starts to oscillate with a period of Ts, and the number of oscillations is counted by the coarse counter. Then, after an input delay of Tinput, the 'Stop' signal triggers the faster DCO with a period of Tf. At this time, the coarse counter is disabled, and the output of the counter represents a coarse measurement of the time between 'Start' and 'Stop' rising-edges (Tcoarse). To improve the measurement accuracy, the residue of the input delay (Tfine) is measured by the Vernier structure. Since Tf is smaller than Ts, the time difference between rising edges of two oscillations is reduced cyclically by the difference in periods (Ts - Tf), and the edge of the fast DCO eventually catches up with the slow DCO. By counting the number of cycles it takes for the fast DCO to catch up with the input, determines digital value of input signal's time variation. As shown in Fig. 3, the TDC operates in two-steps; a coarse step and a fine step. The resolution of the coarse step is the period of the slow DCO, and the resolution of the fine step is the difference between the periods of the two DCOs. Note that the fine resolution does not depend on the absolute frequencies of the DCOs, but only their difference in periods. This is crucial for the calibration of mismatch between the PAR-ed DCOs.[17]

Figure 4 Cyclic Vernier TDC Architecture

In recent publication on cyclic TDC [18], Proposed TDC consists of a cyclic input control block, a 1.5b Multiplying Digital-to-Analog Converter (MDAC), and a digital error correction (DEC) block, which is similar to the one used in ADC to compensate comparator offset error. Timing is controlled by asynchronous clocking scheme. For 1.5b MDAC operation, 2x TA is used after time domain subtraction using delay in signal path.

Figure 5 Cyclic TDC Architecture

Half Rate Phase Detection - In pursuing higher data rate with fixed device technologies, half-rate phase detection based Clock and Data Recovery (CDR) circuits are advantageous since they double the operating data rate. Moreover, if a de-multiplexer follows the CDR circuit, which is used for several applications, the half-rate architecture also reduces the circuit complexity since it has built-in the 1 :2 de-multiplexer.

Figure 6 Half Rate Phase Detection

Figure 6 shows the architecture diagram of the proposed half-rate bang-bang PD, which uses only five D edge trigger latches. The clock period is equal to the minimum pulse width in the data stream that contains random Non Return to Zero (NRZ) bit sequences. The signal A is the output of the D latch triggering on the falling edge of the quadrature clock. The latches with the de-multiplexing outputs are triggered on the opposite edges of the clock. The signal A is then used to sample the D, and Do and creates the bang-bang PD outputs (UP and DN).

Modeling of Different TDC Architecture - To understand different TDC architecture in depth, shall try to model TDC in Simulink and measure its response for high bandwidth input.

Figure 7 Cyclic TDC ModelingFigure 7 shows one of the model for of Cyclic TDC, which tries to implement pulse shrinking technique.

Current trend in TDC - Following table mentions some papers published in year 2012 in area of various TDC architecture used in DPLL.









A 300-MS/s, 1.76-ps-Resolution, 10-b Asynchronous Pipelined Time-to-Digital Converter With on-Chip Digital Background Calibration in 0.13-μm CMOS



A 2.8-3.2-GHz Fractional- N Digital PLL With ADC-Assisted TDC and Inductively Coupled Fine-Tuning DCO



A 1.25 ps Resolution 8b Cyclic TDC in 0.13 um CMOS



A 3x9 Gb/s Shared, All-Digital CDR for High-Speed, High-Density I/O



A 2 GHz Fractional-N Digital PLL with 1b Noise Shaping ΔΣ TDC



A 10-Bit 80-MS/s Decision-Select Successive Approximation TDC in 65-nm CMOS



A 5.6 GHz to 11.5 GHz DCO for Digital Dual Loop CDRs



A 3.6 mW, 90 nm CMOS Gated-Vernier TDC With an Equivalent Resolution of 3.2 ps



A Dither-Less All Digital PLL (2-D Vernier TDC & Dither-less [email protected]) for Cellular Transmitters



1-1-1 MASH ΔΣ TDC With 6 ps Resolution and Third-Order Noise-Shaping


32nm SOI

An 8.0-Gb/s HyperTransport Transceiver for 32-nm SOI-CMOS Server Processors




A 40nm CMOS All-Digital Fractional-N Synthesizer without Requiring Calibration



A 0.004mm2 250μW ΔΣ TDC with Time-Difference Accumulator and a 0.012mm2 2.5mW Bang-Bang Digital PLL Using PRNG for Low-Power SoC Application



An All-Digital Clock Generator Using a Fractionally Injection-Locked Oscillator in 65nm CMOS



A 13b 315fsrms 2mW 500MS/s 1MHz Bandwidth Highly Digital TDC Using Switched Ring Oscillators



A TDC-Less ADPLL with 200-to-3200MHz Range and 3mW Power Dissipation for Mobile SoC Clocking



Modeling the Response of Bang-Bang Digital Phase Locked Loops to Phase Error Perturbations



A Digital Phase-Locked Loop with Calibrated Coarse and Stochastic Fine TDC



A Digital PLL with Two-step Closed-locking for Multi-mode/Multi-band SAW-less Transmitter




ADPLL Frequency Synthesizer With an Improved Phase Digitization Approach and an Optimized Frequency Calibration Technique


A Frequency-Based Model for Limit Cycle and Spur Predictions in Bang-Bang ADPLL



A 4-GHz All Digital PLL With Low-Power TDC and Phase-Error Compensation




An All-Digital Clock Synchronization Buffer With One Cycle Dynamic Synchronizing

In brief, Flash Architecture can handle high bandwidth input. Vernier Delay line makes the TDC architecture process independent. Cyclic TDC architecture is based on pulse shrinking method. The half rate phase detection provides us convenience of working at half of the input frequency. This provides us scope to work at high speed along with scalability to obtain stable Digital Phase Locked loop. The proposed TDC implementation shall try to explore these three TDC architectures along with different design for vernier delay line to meet high resolution and low conversion time requirement. This research shall try to build half rate TDC based on vernier delay line.

Digital Loop Filter - Once we can digitize the input time variation, time filtering in digital domain becomes easy. We shall try to explore FIR and IIR filters, which can give us stable loop. Digital Signal Processing and digital filter is different topic all together. This Research Project shall concentrate on area, which is not explored earlier and port software based digital loop filter for testing loop in cadence. We can also use predefined filter IP available in cadence library.

Digitally Controlled Oscillator - Digitally Controlled oscillator is based on ring oscillator, which uses odd number of NOT gates to generate oscillations. DCO is distributed in coarse and fine blocks. Coarse block increases output frequency, whereas fine block maintains fine resolution. DCO implementation can be categorized in as follows,

Series Connected Delay Chain with MUX

Ring Oscillator with control code

This research shall try to explore merits and de-merits of above mentioned types of DCO. This work shall try to focus on modeling of DCO in Simulink before implementing it in Cadence for simulation.

Currently more than 50% power and area in the chip has been utilized by Serializer - Deserializer (SerDes). By converting PLL into digital domain, the proposed architecture shall try to reduce power consumption to minimum. As Voltage control oscillator consumes most of the area of PLL, its alternative Digital Controlled Oscillator (DCO) shall concise the chip area. This shall give data conversion technique new direction with minimum power and area consumption.

The proposed architecture shall try to enhance the resolution with minimum internal jitter. Once we get approval from higher management, team of 3 engineers with one architect (1 test engineer, 1 Digital Deisgn Engineer, 1 AMS Engineer along with 1 SerDes Architect), can finalize the architecture based on research and available models from Simulink.

Tentative schedule for the project is as follows,

Finalizing and brainstorming the architecture - 2-4 weeks

Designing High Speed DFF - 1-2 months

Designing TDC - 2-4 months

Designing DCO - 2-4 months

Rx Data In


Half Rate TDC

Digital Filter

Digital Controlled Oscillator

Recovered 500M Clock





Cancellation Circuit

Rx Data out (5G)

Synthesizing All Digital PLL Based CDR - 2 months

Figure 8 Proposed DPLL ArchitectureThe proposed research shall focus to design this DPLL in such a way that it can be compatible with current test environment of the chip.

Figure Proposed Digital PLL ArchitecturePower consumption, area and testability are major criteria for any design to be scalable to deep submicron region. To communication to external world, any chip uses analog signals. Phase locked loop consumes most of the power and area inside the chip. To overcome the bottleneck of chip design, i.e. analog component we shall attempt to look for its better alternative, which can ethically replace the conventional analog Phase locked loop. As we are scaling down the technology along with operating voltage, the conventional method of voltage measurement is difficult to follow. Time to digital conversion would have been better fix to this problem. We shall endeavor to tackle each component of PLL one by one find their merits and demerits and replace it with its digital substitute.