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Digital integrated circuits are found everywhere in modern life and many of them are embedded in mobile devices where limited power resource is available e.g. mobile phones, watches, mobile computers, personal assistantsâ€¦.. To permit a usable battery runtime, such devices must be designed to consume the lowest possible power. Furthermore, low power is also very important for non-portable devices, too. Indeed, reduced power consumption can highly decrease the packaging costs and highly increase the circuit reliability, which is tightly related to the circuit working temperature. For these reasons, low power design is now mandatory for all types of digital circuit.
Because of the quadratic relationship between power and voltage, supply voltage reduction has become an important method for reducing active power in VLSI systems, improving reliability in highly scaled MOSFETs, and minimizing the effects of heat dissipation in high-performance systems. The reduction of supply voltage is dictated by the need to maintain the electric field constant on the ever shrinking gate oxide. Unfortunately, to keep transistor speed (proportional to the transistor "on" current) acceptable, the threshold voltage must be reduced too, which results in an exponential increase of the "off" transistor current, i.e., the current constantly flowing through transistor even when it should be non-conducting.
As silicon CMOS is scaled beyond the 90nm and 65nm to the 32nm and 22nm technology nodes, ultra-low supply voltage becomes one of the most critical and powerful mechanism for improving device reliability and energy efficiency. Unfortunately, ultra-low voltage operation has been limited by performance constraints and other challenges.
1.2 INTRODUCTION TO LOW POWER CMOS DESIGN
It is well known that the power dissipation is directly proportional to the square of the power supply voltage, while it is proportional only to the first power of the capacitance and frequency (Pav=CV2 f). Thus, much work has been done on the technology side to reduce the power supply voltage from 5v to 1.5v and below. This trend will likely continue in the future and we may soon see 0.9v or lower supplies. However, reduction in the supply voltage has a negative effect on circuit performance. Propagation delays through logic gates increase as the supply voltage decreases and the overall noise immunity of the circuit decreases.
To reduce these undesirable effects, threshold voltage have also been lower. However, lower threshold voltages increase the leakage power dissipation caused by sub-threshold conduction in the MOSFETs. For circuits with very low threshold devices, the static (leakage) power no longer negligible and can even dominate the active and short-circuit power. Starting from 0.13µm technology node (i.e., a technology with a minimal transistor size of 0.13µm), the static power consumption cannot be neglected anymore and must be added to the dynamic power to correctly estimate total power consumption.
1.3 OVERVIEW OF THE PROJECT
High speed divide-by- N/N+1 counter (also called prescaler) is a fundamental module for frequency synthesizers. Its design is crucial because it operates at a higher frequency and consumes higher power consumption. A divide-by-N/N+1 counter consists of flip-flops (FF)and extra logic, which determines the terminal count. Conventional high speed FF based divide-by-N/N+1 counter designs use current-mode logic (CML) latches and suffer from the disadvantage of large load capacitance. This not only limits the maximum operating frequency and current-drive capabilities, but also increases the total power consumption.
Alternatively, FF based divide-by-N/N+1 designs adopt dynamic logic FFs such as true-single-phase clock(TSPC) . The designs can be further enhanced by using extended true single-phase-clock (E-TSPC) FFs for high speed and low power applications. E-TSPC designs remove the transistor stacked structure so that all the transistors are free of the body effect. They are thus more sustainable for high operating frequency operations in the face of low voltage supply .
Past optimization efforts on prescaler designs focused on simplifying the logic part to reduce the circuit complexity and the critical path delay. For example, an E-TSPC design embedded with one extra PMOS/NMOS transistor can form an integrated function of FF and AND/OR logic . Moving part of the control logic to the first FF to reduce unnecessary FF toggling yields another version of prescaler design. These two classic designs each contains 16 transistors only and the mode control logic uses as few as 4 transistors. To achieve such circuit simplicity, it calls for a ratioed structure in the FF design .Despite its distinct speed performance, the incurred static and short circuit power consumptions are significant.
A general TSPC logic family containing both ratioed and ratioless inverter alternatives. Since the maximum height of transistor stacking is up to 5, these designs lose their performance advantages when working under a low scenario. A power gating technique by inserting an extra PMOS between Vdd and the FF is employed in two novel divide-by-2/3 counter designs. The unused FF can be shutdown when working in the divide-by-2 mode. Due to the increase in the number of transistor stacking (up to 4), these designs are not suitable for low Vdd operations. Due to the quadratic dependence of power consumption on supply voltage, lowering Vdd is a very effective measure to reduce the power at the expense of speed performance. In this paper, a prescaler circuit design aimed at tackling the speed and power issues simultaneously using non-state-of-the-art process technology (0.18 m) is presented.
In particular, we focus on low Vdd operations for power saving without sacrificing the speed performance. In this design, ratioed E-TSPC FFs are employed due to its circuit simplicity and speed performance. Only one pass transistor is needed to implement the mode control logic. The proposed design is capable of working at a maximum frequency of 531MHz when the supply voltage is as low as 0.6 V.
DRDL is a precharged circuit technique which is used to improve the speed of CMOS circuits. Domino gate consists of dynamic CMOS gate circuit followed by a static CMOS buffer Eliminates the transition and power dissipation over static style. Dynamic logic does not suffer from short circuit current.
Complementary pass transistor logic (CPL) has swing restoration ability. one pass-transistor network SS is sufficient to implement the logic function , which results in smaller number of transistors and input loads especially when NMOS network used.
DCVSPG has the ability to generate any logic function(both true and complement outputs).It eliminates p logic gates because of inherent availability of complementary signals. P logic gates cause long delay time and consumes large areas.
Current mode logic (CML), or source-coupled logic (SCL), is a differential digital logic family intended to transmit data at speeds between 312.5 Mbits/s and 3.125 Gbit/s over a standard printed circuit board. The transmission is point-to-point, unidirectional and is usually terminated at the destination with 50â„¦ resistors to Vcc on both differential lines. CML is the physical layer used in DVI and HDMI video links, and is frequently used in interfaces to fiber optic components. This technology has widely been used in design of high-speed integrated systems, such as in telecommunication systems (serial data transceivers, frequency synthesizers, etc.). The fast operation of CML circuits is mainly due to their lower output voltage swing compared to the static CMOS circuits as well as the very fast current switching taking place at the input differential pair transistor. Recently, CML topology has been used in ultra-low power applications. Studies show that while the leakage current in the conventional static CMOS circuits is becoming a major challenge in lowering the energy dissipation, good control on current consumption in the CML topology makes them a very good candidate at extreme low power conditions. Called subthreshold CML or subthreshold source coupled logic (STSCL), the consumption of each gate can be reduced down to few tens of pico-amperes.
1.4 LITERATURE SURVEY
The circuit speed is affected by the smaller feature size. In a digital system the speed is improved by the clock distribution. Many digital circuit cells are designed to use a single phase clock. By considering T flip flop it delivers a drive current that are rapidly changing functions of the transistors terminal voltages. This makes it difficult for designer to recognize the dimensions of each transistor that would result in the optimal performance of the overall circuit. So D flip flop is used. This has the best transistor dimensions and which maximize the slowest state transition and the clock period can be minimized .The circuit achieves high speed by reducing the capacitive load and sharing the delay between the combinational logic blocks and the storage elements. By this way it is suitable for realizing high speed synchronous counters. The operating speed of prescaler is mainly limited by that of divide by 4/5 counter which is the only partly operating at the maximum frequency. To maximize the speed of such a prescaler the D flip flops and NAND gates among the synchronous counter have to be optimized together.
Single phase clock policies are superior to the others due to the simplification of the clock distribution. They reduce the wiring costs and number of clock requirements high frequencies and simpler designs can be achieved. The extended true single phase clock CMOS circuit technique an extension of the true single phase clock consists of composition rules for single phase circuits using static, dynamic, latch, data precharged and NMOS like blocks. The composition rules enlarge the connection possibilities and avoid races. Additionally NMOS like blocks enhance the technique for high speed operations .
True single phase clock policy simplifies the clock distribution on the chip and reduces the transistor number. Thus higher frequencies and simple designs can be achieved. In extended true single phase clock handle data with rates that are twice the clock rate. These structures are formed by the connection of certain n and p data chains leading to lower power consumption or higher speed circuits. Here the block connections should be done according to composition rule .The advantage of dynamic logic over the more traditional SCL logic in terms of power consumption is due to reduced capacitive loads. In order to compare the two logic families both the size of the devices and the interconnection lengths have to be taken into account. A typical divide by 2 counter in SCL logic embodies 18 transistors, considering also the tail generators and the resistive loads. The achievable output swing, which is limited by the stacking of several transistors has to switch completely the source coupled transistor. The transistor driven by he input clock are placed nearest to the power rails in order to lower the internal node capacitance.
The MOS current mode logic circuit which is of high power consumption is commonly used to achieve the high operating frequency, while a true single phase clock dynamic circuit, which only consumes power during switching has a lower operating frequency. In the extended true single phase clock logic is proposed to increase the operating frequency. However, this causes additional power consumption. To achieve the low power consumption by reducing the switching activities and short circuit current in the D flip flops of the unit.
The prescaler is a synchronous circuit which is formed by D flip flop and additional logic gates. Due to the addition of additional logic gates between the flip flop to achieve two different division ratios, the speed of the prescaler is affected and the switching power increases. Various flip flop have been proposed to improve the operating speed. The width of the mos transistor can be increased to reduce the delay. This is known as gate sizing. Delay can be reduced by increasing the supply voltage Vdd and/or reducing the threshold voltage Vt of the mos transistors. Therefore, dynamic and sequential circuit techniques or clocked logic gates such as true single phase clock s must be used to reduce circuit complexity, increase the operating speed and reduce power dissipation.
High speed applications, low transconductance of MOSFET's imposes severe speed power trade off's, thereby limiting their advantage over silicon bipolar. The first generation of the technology scales only two dimensions: the channel length and gate oxide thickness. The remaining dimensions roughly correspond to other technology. To solve this issues,, ring shaped transistors are used. The ½ frequency divider employs two D latches in a master slave configuration with negative feedback. In high sped master slave dividers, it is common to design the slave as the dual of the master. So that both can be driven by a single clock. However, duality requires one of the latches to incorporate pmos devices in the signal path, hence lowering the maximum speed. To avoid this complementary clock signals are used.
PASS TRANSISTOR LOGIC
It acts as either NMOS or PMOS transistor .It is sufficient to perform logic operations. It results in a smaller number of transistor and smaller input loads. Compared to CMOS the source side of the logic transistor is connected to some input signal instead of power rails. Pass transistor logic (PTL) describes several logic families used in the design of integrated circuits. It reduces the count of transistors used to make different logic gates , by eliminating redundant transistors. Transistors are used as switches to pass the logic levels between nodes of a circuit, instead of as switches connected directly to supply voltages.
2.2 CMOS CIRCUIT DESIGN STYLE
Conventional static CMOS
Complementary pass transistor logic
Double pass transistor logic
Static and dynamic differential cascode voltage swing
Static differential split level
Dual rail domino logic
Enabled/disabled CMOS differential logic
2.2.1 Conventional static CMOS
Conventional static CMOS is used in most chip designs in the recent VLSI application. The schematic diagram of a static CMOS full adder cell is illustrated. The signals noted with '-' are the complementary signals. The PMOSFET network of the each stage is the dual of the NMOSFET network one. In order to obtain a reasonable conducting current to drive capacitive loads the width of the transistor is increased. This results in increased input capacitance and high power dissipation and high propagation delay.
2.2.2 Complementary pass transistor logic
Complementary pass transistor logic or "Differential pass transistor logic" refers to a logic family which is designed for certain advantages. It is common to use this logic family for multiplexers and inverters .CPL uses series transistors to select between possible inverted output values of the logic, the output of which drives an inverter to generate the non-inverted output signal. Inverted and non-inverted inputs are needed to drive the gates of the pass-transistors.
2.2.3 Double pass transistor logic
Double-pass transistor logic eliminates some of the inverter stages required for complementary pass transistor logic by using both N and P channel transistors, with dual logic paths for every function. While it has high speed due to low input capacitance, it has only limited capacity to drive a load.
2.2.4 Dynamic differential cascode voltage switch logic
DCVSL is a combination between the domino logic and the static DCVSL. The circuit diagram of the dynamic DCVSL full adder is given. The advantage of this style over domino logic is the ability to generate any logic function. Domino logic can only generate non inverted forms of logic. In the design of a ripple carry adder , two cells must be designed for the carry propagation , one for the true carry signals and another for the complementary one. Using DCVSL to design dynamic circuits will eliminate p-logic gates because of the inherent availability of complementary signals. The p-logic gates usually cause long delay times and consumes large areas.