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Abstract: In this designing, the aim is to design Butterworth low pass filter using the operational amplifier to consist of the filter circuit. Through calculating the number of order of filter, it chooses appropriate the circuit topology to implement the filter circuit. At the same time, it base on CMOS layout design rule to lay out the circuit and optimize size of passive component to minimize the size of component and power consumption. Finally, it adjusts circuit components to meet the specification and finish the whole filter circuit.
Keywords: Butterworth low pass, filter number of the order, layout, component.
According to filter amplitude-frequency of characteristics, the filter is classified the low pass filter, stop-bands filter, pass-bands filter and high pass filter. The low filter allowed low frequency signal to pass and attenuation to high frequency of signal. Although the ideal of filter do not implement in the real world, it uses the appropriate electronic components to produce the filter which close the characteristic of ideal filter. As for a low pass filter, the frequency response of Butterworth filter is usually flat in the pass band and roll off towards to zero in the stop band.. Comparing the other filter, the attenuation speed of Butterworth low pass filter is slower than other filter and without ripple. Generally, the low order Butterworth filter has rapid response, small overshoot but bad in test precision, while high order Butterworth low pass filter is good in test precision but has slow response, large overshoot and poor stability . When designing the filter, it usually designs a low filter for a typical Prototype filter, and then to modify this filter which we want to get.
A. Cadence Tool
Cadence Analog/Mixed-Signal (AMS) Design software supplies kind of designing editors for designing schematic and layout. In addition to these editors, it also includes simulation tools to simulate the customer designs. Cadence design tool provides the most comprehensive and flexible design tool kit for customer to verify and modify their design. When the customer finish their schematic designing and layout designing, Cadence provides LVS(Layout Versus Schematic) tools to verify difference between layout and schematic. At the same time, this tool also provides more convenient tools such as hierarchy editor for customer designs. In this experimental, Cadence tool is used for designing the Butterworth low filter circuit. And the design file uses 0.35um Process design kit for design. The whole design process shows at figure1.
A. The order of filter
The order of Butterworth low pass filter decides the speed of attenuation to amplitude-frequency of characteristics. The higher the order of Butterworth increases, the faster the speed of amplitude-frequency of characteristics decrease. At the same time, it also closes the ideal of amplitude-frequency of characteristics. The order number of Butterworth low pass filter determinates the rate of roll-off. The first order of filter's rate of roll-off is about 20dB/decade or 6dB/octave. And the second order of filter's rate of roll-off is about 40dB/decade or 12dB/octave. The structure of filter depends on the order of the filter; it's also determined by other electronic components which include resistances and capacitors within the filter circuit.
According to the cut-off frequency, pass band gain and stop band of cut-off frequency, it can calculate the order number of Butterworth low filter by using attenuation function.
In the equation 1, is Maximum pass-band attenuation, is pass-band cut-off frequency. In this case, the pass-band cut-off frequency is 2395.1 KHz. The stop-band cut-off frequency is twice time than pass-band cut-off frequency. And the pass band gain shall be 40dB; the stop band attenuation is 40bdB. It uses the above equation to calculate the number of order. This number order can be obtained, which is seventh order filter.
When the number of order can be determined, the each stage of gain will be calculation by using normalized Butterworth polynomials, because the Butterworth polynomials form is usually more complex. The table 1 shows the general form for normalized Butterworth polynomials. This research use seventh order for designing the Butterworth low pass filter, it chooses the seventh order's polynomial form the table 1 to calculate the each stage gain. Because this filter is odd number of order, the first order stage's gain need calculate by the second order stage. This process also can be calculated by Matlab, because Matlab supplies butter function for calculating and simulation the Butterworth filter.
B. the structure of filter
There are many different of filter topologies for designing the filter such as Cauer topology and Sallen-Key topology. These two filter topologies base on different realisation way. Due to the Cauer topology use the passive electronic components to male up the circuit, this topology is applied for a passive circuit. The figure 2 shows the Cauer topology.
On the other hand, Sallen-key topology not only uses the passive components into the filter circuit, it also uses the active component into the filter circuit such as op-amps. Each stage can be cascaded to accomplish the whole filter circuit. This topology usually is simple and easy to implement the filter circuit. As for this reason, Sallen-key topology is used in this designing. In generally, in order to implement high order filter circuit it needs to cascade low order Sallen-key circuit to reach the target. This designing needs to design a seventh order filter circuit, whole circuit need to cascade three the second order filter circuit and one first order filter to compose filter circuit.
The figure 1 shows the first order low pass filter circuit.
The figure 2 shows the second order low pass filter circuit.
From the figure 1 and figure 2, the cut-off frequency of Butterworth filter is determined by resistor R and capacitor C. Equation 2 represents relationship between RC values and filter response. Each of stage gain determines the value of resistor R1 and R2. In order to calculate the value of resistor R1 and R2, it needs to calculate the gain of each stage at first. According to the normalized Butterworth polynomial, the gain of each stage is affect by the coefficient. Equation 2 and equation 3 supply a method to calculate the gain of the second order by coefficient.
(2) (3) (4)
When the gain of each stage has been determined, the value of resistor R1 and R2 can be calculated. But the first order filter circuit and second order filter circuit has different equation to calculate the value of resistor R1 and R2. The ratio of R2 over R1 decides the gain of the first order stage. At the same time, this gain is usually as the high gain stage in the high order filter. On the other hand, the gain of the second order stage and resistor R1 and R2 has different relationship between them. The equation 3 shows this relationship.
In this equation, is the gain of the second order stage.
Except passive component resistor and capacitor, Sallen-key topology also has the op-amp to compose the filter circuit. Op-amp consists of three parts which include differential amplifier, gain stage and output buffer. When drawing the op-amp layout, some designing rules and factor of circuit optimizing need to be considered by designer. It uses cadence schematic editor to edit the op-amp schematic, and then simulate this schematic to achieve specification. If the simulate result do not reach the specification requirement. It needs to check circuit to judge whether circuit has any errors and to adjust dimension of transistor. Except the circuit connection error, the dimension of transistor is other important factor to affect the circuit performances in the analogue circuit. When the op-amp simulation has succeeded, the next step is to be created the op-amp layout from their schematic to implement the whole circuit layout. When designing the op-amp of layout, some design constraint rules need to be obeyed. If this rules is ignored by designer, the layout do not pass Cadence DRC check. And the designing errors are noticed and displayed by Cadence DRC tool in the layout. Distance of materials leads to the DRC error. If the distance of two parallel mental1 is less than 0.45um, the DRC tool notices error to designer to check these mental distances. If the mental2 has same situation, DRC tool also notices this error. So when the designer designs their circuit or chip, this situation should be avoided and considered in advanced.
The dimension of transistor, resistor and capacitor are another problem for designer to design their circuit or chip. These several method is supplied to designer for solving those problems. The large-width transistor can be spilt into small pieces and connected for minimizing the area of transistor. The length of the transistor is affected by the length of poly and the transistor overall width is the width of poly over active to multiply the number of "fingers". This method bases on to share drain and source connections between transistors. It also can be seen one transistor to be split several pieces and parallel them. All of transistors of the gates are tied together.
Width of transistor = (number of figners) * w (6)
W is the width of poly over active.
å›¾The figure 6 shows that the layout and schematic of transistor is split into smaller pieces. So in this op-amp designing, the pmos and nmos can be split for minimizing the component size, especially the size of pmos shrinking about 1/2. The table shows all of the shrinkage of the transistor area.
Resistor also can be divided into smaller fragments and cascade them for minimizing its area. Except reducing the dimension transistor and resistor to minimized the electronic component size, the substrate noise exits in the whole circuit and affect each component. The reason is that adjacent circuit injecting current into one another. the method is to place the guard rings around the transistor to avoid this effect. When placing the guard rings into the circuit, two points need to be considered. The first one is to place the p-substrate with p-tap guard ring which is connected to ground to surround nmos. The second one is to place the n-well with n- tap guard ring which is connected to vdd to surround the pmos.
The figure 8 shows the guard rings is used in the op-amp circuit layout.
So when the designer finishes the op-amp circuit layout and the layout pass the Cadence DRC tool checking, the layout needs to extract the layout into a netlist. Then, it uses the LVS tool to check whether the extracted layout netlist matches the schematic. If the result have some unmatched between extracted layout netlist and schematic, the designer base on the report form LVS tool to check these unmatched problem and modify them. There are some problems happen in the LVS. It needs to be considered by the designer. These problems can be classified three parts which include instance problem, nets connection problem, and terminate problem. The instance problem usually causes by different size of component between layout and schematic. So the designer needs to check every resistor and capacitor to make resistor and capacitor having same size in the layout and schematic. Short is another important problem in the nets connection problem. If the designer uses same metal to cross, it makes short to emerge unmated problem and cause another problem. At the same time, if the polarity of capacitor connects opposite, it also makes nets unmatched. Another problem needs to be noticed that the guard ring of capacitor need to connect vssa not connect the ground, no matter what this capacitor is in op-amp or Butterworth filter.
When the LVS has passed, it needs to simulate the op-amp layout. If the simulation result reaches the specification requirement, it starts to design the Butterworth filter circuit. According to equation 1 and specification, the order of Butterworth low pass filter needs seventh order. That means is that the filter circuit need one first order filter circuit and three second order filter circuit to cascade. The whole process of designing the Butterworth filter is same with designing the op-amp. The process is also from draw schematic to layout, and then checking the difference between schematic and layout by LVS tool. Finally, when the layout is passed LVS tool checking, it uses the simulation tool to simulate the layout get the result.
4. Result and Discussion
Using Cadence simulation tool to simulation the layout and schematic of filter circuit, the simulation result displays in the table 1.
Form the table 1, although their have same the electronic component parameter, the circuit of layout and schematic simulation have different simulation result. Because this filter circuit have parasitic component, these component impact on the whole circuit performance. Parasitic component exit in the Resistance of interconnect and Capacitance between layers. Cadence extractor tool supplies a function which it can extract parasitic capacitances into netlist file. However, the circuit of schematic do not simulate with parasitic capacitances. So the filter circuit of layout and schematic simulation have different result. In order to minimize the area of circuit and minimize the power consumption, it needs to optimize size of component, especially capacitor. The size of capacitor is usually bigger than size of resistor. When the cut-off frequency does not meet the specification, it can adjust the RC to meet requirement, basing on equation 1. If cut-off frequency is higher than the frequency which is at 3 dB point, the way which is decrease the value of capacitor can adjust the cut-off frequency to meet the specification. At the same time, as the area of capacitor decreases, the size of circuit will minimize than before. This smaller component means that the whole circuit of power consumption will be decreased.
In this Butterworth low pass filter designing, it needs to base on the specification to calculate the number of order, then to chose appropriate the circuit topology to design the whole circuit and calculate the circuit component parameter. As for a circuit and chip designing tool, Cadence tool is used for designing analogy filter circuit in this research. It requires the designer to obey the design rules to lay out the transistor and other components. In addition, several layout methods are used to lay out the op-amp and filter circuit, which include folding the large-width transistor, dividing resistor into small segment and using guard rings to avoid the noise from other component. Finally, basing on the specification and simulation result, the designer needs to modify their designing to meet the specifivation.