Design Of Low Power Router Using Dynamic Computer Science Essay

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This paper deals with the implementation of a low power and high performance 1x3 router, which is designed by using the dynamic power reduction technique i.e. clock gating. The main advantage of using Clock gating is that this technique reduces the activity on parts of the clock net by disabling the clock on flip fops when they are clocked only to store their values. A low power 1x3 router is designed by applying clock gating to the router RTL Verilog code by using Cadence. The 1x3 router accepts data packets on a single 8-bit port and routes the packets to any one of the three output channels. At the input side of the router design an eight state FSM is used to receive the data and transmit that data to either of the three output channels . Source code is written in Verilog HDL and the synthesis is carried out using RTL compiler tool from Cadence.

Index Terms-FSM, FIFO, Clock gating


Routers are devices used to transfer data packets between any two networks. It finds application in telephone network electronic data networks and transportation networks by creating an overlay of internetwork. Power is a major concern in today`s devices. Power consumption in a logic circuit is mainly due to the switching activity in the circuit. The switching activity can be reduced using clock gating. In this paper, we have implemented a 1x3 router using Finite State Machine (FSM) design . The overall switching between the states can be reduced by assigning state codes with lesser hamming distance .The local clocks in a circuit that are conditionally enabled are known as gated clocks.Large power-constrained systems [2], [3] use gated clocks as the core of dynamic power management schemes. In the implementationof our FSM, there are many states that do not change very frequently. Therefore clocking the FSM continuouslywastes power in the circuit .So by using clockgating we are able to detect when the machine is idle, we can disable the clock until a meaningful transition must be performed and the clocking must resumed at appropriate times. The presence of a gated clock has added advantage as it helps in reducing power in combinational and sequential elements.












Fig1. Block diagram of a 1x3 Router


In this paper we have designed a low power 1 x3 Router bytaking into consideration the following specifications:

A. Input/output Specifications

The routerroutes the 8-bit input data to any one of the three output channels,channel0, channel1or channel2. An active low input resetn is used to reset the router.The data is routed to the output only when the packet valid pin is asserted high. A synchronous clock is used for the design.

B. Data packet Description

Data packet consists of bytes sequences. The first byte is header byte, next set of bytes contain data, and the last byte contains parity. The header consists of a 2-bit address field and a 6-bitlength field [1]. In order to determine to which output channel the packet should be routed, the address field is used. Since we make use of a 1x3 router , an address '3' becomes invalid as there are only three channels through which the router routes. The number of data bytes specifies the length field. The parity can be of bitwise parity or even.

C. Router Input Protocol

All the input signals are active high .These signals are synchronized to the falling edge of the clock .As a result , input signals driven on the falling edge ensures adequate amount of setup and hold time. The packet_valid signal has to be asserted high simultaneously on the same clock as when the first byte of a data packet is driven onto the data bus of the router. The address bit in header byte ensures to which output channel the data packet should be routed. The router can route through any one of the channel , either channel 0, channel l or channel 2.

Once the last data byte has been completely driven, on the next falling clock, the packet_valid must be de asserted to low value .This operation completes the transfer of data packet. The err signal is asserted to high value whenever a packet with bad parity is detected.

D. Router Output Protocol

All output signals are active high. These signals are synchronized to the falling edge of the clock. The packet data is sampled at the falling edge of the clock. All together the router will drive and sample data at the edge of clock. The output port consists of the three channels channel 0, channel 1 or channel 2 is internally buffered by a 8 bit FIFO. The router will assert a high value ontoeither of the vld_chan_0 , vld_chan_1 , or vld_chan_2 signal when valid data appears on either of the respective channels of the output bus. The packet data receiver waits till it has space to hold the byte of the packet and then responds by asserting a high value to either of the three read_enb signals corresponding to each of the channel. The read_enb input signal is asserted high on the falling edge of the clock , where data is read from the respective channel bus. Whenever the read_enb signal remains active high, theither of the three channel bus will drive a data packet on the rising edge of the clock.


In this paper, the 1x3 router consist of a FSM module and 3 FIFO modules to route the data through either of the three channels.

FSM Design

An FSM is a controller that consists of combinational and sequential logic. The next state of the FSM is decided using the combinational logic. The current state of the FSM is stored with the help of sequential logic. The input side of the router is controlled by a five state FSM. On the basis of the FSM logic the router receives and transmit that data to either of the three output channels, channel 0, channel 1 or channel 2. Whenever there is a valid input data the FSM shifts to next state. The FSM checks the address bits and routes the data to either of the three channels. If the address bit is 11, the FSM goes back to the initial state and starts over again.

FIFO design

In this paper, a 8-bit FIFO is being used. By parallel placing

of three FIFO's at the output side , this structure will work as three output channels, and the respective channels are selected by checking the address bits.

Clock Gating

Clock gating is used to reduce dynamic power dissipation in many sequential cicuits. Clock gating saves power by disabling the flip-flops in the circuits that do not have to switch states frequently. Majority of the power dissipation in a logic circuit is due to the switching of the logic states.

Fig 2. Single clock, flip-flop based FSM.

Fig 3. Gated clock, flip-flop based FSM.

In our design Clock gating is applied by using the RTL tool from Cadence. As a result of clock gating , the dynamic power is reduced by 48%. Even though the power is reduced, the number of cells count has been increased. This increase is due to the placing of clock gating cells throughout the clock tree in the logic circuit.


In this paper, the design is simulated using NC launch tool from Cadence and the design functionality was verified.

The simulation result is shown below in the following


Fig 4. Simulation Results


The synthesis of our design is carried out using the RTL compiler tool from Cadence. The synthesis of top level module is shown in the figure below

Fig5.Synthesis result of the top level module

The power reports without clock gating are shown in figure 6 and with clock gating is shown in figure 7. These reports are generated by making use of the RTL tool from Cadence. A power reduction of 48% was achieved with clock gating.


Generated by: Encounter(R) RTL Compiler v09.10

- s233_1

Module: set

Technology library: slow

Operating conditions: slow (balanced_tree)

Wireload mode: enclosed

Area mode: timing library


Leakage Dynamic Total

Instance Cells Power(nW) Power(nW) Power(nW)


set 507 78.077 94812.525 94890.602

a1 169 26.026 31171.947 31197.972

a2 169 26.026 30710.251 30736.277

a3 169 26.026 29649.827 29675.852

Fig6.Power report without clock gating

Generated by: Encounter(R) RTL Compiler v09.10- s233_1

Module: set

Technology library: slow

Operating conditions: slow (balanced_tree)

Wireload mode: enclosed

Area mode: timing library


Leakage Dynamic Total

Instance Cells Power(nW) Power(nW) Power(nW)


set 552 86.720 48948.150 49034.870

a1 182 28.652 14815.527 14844.179

RC_CG _HIER _INST0 1 0.217 50.583 50.800

RC_CG_HIER_INST1 1 0.217 50.583 50.800

RC_CG_HIER_INST6 1 0.217 238.721 238.938

RC_CG_HIER_INST9 1 0.217 86.267 86.483

RC_CG_HIER_INST12 1 0.217 210.856 211.072

RC_CG_HIER_INST19 1 0.217 50.583 50.800

RC_CG_HIER_INST22 1 0.217 64.666 64.883

RC_CG_HIER_INST23 1 0.217 50.583 50.800

RC_CG_HIER_INST24 1 0.217 195.513 195.729

a2 182 28.652 15807.099 15835.751

RC_CG_HIER_INST2 1 0.217 341.219 341.436

RC_CG_HIER_INST3 1 0.217 50.583 50.800

RC_CG_HIER_INST4 1 0.217 64.857 65.073

RC_CG_HIER_INST10 1 0.217 121.950 122.166

RC_CG_HIER_INST13 1 0.217 50.583 50.800

RC_CG_HIER_INST14 1 0.217 161.788 162.004

RC_CG_HIER_INST16 1 0.217 50.583 50.800

RC_CG_HIER_INST17 1 0.217 64.666 64.883

RC_CG_HIER_INST18 1 0.217 261.294 261.510

a3 182 28.652 15207.896 15236.548

RC_CG_HIER_INST5 1 0.217 283.092 283.309

RC_CG_HIER_INST7 1 0.217 187.730 187.947

RC_CG_HIER_INST8 1 0.217 50.583 50.800

RC_CG_HIER_INST11 1 0.217 50.583 50.800

RC_CG_HIER_INST15 1 0.217 50.583 50.800

RC_CG_HIER_INST20 1 0.217 155.254 155.470

RC_CG_HIER_INST21 1 0.217 50.583 50.800

RC_CG_HIER_INST25 1 0.217 283.221 283.437

RC_CG_HIER_INST26 1 0.217 50.583 50.800

RC_CG_HIER_INST27 1 0.217 253.829 254.045

RC_CG_HIER_INST28 1 0.217 249.794 250.011

RC_CG_HIER_INST29 1 0.217 296.571 296.787

Fig7.Power report with clock gating


The backend flow of our design is carried out using the Soc encounter tool from Cadence. The physical design flow is shown below

Fig7. Backend flow of the design


In this paper, a low power 1x3 router was designed by reducing the dynamic power with the help of clock gating technique. By applying clock gating to the design, the dynamic power was reduced by 48%. Also 90% of the cells present in the design were gated. Consequently the area has also been increased, as clock gating cell were introduced into the design. A summary of the clock gating applied to the design is shown in the report below


Category Number %


RC Clock Gating Instances 30 -

Non-RC Clock Gating Instances 0 -


RC Gated Flip-flops 228 90

Non-RC Gated Flip-flops 0 0

Ungated Flip-flops 24 10

Total Flip-flops 252 100