Design Cmos Operational Amplifier Computer Science Essay

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Operational amplifiers are a key device in analogue systems. The op-amp operational amplifier is usually used for amplifying small signals and performs the function of a voltage controlled current source. Generally, the op-amp has high gain, high input resistance and should function over a variety of frequencies. The design of op-amp usually can be divided two steps that are for most part independent of one another [1]. The first step is to choose proper structure of op-amp. Other step is to select dc current, to calculate size of transistors and to design the compensation circuit [1]. This goal of assignment is to design a COMS Op-amp for D/A converter buffer by using a standard 0.35um technology.

Basic circuit Architecture

At the beginning of design, the first step is to choose a basic structure of op-amp. Because of the resistive load we decide to use a two stage op-amp to perform this design. The two stage operational amplifier consists of four parts, which includes an input differential amplifier, a second gain stage, compensation circuit and a bias circuit [1]. In generally, the first stage provides higher gain for the op-amp and the second stage supply high swing. The generic circuit schematic of a two stage op-amp can be represented by the block diagram shown in figure 1.

Fig. 1 the two stage op-amp block diagram

The two stage Op-amp circuit schematic shown as figure 2. The first stage is consisted of a differential pair. It provides the differential to single ended conversion. At the same time, this stage also provides a good portion of overall gain to improve noise and offset performance [1]. Because PMOS differential pair has better slew rate than NMOS differential pair, we choose PMOS differential pair to consist of the first stage. The second stage is inverter amplifier that provides high output swings. The bias circuit provides same reference current for first stage and second stage. So the bias currents in the two stages will be controlled together. The purpose of the Compensation Circuit is to maintain stability when negative feedback is applied to the op amp [2].

Fig. 2 the two stage op-amp schematic diagram

Circuit design

Specification requirement

Table 1 Specification for the CMOS Op-amp [2]

Specifications

Proposed value

LF Gain

≥60dB

Full power Bandwidth

>100KHz at 2 p-p

Phase Margin

Settling Time

≥45°

<1% of final value with in 500ns

Supply Voltage

Input Common Mode Range

Output Common Mode Range

Output Load Condition

Bias

0V ~ 3.3V

0.2V ~ 1.2V

0.4V ~ 2.4V(10KΩ feedback resistances)

and

(ideal source)

Circuit analysis

In the first stage, the current mirror (M3 and M4) is used for convert differential to single ended [3]. The current from PMOS (M1) is mirrored by current mirror and subtracted from the current from PMOS (M2). The signal contributions of the two currents multiplied by the output resistance of the first stage give the single ended first stage output voltage. The resulting signal constitutes the input of the second gain stage. The second stage is a current sink load inverter. PMOS (M6) is the driver while PMOS (M7) acts as the load. Capacitor is used to lower the gain at high frequencies and provide the compensation for the op-amp.

Hand Calculation

Determine to ensure phase margin > :

The phase margin that is less than will cause ringing in the output response. So we need ensure that the phase margin is bigger thanin order to ensure good stability. The large phase results in less ringing in the output response. So we desire to obtain a phase margin which is at least, with preferable in most situations [3]. According to op-amp design procedure which is introduced by Phillip Allen's book---CMOS Analog Circuit Design, the second pole must be higher than 2.2GB in order to reach a phase margin.

So the value of is set to 7pF.

Choose as 7pF and to calculate:

The below equation represent the relationship between, unity-gain bandwidth and capacitor. According to specification requirement, the LF gain should be at least 60dB and op-amp need have an open loop gain of at least 40dB at 100 KHz. The open loop gain at 40dB will roll down by 20dB/decade until the gain reaches 0dB. So we can know the unity gain frequency is at least 10MHz.

Decide M1 size using, the aspect ratio is directly obtained from :

The MOS transistor characteristic bases on small signal analysis, we can obtain the below equation from

, ( )

The bias current, supplies by an idealsource. We assume that is two times than.

Decide M3 and M4 size using the lowest common mode input voltage specification:

For saturation,

So

Decide M5 size using the maximum common mode input voltage specification:

Calculate M6 size using.

We assume that the location of loading pole is placed at 2.2 times GB for a phase margin of 60°. According to this assumption and equation, we can use the below equation to calculate[4].

,

So,

Find M7 size:

Calculate M8 size using the aspect ratio

, so the aspect ratio

We assume that the aspect ratio of M8 equal to the aspect ratio of M5. And then we set the aspect ratio of M1 two times of the aspect ratio of M8.

So,

Determine to adjust the overshoot to meet specification

Calculate the total gain

Base upon the result of calculation, the total gain reaches 79.55dB. It satisfies the specification requirement.

Simulation

In order to test this two stage Op-amp circuit whether reach the specification goals, we use five test circuits to test op-amp circuit. Basing on specification requirement, all of simulations used 30pF for (capacitance load) and 10kΩ for (resistance load).

Gain/Phase margin Simulation

The ac frequency sweep analysis is used for examining the LF gain, gain bandwidth and phase. The test circuit 1 is used for testing op-amp's gain and phase margin. The test circuit 1 is shown in figure 3. In this circuit, the positive input terminal is cascade of the AC voltage source and DC voltage source.

Fig. 3 Op-amp basic ac (small signal) gain/phase test circuit

After the simulations by using gain and phase simulation, we find the result of simulation does not reach the specification requirement. We need adjust size of transistor and capacitor to reach the requirement.

Gain adjustment

The total gain of op-amp can be represented by below equation.

Base on the total gain op-amp equation, we can adjust the value of,, ,,and . Comparing to the second stage gain, the first stage provide high gain for the whole circuit. So a proper approach is to adjust the second stage to change the total gain. We choose to adjust the value of.

Phase adjustment

It will cause ringing in the output response when the phase margin is less than. Base on the Miller compensation theory, the dominant pole will be move to the original point when the compensation capacitor increases [3]. Meanwhile, the second non-dominant pole will be move to opposite direction [3]. It results in bandwidth reduction and phase margin will be changed. In addition, the specification requires that the open loop must reach 40dB and the frequency is greater than 100 KHz. We need change the value of the compensation capacitor to meet requirement. According to simulation analysis, we choose 3.45pF for the compensation capacitor.

The graph in figure 4 shows the result of simulation. The value of DC voltage source is set to 0.2V The LF gain is 61.01dB. When the open loop gain reaches 40dB, the frequency is 155.9 KHz. This frequency satisfies the specification requirement which is bigger than 100 KHz at point of 40dB. The phase margin is 63°. The graph in figure 5 shows the result of simulation when the value of DC voltage source is 1.2V. The LF gain is 76.18dB and the phase margin is 57°. The frequency at point of 40dB is 168.22 KHz. When the DC voltage is within range 0.2V ~ 1.2V, the gain and phase achieve the proposed specifications.

Fig. 4 Gain and Phase simulation result (DC voltage is 0.2V)

Fig. 5 Gain and Phase simulation result (DC voltage is 1.2V)

The test circuit 2 shows in the figure 6. Comparing to test circuit 1, the test circuit 2 have large capacitor at the negative input terminal. The figure 7and 8 shows result of simulation. When the input voltage is 0.2V and 1.2V separately, the total gain is separately 67.36dB and 70.66dB. The phase margin is 68° and 55°. The figure 9 and 10 shows the result of simulation when output voltage is 0.35V and 2.8V. According to figure 9 and 10, the gain is bigger than 50dB for output voltage in the range 0.35V and 2.8V.

Fig.6 Op-amp ac (small signal) gain/phase test circuit

Fig. 7 Gain and Phase simulation result (DC voltage is 1.2V)

Fig. 8 Gain and Phase simulation result (DC voltage is 0.2V)

Fig. 9 Gain simulation result (the output voltage is 0.35)

Fig. 10 Gain simulation result (the output voltage is 2.8)

Output voltage range simulation

In order to test the range of output voltage, we use the test circuit 3 to examine whether output voltage achieve the specification requirement. The figure 11 shows the DC test circuit.

Fig. 11 Op-amp DC sweep test circuit

According to specification, it requires the input common mode range from 0.2V ~ 1.2V and the output common mode 0.4V ~ 2.4V. The linear curve in the graph represents the range of output voltage. When the output voltage is 1.2V, the output voltage is 0.4V. Similarly, when the input voltage is 1.2, the output voltage is 2.4V. So the result satisfies the specification requirement.

Fig. 12 the DC sweep simulation result

Settling time simulation

The settling time and overshoot can be test by the large signal step response test circuit. This test circuit requires cascading five pulse voltage sources. Each voltage source meets 0V ~ 2V step and 1ns rise time. The test circuit is shown in figure 13.

Settling time adjustment

The settling time is that the output voltage achieves the expected output voltage within a given accuracy (usually 0.1% or better) [1]. It is measured from the end of slewing period. So the settling time depends on the slew rate and damped oscillation time. Base on specification requirement, settling time must satisfy less than 1% of final value with in 500ns. The figure 14 shows the result of simulation. The settling time is 0.199us. This value is less than 500ns.

Overshoot adjustment

In order to reduce overshoot, we can place a resistance in series with the compensation capacitor. So according simulation analysis, we adjust the value of this resistance to 4.1KΩ. The overshoot meets the specification requirement basing on simulation waveform.

Fig. 13 Op-amp large signal step response test circuit

Fig. 14 large signal step response simulation result

Full power bandwidth simulation

In order to test whether the full power bandwidth is greater than 100 kHz at 2 p-p output, we use the large signal sine full power bandwidth simulation test circuit to examine this requirement. The input is cascaded by a sine voltage source and DC voltage source. We separately use 10KHZ, 100 KHz, 1 MHZ for the working frequency of sine voltage source to test.

Fig. 15 Op-amp large signal sine full power bandwidth test circuit

The figure 16 separately display output and input voltage waveform at different working frequency. Comparing with output waveform and input waveform, these waveform do not occur waveform distortion. The output voltage is nearly at 2.2V

The sine voltage source use 10KHz working frequency

The sine voltage source use 100KHz working frequency

The sine voltage source use 1MHz working frequency

Conclusion:

After all the simulations by using parametric analysis, all parameters are adjusted to achieve optimized performance (Table 2)

Table 2 Summary of device size parameter

Device

Calculate Size

Simulated Size

7pF

3.45PF

1.28KΩ

4.1KΩ

M1

M2

M3

M4

M5

M6

M7

M8

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