Design And Implementation Of Video Frame Grabber Computer Science Essay

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Abstract - There are many video frame store cards available in the markets which are dependent on PC or PC compatible computers. But there are so many applications where we need a video frame store which can be operated by any computer. For example, in remote sensing satellites, a video frame grabber is required which is operated by a special computer. This paper describes such type of Video Frame Grabber (VFG ) for a monochrome CCD camera of 208 x 288 pixels. The major components used are a video amplifier, a high speed Analog-to-Digital converter (ADC), high speed binary counters and a Universal Asynchronous Receiver Transmitter (UART).The other distinct feature is that it is designed with discrete logic components, i.e., neither microprocessor nor microcontroller is used.

1. INTRODUCTION

Most of the Video Frame Grabbers are microprocessor based, that is, all the functions like address generation, A to D conversion clock, Read/Write clock and other control functions are handled by microprocessor [6]. In this design, the above mentioned functions are carried by logic circuits. The pixel clock of camera is fed to the binary counters which generate address for memory bank. The same clock with a small delay in microseconds is used as conversion clock required by ADC. The horizontal synchronization pulse of the camera is used to enable and disable the ADC when there is video and no video at output respectively. When there is no deo ( during retrace period) a special binary code called sync. code (1010.….…..……………....1010) is stored in the memory as a start or end of line. The clock, horizontal sync.and video output are taken from the CCD camera. At the end of the Horizontal pulse ADC starts conversion into digital, and at the same time those digital data are stored into RAM. On during next pulse, ADC becomes disable and a code called sync. code ) is stored into RAM as end of a line of video. This can be better understood from the block diagram of Image Store Unit (Fig.1).

The memory required of a frame can be designed by multiplying no. of pixels in a frame with no. of bits of ADC. In this grabber memory of 208x288x6 (360 k) bits is used to store a frame. The 6 bits per pixel are enough to get 64 grey levels and for monochrome images more than 64 grey levels can not recognized by human eye [4].

The RS-232 port is used to transfer data from Video Frame Grabber to any type of computer. In this design, the PC is used. The program to store data in computer is written in Turbo-Basic and the program to reconstruct the image is written in Turbo-C. The flow chart of image reconstruction software namely FCIRS is given and the software can be provided on request.

The major sections of an Image Store Unit of video data, are

i) Address generation,

ii) Digitization and

iii) Controlling & Storing the digitized video data into memory in synchronized manner.

2. VIDEO PROCESSOR & ADC:

The video processor shifts the dc level of video signal and amplifies it to make compatible with an ADC (Analog to Digital Converter) which is unipolar. The ADC used in this design is CA3300, which has 6 bits output.

3. ADDRESS GENERATOR

This block generates addresses both in read and write modes.. In write mode it takes the input from pixel clock of camera and at every clock the address is generated, video signal is digitized and stored in the memory bank. During the period of H/Sync. (Horizontal Sync.) pulse the sync code is stored. In read mode it generates the address using its internal clock by dividing the factor required for particular baud rate. (In this case the baud rate is 9600).

4. CONTROLLING & STORING (DIGI- TIZED) DATA INTO MEMORY: The address generation, digitization and storing data in proper memory location requires precise synchronization. It has the following components:

4.1 DELAY CIRCUIT: The delay circuits are used to synchronize the pixel data, dig ital conversion and memory location.

4.2 SYNC. CODE GENERATOR: It generates the code which is stored in memory at every horizontal sync.pulse. During this period ( H/Sync.) the ADC is disabled by CS (chip select).

6. CIRCUIT OPERATION

When the fame sync. is received the control circuit will reset the counter for address generation, enable the memory bank and enable the A/D converter. At every line sync. (or H/Sync.) pulse (during retrace time) when there is no video, the ADC will be disabled and sync. code will be stored into memory. During horizontal scanning, the ADC will be enabled and video data (digital) will be stored byte by byte into memory bank. There must be synchronization among address, digitization and writing into memory. That is, first of all address should be generated, then analog signal of first pixel be converted into digital and finally the data of first pixel is stored into first memory location. As shown in figure1, the clocks for address increment, data conversion and writing into bank memory are delayed with each other.

5. MEMORY BANK: The size of memory depends upon number of frames required to be stored, and number of pixels of camera sensor.

ADC

C/Clock

Video Amplifier & DC Level Shifter to convert bipolar to unipolar signal

B

U

F

F

E

R

MEMORY

BANK

Data input R/W

Address

Input Video

Syn Code Generator

Control for R/W

UART

H/Syn.

Address Generator

Delay

P/Clock

S/out

Fig.1 The block diagram of a Video Frame Grabber

Video

Pixel Clock

Horizontal Sync

Fig.2 The video signal, pixel clock and horizontal sync. waveforms available at camera connector are applied to VFG to digitize analog video signal and store into the memory bank of VFG in synchronized manner.

7. DATA ACQUISITION PROGRAM:

Following is the program to acquire data from stored data can then be used to reproduce

grabber and store into computer memory. The the image on computer screen.

rem thru RS232(COM1)and to store

on file

on error goto 999

rem fx$="c:\tb\test.dat"

rem input "Filename (default

test.dat)";f$

rem if f$ = "" then f$ = fx$

open "c:\tb\test.dat" for output as #1

cls

rem on com(1) gosub 500

com(1) on

55 open "com1:9600,o,8,1,cs,ds,cd" for input as#2 len=1

field 2, 1 as t$

500 for i=1 to 64000

503 get 2:print t$;

504 print#1,t$;

505 next

print "done"

999 print err : close#1,#2:end_

Fig. 3 The circuit diagram of a Video Frame Grabber.

START8. IMAGE RECONSTRUCTION PROGRAM: The image reconstruction software is written in Turbo-C and can be provided on request. The flow chart (FCIRS) is given below:

Check Sync.

Code

Is Sync.

Code?

N

Y

Read Code

and delete

Is End of

Code?

N

Y

Read pixel from data file and put on

computer screen

Pixel = Pixel +1

Is

Pixel=

208 ?

N

Check next code

Y

Is

Sync Code?

Y

N

End

Fig.4 An image grabbed by Grabber With Discrete Logic.

9. RESULTS AND DISCUSSION : The images stored and reproduced on a computer screen of a monochrome CCD camera of 208 x 288 pixels which is a low resolution camera. The result which is an image of satellite is shown in Fig. . The quality of image depends upon the resolution of camera as well as quality of grabber. This grabber can be used with high resolution CCD camera. Similarly, grey levels can be enhanced just by adding ADCs.

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