Design And Implementation Of Digital Circuits Computer Science Essay

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Abstract - Digital design circuits have applications in a large number of fields such as communication, automotive and entertainment industry. The applications of digital circuits are becoming more and more in daily use electronic devices such as computers, cell phones, televisions and remote control devices etc. So a need arises to have a procedure to design chips from the digital circuits. There are number of software's which are currently used in the designing of chip from the digital circuits. However and to the best of author's knowledge there are very few procedures available which can be conveniently used to develop the digital circuits chip. Verilog and VHDL are a hardware description language which has attracted an attention of large number of digital designers. In this paper we suggest a procedure by which digital circuits are designed from code in verilog or VHDL.

Keywords

Hardware description language, Chip fabrication

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I. INTRODUCTION

Digital circuit [1] is an electronic circuit that can process only finite number of states. The two most common states of the digital circuits are represented in the binary bits of either 0 or 1. Digital electronic circuits are usually made from large assemblies of logic gates which is a simple electronic representation of boolean logic functions (AND, OR, NOT etc). Digital techniques [4] are useful because it is easier to get an electronic device to switch into one of a number of known states rather than to accurately reproduce a continuous range of values. Digital circuits are immune to noise, can often manipulate signals more effectively and can be stored and duplicated without degradation. These all reasons helped digital circuits to succeed and to be used in most of the real world applications. A digital circuit is often constructed from the small electronic circuits known as logic gates which can further be used to create combinational logic. Logic gates commonly use a few number of transistors in order to reduce their size, power consumption and cost, and to increase their reliability. Integrated circuits (IC's) are the least expensive way to make logic gates in large volumes which are the small wafers of semiconductor material in the form chip. Performance of IC's is high and the cost is low because the chips, with all their components, are printed as a unit by photolithography. Chips because of their small size are used in number of devices such as cell phones, radio sets, laptops and televisions etc.

In electronics, a hardware description language (HDL) is a language for the formal description and design of electronic circuits, and most-commonly, digital logic. It can describe the circuit's operation, its design and organization, and tests to verify its operation by means of simulation. HDL's are standard text-based expressions of the spatial arrangement of the gates. Languages which are only used to express circuit's connectivity between hierarchies of blocks are properly classified as netlist languages used on electronic computer-aided design (CAD).

HDL's used for digital circuit design include:

' Verilog HDL [3]

' VHDL

' ABEL HDL(Advanced boolean expression language) [5]

' AHDL (Altera HDL)

' CUPL (Language from logical devices)

In the semiconductor and electronic design industry, verilog is a hardware description language (HDL) used to model electronic systems and is most commonly used in the design, verification, and implementation of digital logic chips at the register transfer level (RTL) of abstraction. There are many software's and tools for the designing and the fabrication. Few of them are tanner, cadence etc. This software's helps in the designing of schematic view which further generates the layout and then the padding. In this paper cadence tools are used for the implementation of Ex-or gate. Cadence tools [2] which are ambit build gates, encounter, and virtuoso are used on the UNIX environment.

Ambit build gates: Typically a digital design starts from Verilog netlists. This tool is used to convert verilog code into netlist.

Encounter: It creates a layout from the netlist. This tool is for the creation of digital integrated circuits. This includes floorplanning, synthesis, test, and place and route.

Virtuoso: It adds the pads with the input and output pins of the layout. This is a tool for designing full-custom integrated circuits; includes schematic entry, behavioral modeling, circuit simulation, full custom layout, physical verification and extraction.

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II. PROCEDURE

A procedure has been described to design a chip. To create a chip the verilog code is written. This verilog code should be converted into the netlist so that it can be used by the encounter. The steps involved for the chip designing for the Verilog/VHDL code till the padding are as follows:

' Verilog code is written.

' Ambit build gates create a netlist.

' Encounter imports this netlist to generate a layout.

' Routing is done in the encounter to connect the input and output pins with the components (gates).

' Layout is saved in *.gds and *.def format.

' *.gds and *.def files are imported in the virtuoso to add the pads for each of the input and out pins.

III. IMPLEMENTATION

Ambit built gate

Ambit build gates tool is used to convert the verilog code to the netlist. This netlist is a kind of verilog code which is converted by Ambit build gates so that it can be understood by the encounter. In this netlist the gates are defined as a separate component.

' Make a directory.

' Open the terminal and invoke ambit builds gates by the command 'bgx_shell'

' Type the following commands in the shell window:

o read_tlf ami06 (read the library)

o set_global hdl_vhdl_environment synopsys (control the different library used for the project)

o read_verilog code_name.v (read the verilog code with name code_name.v)

o do_build_generic (this will do the synthesis)

o do_optimiz (this will map the synthesized logic to ami06 std cells)

o write_verilog netlist.v (write a netlist netlist.v)

Generation of layout using Encounter:

This tool imports the netlist generated by the Ambit build gates to make a layout. Here the dimensions for the layout can be set according to the requirements. Voltage and ground pins are added for the power supply. Gates and input-output pins are placed inside the layout and routing is performed to connect these pins with the gates.

Encounter setup: Type these commands in the terminal

% cd $CDSVHDL

% mkdir fe

% cd fe

%cp $DSMSE/ece753.conf ece753.conf

and then type encounter in the terminal, encounter window will pop up as shown in the Fig 1.

Fig. 1. Encounter window

' Import the netlist using the tab in the encounter window 'File>import design'.

' Design window will pop up.

' In the design window click 'Load' on the bottom

' Browse for 'ece753.conf'

' Press OPEN

' Browse for the netlist created by ambit build gates.

' Then check the auto assign.

' Press OK.

' Layout boundary will be created as shown in the Fig. 2.

' Set the floor plan dimensions using tab Floorplan>specific floorplan

' 'Add rings' command will add the power rings in layout which are voltage ring (vdd) and the ground ring (gnd). To add rings the different metal layers are used. For top and bottom ring metal 3 layer is used and for left and right ring metal 2 layer is used.

' Route > Special Route. This will add power and ground lines for the layout.

Fig. 2. Encounter window with the layout boundary.

' Use 'Place Jtag' and 'Place standard cell' commands to place components.

' Route > Nanoroute>Route. This will connect the components with the input, output and power pins.

' Fill the empty space in the layout using the following command. Place > Physical Cell > Add Filler.

' To check the connections between pins and component do the Verify > Verify Connectivity.

' Warning will be given if there are any unconnected pins with the component.

' Remove the errors if any and again verify the connectivity.

' Save the file in *.gds and *.def file format using the following commands.

' File> Save > GDS/OASIS

' File> Save > DEF

' Close Encounter

Final layout in created by encounter is shown in the Fig. 3. This layout will be used in the further step by virtuoso for the padding and routing.

Fig. 3. Final layout in encounter

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Virtuoso

This tool is used at the end to import the layout that is generated by the encounter. A symbol is designed for the imported layout. After the importing is done, pads are placed for each of the input, output, ground and the voltage (vdd) pins in the layout. This process is known as padding. Routing is done to connect the pads with the input-output pins using different metal layers. The steps involved for the padding and routing in virtuoso are as follows:

Open terminal and start virtuoso by typing the following commands.

%virtuoso &

' Virtuoso library manager window will pop up along with the cds.log window.

' Library manager is as shown in the Fig. 4.

' Log window is shown in the Fig. 5.

' Create a new library in the library manager using the tab File > New>Library.

' Create library window will open and name the library and click OK.

' After creating the library import the *.gds file.

' To import the *.gds file go to the virtuoso log window and then File>Import> Stream.

' A virtuoso Xstream IN window will pop up.

' In virtuoso Xstream IN window click on the options tab.

Fig. 4. Virtuoso library manager window

Fig. 5. Log window

' Window StreamINOptions will pop up. In this window in the geometry tab check on the snap to grid.

' In layers tab click on the load file and browse for StreamOut.map file.

' Press OK.

' In virtuoso Xstream IN window under the Stream file tab browse for code.gds2 file created using encounter in the last step.

' Fill the destination library with the library name created in the first step of virtuoso.

' Attach the technology library.

' Press translate to translate the *.gds file to the virtuoso file format. This step also creates different cell views in the library manager.

' Close virtuoso Xstream IN window.

' Import the *.def file using File> Import> DEF tab in virtuoso log window.

' Select DEF file window will pop up.

' Browse for the .def file.

' Fill the target library name with the library name created in the first step of virtuoso.

' Press OK.

' Create a symbol in the same cell that has been created by gds import.

' To create a symbol go to library manager File >New> Cell View. New file window will pop up.

' In the new file window, change the type to schematic.

' Symbol of Ex-or gate will look like as shown in the Fig. 6.

Fig. 6 Symbol of Ex-or gate in virtuoso

' This symbol will be used in the schematic view for the padding.

' To do the padding, create a new cell.

' This is a cell in which both the schematic and the layout will be created.

' Create a schematic view the schematic view look like as shown in Fig. 7. This schematic view will have pads for the each input, output, Vdd and ground pin.

' After creating a schematic create a new cell view for the layout.

' Layout L editor window will open. Go to launch >layout XL.

' Layout XL editor window will open.

' Press generate from the source button to import pins from the schematic view.

Fig. 7 Schematic view in virtuoso

' Type placepads command in the virtuoso log window to place pads in the layout XL window.

' Arrange input, output, vdd and ground pins on the pad space.

' Do the auto routing to connect the pins with the actual layout.

' Check DRC and LVS to verify the connectivity.

' The final layout after padding is as shown in the Fig. 8.

Fig. 8. Final layout after padding

IV. CONCLUSION

In this paper a procedure for the designing of chip from the verilog code has been given and its implementation is shown by following this procedure for the design of Ex-or chip. ICs have consistently migrated to smaller feature sizes over the years, allowing more circuitry to be packed on each chip. So apart from the chips being used in the computers as RAM's, digital microwaves etc can also be used for the portable devices because of their high performance, fast speed and low power comsumption.

V. REFERENCES

[1] M. Morris Mano. Digital Design, Third Edition

[2] Charles L. Brown ECE Department, at the University of Virginia in Charlottesville 'http://www.ece.virginia.edu/~mrs8n/cadence/tutorial1.html'.

[3] Frank Vahid 'Digital Design with RTL Design, VHDL, and Verilog' University of California, Riverside

[4] High-Speed Digital Design 'Howard W. Johnson and Martin Graham'.

[5] John F. Wakerly 'Digital Design Principles and Practices'.