Ddr3 Memory Controller For A Random Number Generator Computer Science Essay

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The Memory controller is the soul of a memory system. The DDR3 memory is very high speed and the state of the art technology. The Memory controller will control the DDR 3 memory using Verilog HDL for implementation and would provide a Synthesizable net list. The project would be mainly focused on designing the Memory controller and use a random number generator at the output and input of the controller which would provide random address and data at the input and obtain a random data at the output. The probability or the randomness of the entire system can be increased by utilizing the entire memory and use of high speed DDR3 module for burst read and write operation. The aim of the project is to develop a random number generator using the powerful technique to access memory location using DDR3 memory controller.

The memory controller design has always been a topic of interest for everyone. There are various memory but to control them for its effective use and to maximize the speed of operation we need a fast and a highly effective memory controller. Apart from a memory controller one of the major aspect to test the functionality of the controller we need a good random number generator to generate random memory address and random data and these address are accessed by another random number to retrieve data. So a random number generator is very useful in the field of verification and testing various applications. If we have a good random number generator it reduces the error caused by the redundant data produced by a random number generator. Using a memory controller as a powerful tool to access memory will reduce the error probability and increase the randomness of the desired output.

There are various memories available which we can use, but to have a very effective memory we use the latest memory which is DDR3 SDRAM where DDR stand for Double data rate and SDRAM stands for Synchronous Dynamic Random Access Memory. The double data rate means that for a given clock frequency the memory access is double the rate of the given clock frequency. DDR3 is the latest technology used for the random memory access. There have been previous versions of the same family as DDR, DDR2 and the latest one is the DDR3 SDRAM. The memory used in our PC is DDR3 memories and a Low Power memory are used in Mobile and camera devices are LPDDR SDRAM.

The Memory devices have specifications as defined by JEDEC. So to design a memory controller we need to satisfy the specs as defined by JEDEC data sheet for any memory controller. Memory controller becomes the intermediate block between the CPU and the memory. The memory controller acts as the controlling unit for the memory.

The objective of the project is to develop a memory controller for a DDR3 SDRAM and use a random number generator to store data on the memory and access that memory randomly to get the random numbers. This will suffice two purpose as it will test the functionality of the controller as well as would generate a random number pattern which could be used to any other application.

INTRODUCTION

The DDR3 memory controller can be a part of a very large chip or we can have a different block inside or outside the memory. Traditionally there has been use of the RAM, ROM, DRAMs, and SDRAM. But due to technological advancement people are moving to a newer technology and fast access time to memory. DDR have brought in a revolution in field of accessing the memory data in more efficient and in a fast manner. Figure 1. Below shows the basic functional block diagram of a DDR SDRAM taken from Micron DDR data sheet. The basic idea is to controller the memory using FSM to control the various read, write and refresh operation of the DDR3 memory. Designing of the memory controller will be done in Verilog HDL and the verification of the entire controller will be carried by using Verilog testbench. The test bench would be robust in testing all the desired functionality based on the specification.

Figure 1. DDR SDRAM Functional Block Diagram for 256 MB. [1]

Random number generator would be used in order to test the entire controller as well as the random number would access the random number stored at the random memory location. Accessing the data would make the probability much higher which would result in reducing the error occurred by a random number generator.

Scope of the projectFigure 2. shows the basic block diagram of the entire project. The

Figure 2. Functional Block diagram

The Memory controller will be designed as per the JEDEC specification using Verilog coding. The interface will be designed in order to interface the controller to the memory. The random number generator would be either used from previously designed random generator module in order to validate the functionality as well as the generation of another random output.

The DDR3 memory module can be obtained for testing from Xilinx online for testing and verification.

The DDR3 SDRAM is used as it is the latest available memory block and used in wide range of application now. DDR3 is low power and low voltage. DDR3 as compared to DDR2 have a higher precharge and high operating frequency. Figure 3. Below shows similarity and differences between DDR2 and DDR3 SDRAM

Figure 3. Comparison between DDR2 Vs DDR3 [6]

The functional block diagram of the memory controller is shown in figure 4. The various block of the memory controller can be listed as follows.

Address Decoder

Request queue

Arbitration

Command queue

Memory interface

Data path

HYPOTHESIS

If a memory controller for a DDR3 is developed for low power and high speed it would be useful for any memory controller industry and for a actual chip can be fabricated in future using the design and architecture. The random number has a wide range of application in verification hence this project can be seen as a revolution in field of memory controller and verification.

LITERATURE SURVEY

There is research going on currently in designing a robust memory controller for a latest memory technology DDR3. There is paper published on various topics for other memory controller which would be helpful in developing a memory controller for DDR3. If we achieve to produce a functionally running Verilog code for DDR3 memory controller this would be really helpful for various other memory controller designers in future.

PRESENT STATE OF THE ART

The main objective of developing a memory controller is to produce a memory controller which would be helpful to a industrial point of view. Currently the industries are still using the DDR2 memory and trying to migrate on DDR3 SDRAM. Industries are still thinking various ways in which the DDR2 memory controller can be used for the DDR3 memories. DDR 2 memory controller is widely used currently in most of the applications. The random number are used in various application but developing a random number which has negligible error probability of occurrence of repeated number after a series of random number.

Due to the wide range of application of both the individual component makes this project really helpful for industrial perspective and also a very important topic from research point of view.

MOTIVATION AND APPLICATIONS

The main motivation came from the current state of art technology and the keen interest in the field of Memory controller design. It has been always fascinating to know more about memory design and also develop a memory control design for any DDR SDRAM. Although the memory controller have same technique for basic operation but the latest DDR3 seems to be the latest technology and operates on really low voltage hence it becomes challenging to design a memory controller for such a fast memory. So looking at the challenges involved and the amount of knowledge we would obtain from this project we selected to design it as a master’s project. The memory controller will be used in various IC manufacturing company related to memory devices. As a scope of this project we are looking at a random number generator using the DDR3 memory controller.

. PROPOSED WORK

METHOD

The project is equally divided between the two members. The various building blocks of the Memory controller are as follows.

Request Queue

Memory sequencing

Arbitration or Bus status

Command Queue

Memory device

Interface or Data path

These blocks for the memory controller would be designed in Verilog HDL using VCS or Modelsim for simulation and VCS â€" Design Vision for the Synthesizable netlist. The test bench will be written in Verilog and used for simulation to test the functionality. The random number generator used as a mechanism would be written in Verilog and used for generating the random number for the entire system.

Figure 4. Block diagram of Memory controller [3].

The various modules in a Memory controller is shown in the figure 5 below. The project is divide where I am responsible for the Interface, Command generator and the Bus status queue. There is brief description of the various blocks and detailed description of the modules related to my piece of work.

Interface

DDR 3 SDRAM

Figure 5. Functional Block diagram of a memory controller design.[4]

Request Queue: The request queue is FIFO which will have the status of the requested command. The request queue will have a tag to identify the requested address and the corresponding data. The requestor queue will have the address and the command in a FIFO [3]

Memory Sequencing: The memory sequencing is a block which has the address decoder which decodes the address in various different blocks like row, bank and column. The memory sequencing involves decoding the sequencing pattern and orders the address according to the bank row and column. [3]

Arbiter: The Arbiter is used to control the order in which the request needs to be process based to various parameters like efficiency of memory, predictability, flexible, fair and fast. The arbiter is works a a controller for the various request from the processor for memory read/write. The arbiter will be controller by the Finite State Machine (FSM) which would be used for controlling the state based on the bank status and row and column activation. [3]

Command Queue: The command generator will be used to generate the command in order to access the memory location. The command queue has various commands depending to the various memories and is customized based on address. The figure 6. Shows the basic command for a address on a memory location. The command queue need to be designed based on the timing and the latency of read and write. We need to design a schedule based on the timing specification on the DDR3 datasheet obtained from JEDAC [3]

Figure 6. Example of a command queue. [3]

Memory Device: The memory device for the project we are using is a DDR3 SDRAM 512MB. We would use the memory module available on the XILINX or ALTERA for verifying the various commands and timing specification. We need to make sure that the memory controller should be compliant with the specification standard set by JEDEC. The memory has 8 banks and has row and column address allocation. DDR3 have specific RAS (Row Address Strobe) and CAS (Column Address Strobe). The DDR have read and write latency which we need to make sure while designing. [3]

Interface or Data Path: The controller needs an interface to integrate the memory and the controller. The interface is a control block and we would design it access the memory [3]

All the various modules would be developed in Verilog HDL and the testbench would be designed and developed in Verilog. The synthesizable code would be designed and a netlist would be generated in the Design Vision (VCS) tool which is a tool available in Cadence package.

SCOPE

The figure 2 . shows the functional block diagram of the entire project. The scope of the project is only designing the memory controller in order to control DDR3 SDRAM in order to satisfy all the specification of read write and refresh condition based on the various state of the memory. There are various state which would be considered in order to make successful read and write operation. The priority of the bank state would be considered. The random number generator would be a Verilog code which we would take from an assignment which would be customized for our application. The interfacing module would be designed to interface between the memory controller and DDR3 SDRAM . This would be designed in Verilog . The simulation and synthesis results would be produced in order to validate the specification.

SPECIFICATIONS

The Memory controller specs are based on the speed of the DDR3 specs defined by JEDEC. We have obtained specs which we can use for our project in order to make the design work at high speed and low power. The specs for the Memory Controller are as follows

Requirement

Specification

Memory Module

DDR3 â€" 1066

Frequency

533 Mhz

Transmit Rate

8500MB/sec

Real time frequency

266MHz

Clock Period

3.75

Table 1. Specification[7]

STATEMENT OF WORK

TASK

DELIVERABLE

MEASUREMENT METRIC

Architectural Design for memory controller

Block Diagram

Completed/Not Completed

Designing various ports of each module

Port description and functional block

Design document

Design various module

Verilog Code and simulation result

Test the modules on the specs

Integrate various module

Working code and simulation results

Effective test bench for vigorous testing

Measuring the various timing specifications

Simulation and synthesis results

Hz

Design the random number (customize)

Random number block

Verilog code

Completed/Not Completed

Design the Interface

Block diagram and verilog code

Code and design block

Connect various block

Verification/testing result

Completed/Not Complete

. CONCLUSION

The memory controller designed for DDR3 SDRAM would meet the specification as defined above. The memory controller would satisfy all the specification and the random number is generated. The outcome of this project can be used for various other applications. This memory controller can be used by industries to integrate it with the processor for high speed applications. The random number generated has high probability of randomness and low error probability. The complete designing and verification would be done in Verilog HDL. The simulation and synthesis would be done using VCS tools.

. PROPOSED SCHEDULED

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