Conventional Cmos Full Adder Computer Science Essay

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The One-bit Full-Adder is used widely in systems with operations such as counter, addition, subtraction, multiplication, division.etc. It is the basic core component of Arithmetic-Logic-Unit (ALU). Thus, the innovation and acceleration of FA means that the speed of the Central-Processor-Unit (CPU) and the speed of the whole system in general are accelerated. FA is a basic cell in the CPU and is so fundamental that changes to it are difficult to make. However, this cannot prevent researchers to try to increase the speed for FA. A standard FA is based on three kind of gates such as XOR, AND & OR gates. Tso-Kai Liu [1], Atmel [2] suggest the use of only 1 or 2 kinds of gates NAND or all NOR & NOT to avoid using XOR gate with the aim to accelerate FA and reduce the number of CMOS and layouts in use and fabrication of FA. Nevertheless, the total number of logic gates is still relatively high in their methods.

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A direction for research is towards the acceleration for FA in terms of/ with respect to CMOS. As CMOS devices approach nanometer processes [3], the size of MOS transistors is scaling down, and this increases the density and performance of ICs, resulting in large dynamic dissipations [4-5]. There are studies on Near-Threshold Computing to acceleration for FA [3][6]. In addition, another direction in the acceleration for FA is in terms of quantum. In recently published articles, researchers also experiment to speed up FA, but the concept and implementation is quite complex and the number of components remains high [7-8]. As a result, the total number of logic gates is still relatively large in previous work.

The research on developments of algorithms in the CPU represents the need to improve FA in a new direction. The knowledge of electronic and programmable devices that are widely used today enables us to build and test the algorithms of other researchers. FPGA is now widely used in many practical ways with flexible applications. Also, there are some papers focusing on speeding up the multiplexer [9-14]. This has led to the fact that improvement in FA is not old-fashionable. In addition, there are few papers on improvement of FA on FGPA, so the necessity to improve FA on FPGA [15-18] is confirmed.

Moreover, in order to create one bit FA in the traditional methods, two's component gate must be used. This makes the circuit more complex, and when there is a subtraction of n bits, there should be an addition of n XOR gates. The FPGA device is becoming increasing popular, and the acceleration of the multiplexer and improvement in FPGA allow the configuration of the LUT in FPGA that functions as a memory or a logic functions. This especially allows the formation of many small LUT's inside a big LUT. New designs have the aim to increase the speed of FA based on LUT and Multiplexer. From this, the research expands its scope to improve the FA/S and reduces the number of components so as to enable easier fabrication of FA/S.

This paper has four parts: part one is an introduction, part two provides the background of FA/S and LUT, part three refers to a workshop, and part four presents the result and conclusion.

2 Background and Related Works

2.1 One bit Full-Adder

Standard FA is based on a half-adder and its basic gates (AND, OR, XOR gates) and RLT [10][19] shown in Fig.1 and 2.

Figure 1: Full-Adder layout with basic logic gates

(1)

(2)

Figure 2: Conventional CMOS full adder was implemented with 28 CMOS

The conventional adder was implemented with 28 CMOS. In addition, we have some adders such as the Complementary Pass-transistor Logic adder (CPL), the Transmission Function full Adder (TFA) (16 CMOS), the Transmission Gate full adder (TG) (20 CMOS) [19].

Analysis worked on RTL, AND gate, OR gate are produced by NAND gate & NOT, NOR gate & NOT. AND gate, OR gate can't use direct transistors (CMOS) to make AND, OR gates because transistor's electronic properties do not allow to do this. Therefore, Atmel and many electric companies used Morgan method to change AND-OR by NAND-NAND. Atmel improved FA by using NAND instead of AND [2], and shown Fig.3.

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Figure 3: Full Adder compact layout: (a)NAND & XOR, (b) without XOR

Subtraction is executed by two's components, so we need to use one XOR gate to invert one bit and add one into carry-in [11].

(3)

Figure 4: Diagram of the Subtraction circuit

2.2 Multiplexer 2-1

A multiplexer is a device that uses the concept of a rotary switch in analog electronics to control the digital side. It is a device which, based on some input, can change the connection of its other inputs to its outputs. This part of the research only focuses on MUX 2-1 (2 inputs, 1 control and 1 output). There are some innovations for MUX2-1 to speed up and use smaller resources [10] [13-14]. Some architectures of MUX2-1are shown in Fig.5.

Figure 5: Some MUX2-1: (a) Complementary CMOS MUX2, (b) TG MUX2, (c) CPL MUX2, (d) Pseudo MUX2

2.3 Look-Up-Table (LUT) architectures and properties

Altera company improved and introduced Adaptive Logic Module (ALM) in Stratix devices. ALM has 8-inputs and 2-outputs. This ALM was introduced the first time in Stratix II family and was improved further to become more flexible Logic Elements in Stratix III family. Each ALM contains a variety of LUTs, and this helps us to implement ALM 2 LUT4-1, 2LUTs (5,3), 2LUTs (5,5), 2LUT (6,6) … Along with the development of Altera company, Xilinx company also improved LUT and implemented LUT 6-inputs 2 outputs in Virtex 4,5 family. Like Altera, this new LUT allows a variety of small LUTs inside LUT, and this allows the programmer to implement the number of inputs into dynamic LUT.

Moreover, LUT allows the programmer to use it as logic function or memory. For example, Xilinx supports two types of slice including Slice_ L: logic only and Slice_ M: Logic/ RAM/ ShiftReg. Also, the slice structure of Xilinx and Altera also includes arithmetic and carry logic. This allows us to propose a new method to execute in parallel addition/subtraction of many bits [15-18].

Figure 6: Stratix III ALM of Altera

Figure 7: Xilinx Virtex-4,5 FPGA

Figure 8: ALM Flexibility

From these structures, we propose a new FA/S that uses basic LUT, MUX method, and the reconfiguration of LUT. This design is discussed in part 3: workshop.

3 Workshop

There are two proposals in this paper. In the first proposal, LUT can work as memory or logic function [17-18], this assists to implement LUT as memory to speed up the operation of FA. In the second proposal, a new design method for FA/S is proposed and it is implemented on LUT. The designs use the method of ALM Adaptive Combinational Logic Support in which each ALM can be configured to perform combinational logic functions or logic-and-arithmetic operations.

3.1 A new logical inference for Full Adder/ Subtractor

The truth table for addition/ subtraction 2 bits with carry flag is presented as follow:

Table 1: Truth table Full-Adder/ Subtractor

Cin

x

y

Adder

Subtractor

Sum

Cout

Sub

Cout

0

0

0

0

0

0

0

0

0

1

1

0

1

1

0

1

0

1

0

1

0

0

1

1

0

1

0

1

1

0

0

1

0

1

1

1

0

1

0

1

0

1

1

1

0

0

1

0

0

1

1

1

1

1

1

1

From truth table 1, a conclusion reached regarding output values: Sum/ Sub values and Carry-out flags. This conclusion derives from the idea of the operating current (electronic), by switching on/off the Current to obtain the expected logic value:

(4)

(5)

In addition, another conclusion reached is that the subtracted value output is equal to the addition value output for 1 bit. However, there is a in carry-out flag, thus a new inference built for carry-out flag:

(6)

Two circuits are built for sum and carry-out based on MUX2-1. Those use MUX as a switch which is controlled to allow expected values to pass through.

3.2 Design circuits for Full Adder/ Subtractor

The circuit for Sum value: A circuit is built through a control of values including input x or input y that are shown in Table 2 and Fig.8.

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Table 2: Truth table Sum/Sub value

Controlled by Cin & y

Controlled by Cin & x

Cin

y

Sum

Cin

x

Sum

0

0

0

0

0

1

0

1

1

0

1

0

1

1

1

1

Figure 9: Circuit for Sum/ Sub value: (a) Controlled by & y ; (b) Controlled by & x

The circuit for Carry-out flag circuit: By observing the truth table of addition/ subtraction, 2 bits and new equations are realized, and it is learnt that the Carry-out flag relies on the control of input x and carry-in to find the best solution. Similarly, two circuits for Carry-out of Addition and Carry-out of subtraction and they are illustrated in table 3 and Fig.9.

Table 3: Truth table of Cout value

Addition

Subtraction

Cin

x

Cout

Cin

x

Cout

0

0

0

0

0

0

1

0

1

0

1

0

1

0

1

1

1

1

1

1

Figure 10: Carry-out flag: (a) Addition, (b) Subtraction

3.3 Implementing the Look-up table (LUT)

Two LUT3-1's are used to establish the FA. LUT3-1 is a basis LUT inside the slice [10][13]. Because the sum value and carry-out flag above can be executed at the same time, two basic LUT3-1's used: one for Sum circuit and one for Carry-out circuit.

From the observation the two truth tables of addition and subtraction as well as two circuits of Carry-out flag for addition and subtraction, it is learnt that it is possible combine them to have FA/S with control=0:add and =1:sub following as Fig.10.

Figure 11: Diagram with a control pin

Moreover, the final circuit for FA/S is obtained by using one LUT (6-input, 2-output) that is divided into 2 small LUT's, one for Sum/Sub and one for Carry-out flag .When Carry-out flag is equal to 1, addition shows 'overload' and subtraction shows as 'borrow'. As a result of this, Sum/Sub and Carry-out flag can run at the same time as shown in Fig.12.

Figure 12: Diagram FA/S with 2 small LUTs in a big LUT

The new LUT's of the Xilinx company and the Altera company now allow the designers to use one LUT6-2 of Xilinx or one ALM of Altera to execute FA/S one bit while remaining an input line which can be used to interconnect with other functions.

4 Conclusion

New designed circuits are implemented, simulations and tested the results with ISE software from Xilinx, Quatus software from Altera and electrical softwares. ISE software chose as the standard to synthesize the measurements and comparison of results. This standard FA/S which is formed from logic gates (XOR, AND and OR) uses the addition function of FPGA and our design. Speed and saving capacity of FA/S on FPGA considered, so FA/S implemented on many kinds of FPGA to find optimal values that compared with other kinds of FPGA chips.

In the first experiment, the standard FA and new designs implemented to measure and record results. The result of this experiment is shown in table 4.

Table 4: Comparison among three implementations of one bit full-adder

Spartan 3E: XC3S500E

Virtex 4: XC4VSX35

Virtex 5: XC5VFX100T

Standard

FA

FPGA

New

FA

Standard

FA

FPGA

New

FA

Standard

FA

FPGA

New

FA

Number of Slices

1

4

1

1

4

1

2

2

2

Number of Slice Flip Flop

-

7

2

-

7

2

2

7

2

Number of 4 input LUTs

2

2

2

2

2

2

-

-

-

Number of IOs

6

6

6

6

6

6

6

6

6

Number of bonded IOBs

6

6

6

6

6

6

6

6

6

Number of GCLKs

-

1

1

-

1

1

-

1

1

Levels of Logic

3

2

2

3

2

2

3

2

2

Timing constraint (ns)

5.776

4.040

4.040

5.600

4.221

4.221

3.875

2.826

2.826

- Logic (ns)

4.887

3.683

3.683

4.634

3.908

3.908

2.924

2.540

2.540

- Route (ns)

0.889

0.357

0.357

0.966

0.313

0.313

0.951

0.286

0.286

In the second experiment, the standard FA/S and new designs implemented to measure and record results. With the same idea as in the first experiment, results are shown in table 5.

Table 5: Comparison between two implementations of the full-adder/subtractor

Spartan 3E: XC3S500E

Virtex 4: XC4VSX35

Virtex 5: XC5VFX100T

Standard

FA/S

New

MUX

New

Memory

Standard

FA/S

New

MUX

New

Memory

Standard

FA/S

New

MUX

New

Memory

Num of Slices

2

1

1

2

1

1

2

1

1

Num of Slice Flip Flops

-

2

2

-

2

2

2

2

2

Num of 4 input LUTs

3

2

2

3

2

2

-

-

-

Num of IOs

7

7

7

7

7

7

7

7

7

Num of bonded IOBs

7

7

7

7

7

7

7

7

7

Num of GCLKs

-

1

1

-

1

1

-

1

1

Timing (ns)

6.775

4.114

4.040

6.138

4.317

4.221

4.032

3.040

2.826

- Logic (ns)

5.499

3.757

3.683

4.800

4.004

3.908

2.924

2.754

2.540

- Route (ns)

1.276

0.357

0.357

1.338

0.313

0.313

1.108

0.286

0.286

From the results of the experiments obtained, a conclusion come to that the standard FA/S and new designs used the same quantity of source on FPGA but the rates are different. With the new design, the speed is faster than the standard FA/S by 20% to 30% depending on different kinds of FPGA. If the implementation with the addition clock pulse for standard FA/S to save energy for FPGA, this obtain a better result. The new design occupies only ½ compared with the standard FA/S and the speed increases from 28% to 40%.

Like the ideas initially suggested, two aims proposed for this paper. The first purpose is to optimize the FA/S in order to increase the speed and use less source on FPGA and this idea has been achieved. The second purpose is to develop new logical inference for FA/S to enable a production with fewer gates and layouts. As result, a new design based on multiplexer, and those designs only have two kinds of components: NOT and multiplexer. So the implementation is more easily on FPGA chip and the total masks to fabricate ASIC with integrating existing FA/S will require fewer transistors.

Working on computer calculations, we learn that in order to speed up the calculation, one important thing is to alter the core component which is FA. This is a very fundamental cell, therefore, it is quite challenging to make changes to this component. However, we are finally successful in changing it and we hope that the idea and the result from this research will be recognized and can used as a resource for further development of n bit addition.

Acknowledge

I wish to convey my warmest appreciation and deep gratitude to my supervisor for her valuable assistance over the period of carrying out the research as well as the staff's support in the laboratory and College of Information Science and Engineering.