Compact Canbus Analyser Computer Science Essay

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So from the topology we can say that the CAN differential signal is connected to CAN transceiver which in turn is connected to CAN controller (MCP2515) with Tx and Rx pins accordingly, one for transmitting and one for receiving. These two can be placed in one board which must be connected to MC68HC11F1 development board. This connection is done using SPI (serial protocol interface) between CAN controller (MCP2515) and 68hc11 (Motorola microcontroller).Thus the development (MC68HC11F1) board is connected to a laptop using RS232 interface.

CANH and CANL is a "differential" pair. CAN actually needs 3 lines, CAN_L, CAN_H and ground (not necessary when the nodes or isolated from dc and ac). It is a differential line, where the signal is represented by differences between CAN_L and CAN_H. If the difference is positive and larger than a certain minimum voltage it is a "1" and if the difference is negative it is a "0". It is done in this way because then we can have very long cable lengths with a twisted pair type of cable. If a disturbance is affecting the cable, it is affecting both wires in the same way, which then effectively is cancelled out since it isn't differential. Also the line is said to be balanced which means that each node (or perhaps only the end nodes in a large network) are terminated with the same impedance as the cable (normally around 120 ohms) which cancels out reflections that would otherwise be a big problem for higher communication speeds.

CAN Data Extended Frame =

The CAN 2.0b standard specifies the format of all packets and the encoding scheme used on the CAN bus.  The CAN bus can assume one of two states, dominant (logical low) or recessive (logical high).  If two devices attempt to drive the CAN bus simultaneously, one with a dominant bit and the other with a recessive bit, the bus will assume the dominant state.  All devices read the value of the bus while transmitting.  If a device transmits a recessive bit but reads a dominant bit, it knows that another device is transmitting and will wait until that device is finished to re-attempt its transmission.  This system allows easy connection of multiple devices to the bus without any additional collision detection. This system uses only Standard Data Frames.  Each frame consists of a single dominant start bit, a 32-bit arbitration field used to establish message priority and identification, a 6-bit control field which includes the data length code, a data field ranging from 0 to 8 bytes, a 16-bit cyclic redundancy check (CRC) field for error detection, and a 7-bit end-of-frame field.  In this standard, higher priority is given to frames with lower values of the arbitration field (dominant bits in the more significant positions).So with this standard data frame we could be dealing with 128-bits in total.

Extended frame format =

Field name

No. of Bits

Purpose

Start-of-frame

1

Denotes the start of frame transmission

Identifier A

11

First part of the (unique) identifier for the data

Substitute remote request (SRR)

1

Must be recessive (1)Optional

Identifier extension bit (IDE)

1

Must be recessive (1)Optional

Identifier B

18

Second part of the (unique) identifier for the data

Remote transmission request (RTR)

1

Must be dominant (0)

Reserved bits (r0, r1)

2

Reserved bits (it must be set dominant (0), but accepted as either dominant or recessive)

Data length code (DLC)*

4

Number of bytes of data (0-8 bytes)

Data field

0-8 bytes

Data to be transmitted (length dictated by DLC field)

CRC

15

Cyclic redundancy check

CRC delimiter

1

Must be recessive (1)

ACK slot

1

Transmitter sends recessive (1) and any receiver can assert a dominant (0)

ACK delimiter

1

Must be recessive (1)

End-of-frame (EOF)

7

Must be recessive (1)

The two identifier fields (A & B) combined form a 29-bit identifier

Physical CAN connection according to ISO 11898-2 =

Schematics for CAN Transceiver and Controller:

RS232 Interface Schematic:

Power Description:

MCP2551 Transceiver:

1) Features:

Supports 1 Mb/s operation

Implements ISO-11898 standard physical layer requirements

Suitable for 12V and 24V systems

Externally-controlled slope for reduced RFI emissions

Detection of ground fault (permanent dominant) on TXD input

Power-on reset and voltage brown-out protection

An unpowered node or brown-out event will not disturb the CAN bus

Low current standby operation

Protection against damage due to short-circuit conditions (positive or negative battery voltage)

Protection against high-voltage transients

Automatic thermal shutdown protection

Up to 112 nodes can be connected

High noise immunity due to differential bus implementation

Temperature ranges: -Industrial (I): -40°C to +85°C -Extended (E): -40°C to +125°C

2) MAXIMUM NUMBER OF NODES:

The MCP2551 CAN outputs will drive a minimum load of 45Ω, allowing a maximum of 112 nodes to be connected (given a minimum differential input resistance of 20 kΩ and a nominal termination resistor value of 120Ω).

3) Pin Descriptions:

1) TRANSMITTER DATA INPUT (TXD):

TXD is a TTL-compatible input pin. The data on this pin is driven out on the CANH and CANL differential output pins. It is usually connected to the transmitter data output of the CAN controller device. When TXD is low, CANH and CANL are in the dominant state. When TXD is high, CANH and CANL are in the recessive state, provided that another CAN node is not driving the CAN bus with a dominant state. TXD has an internal pull-up resistor (nominal 25 kΩ to VDD).

2) GROUND SUPPLY (VSS): Ground supply pin.

3) SUPPLY VOLTAGE (VDD): Positive supply voltage pin.

4) RECEIVER DATA OUTPUT (RXD):

RXD is a CMOS-compatible output that drives high or low depending on the differential signals on the CANH and CANL pins and is usually connected to the receiver data input of the CAN controller device. RXD is high when the CAN bus is recessive and low in the dominant state.

5) REFERENCE VOLTAGE (VREF): Reference Voltage Output (Defined as VDD/2).

6) CAN LOW (CANL):

The CANL output drives the low side of the CAN differential bus. This pin is also tied internally to the receive input comparator.

7) CAN HIGH (CANH):

The CANH output drives the high-side of the CAN differential bus. This pin is also tied internally to the receive input comparator.

8) SLOPE RESISTOR INPUT (RS):

The RS pin is used to select High-speed, Slope-control or Standby modes via an external biasing resistor.

4) Block diagram:

5) Operating Modes:

The RS pin allows three modes of operation to be selected:

High-Speed

Slope-Control

Standby

When in High-speed or Slope-control mode, the drivers for the CANH and CANL signals are internally regu­lated to provide controlled symmetry in order to mini­mize EMI emissions. Additionally, the slope of the signal transitions on CANH and CANL can be controlled with a resistor connected from pin 8 (RS) to ground, with the slope proportional to the current output at RS, further reducing EMI emissions.

HIGH-SPEED:

High-speed mode is selected by connecting the RS pin to VSS. In this mode, the transmitter output drivers have fast output rise and fall times to support high-speed CAN bus rates.

SLOPE-CONTROL:

Slope-control mode further reduces EMI by limiting the rise and fall times of CANH and CANL. The slope, or slew rate (SR), is controlled by connecting an external resistor (REXT) between RS and VOL (usually ground). The slope is proportional to the current output at the RS pin. Since the current is primarily determined by the slope-control resistance value REXT, a certain slew rate is achieved by applying a respective resistance. Figure 1-1 illustrates typical slew rate values as a function of the slope-control resistance value.

STANDBY MODE:

The device may be placed in standby or "SLEEP" mode by applying a high-level to RS. In SLEEP mode, the transmitter is switched off and the receiver operates at a lower current. The receive pin on the controller side (RXD) is still functional but will operate at a slower rate. The attached microcontroller can monitor RXD for CAN bus activity and place the transceiver into normal operation via the RS pin (at higher bus rates, the first CAN message may be lost).

Test circuit for MCP2551:

CAN Controller (MCP2515):

1) Description:

Microchip Technology's MCP2515 is a stand-alone Controller Area Network (CAN) controller that imple­ments the CAN specification, version 2.0B. It is capable of transmitting and receiving both standard and extended data and remote frames. The MCP2515 has two acceptance masks and six acceptance filters that are used to filter out unwanted messages, thereby reducing the host MCUs overhead. The MCP2515 interfaces with microcontrollers (MCUs) via an industry standard Serial Peripheral Interface (SPI).

2) Features:

Implements CAN V2.0B at 1 Mb/s: -0 - 8 byte lengths in the data field -Standard and extended data and remote frames.

Receive buffers, masks and filters: -Two receive buffers with prioritized message storage -Six 29-bit filters -Two 29-bit masks.

Data byte filtering on the first two data bytes (applies to standard data frames).

Three transmit buffers with prioritization and abort features.

High-speed SPIâ„¢ Interface (10 MHz): -SPI modes 0,0 and 1,1.

One-shot mode ensures message transmission is attempted only one time.

Clock out pin with programmable prescaler: Can be used as a clock source for other device(s).

Start-of-Frame (SOF) signal is available for monitoring the SOF signal: Can be used for time-slot-based protocols and/or bus diagnostics to detect early bus degradation.

Interrupt output pin with selectable enables.

Buffer Full output pins configurable as: -Interrupt output for each receive buffer -General purpose output.

Request-to-Send (RTS) input pins individually configurable as: Control pins to request transmission for each transmit buffer -General purpose inputs.

Low-power CMOS technology: -Operates from 2.7V - 5.5V -5 mA active current (typical) -1 µA standby current (typical) (Sleep mode).

Temperature ranges supported: -Industrial (I): -40°C to +85°C -Extended (E): -40°C to +125°C.

3) PIN DISCRIPTION:

Name

PDIP/SOIC Pin #

TSSOP Pin #

I/O/P Type

Description

Alternate Pin Function

TXCAN

1

1

O

Transmit output pin to CAN bus

-

RXCAN

2

2

I

Receive input pin from CAN bus

-

CLKOUT

3

3

O

Clock output pin with programmable prescaler

Start-of-Frame signal

TX0RTS

4

4

I

Transmit buffer TXB0 request-to-send. 100 kΩ internal pull-up to VDD

General purpose digital input. 100 kΩ internal pull-up to VDD

TX1RTS

5

5

I

Transmit buffer TXB1 request-to-send. 100 kΩ internal pull-up to VDD

General purpose digital input. 100 kΩ internal pull-up to VDD

TX2RTS

6

7

I

Transmit buffer TXB2 request-to-send. 100 kΩ internal pull-up to VDD

General purpose digital input. 100 kΩ internal pull-up to VDD

OSC2

7

8

O

Oscillator output

-

OSC1

8

9

I

Oscillator input

External clock input

VSS

9

10

P

Ground reference for logic and I/O pins

-

RX1BF

10

11

O

Receive buffer RXB1 interrupt pin or general purpose digital output

General purpose digital output

RX0BF

11

12

O

Receive buffer RXB0 interrupt pin or general purpose digital output

General purpose digital output

INT

12

13

O

Interrupt output pin

-

SCK

13

14

I

Clock input pin for SPIâ„¢ interface

-

SI

14

16

I

Data input pin for SPI interface

-

SO

15

17

O

Data output pin for SPI interface

-

CS

16

18

I

Chip select input pin for SPI interface

-

RESET

17

19

I

Active low device reset input

-

VDD

18

20

P

Positive supply for logic and I/O pins

-

NC

-

6,15

-

No internal connection

Note: Type Identification: I = Input; O = Output; P = Power

4) Transmit/Receive Buffers/Masks/Filters:

The MCP2515 has three transmit and two receive buffers, two acceptance masks (one for each receive buffer) and a total of six acceptance filters. Figure below shows a block diagram of these buffers and their connection to the protocol engine.

5) MESSAGE RECEPTION:

5.1 Receive Message Buffering:

The MCP2515 includes two full receive buffers with multiple acceptance filters for each. There is also a separate Message Assembly Buffer (MAB) that acts as third receive buffer

5.1.1 MESSAGE ASSEMBLY BUFFER:

Of the three receive buffers; the MAB is always committed to receiving the next message from the bus. The MAB assembles all messages received. These messages will be transferred to the RXBn only if the acceptance filter criteria are met.

5.1.2 RXB0 AND RXB1:

The remaining two receive buffers, called RXB0 and RXB1, can receive a complete message from the protocol engine via the MAB. The MCU can access one buffer, while the other buffer is available for message reception, or for holding a previously received message.

[Note: The entire contents of the MAB is moved into the receive buffer once a message is accepted. This means that, regardless of the type of identifier (standard or extended) and the number of data bytes received, the entire receive buffer is overwritten with the MAB contents. Therefore, the contents of all registers in the buffer must be assumed to have been modified when any message is received.]

5.1.3 RECEIVE FLAGS/INTERRUPTS:

When a message is moved into either of the receive buffers, the appropriate CANINTF.RXnIF bit is set. This bit must be cleared by the MCU in order to allow a new message to be received into the buffer. This bit provides a positive lockout to ensure that the MCU has finished with the message before the MCP2515 attempts to load a new message into the receive buffer. If the CANINTE.RXnIE bit is set, an interrupt will be generated on the INT pin to indicate that a valid message has been received.

5.2 Receive Priority:

RXB0, the higher priority buffer, has one mask and two message acceptance filters associated with it. The received message is applied to the mask and filters for RXB0 first. RXB1 is the lower priority buffer, with one mask and four acceptance filters associated with it. In addition to the message being applied to the RB0 mask and filters first, the lower number of acceptance filters makes the match on RXB0 more restrictive and implies a higher priority for that buffer.

5.2.1 ROLLOVER:

Additionally, the RXB0CTRL register can be configured such that, if RXB0 contains a valid message and another valid message is received, an overflow error will not occur and the new message will be moved into RXB1, regardless of the acceptance criteria of RXB1.

5.2.2 RXM BITS:

The RXBnCTRL.RXM bits set special receive modes. Normally, these bits are cleared to 00 to enable reception of all valid messages as determined by the appropriate acceptance filters. In this case, the determination of whether or not to receive standard or extended messages is determined by the RFXnSIDL.EXIDE bit in the acceptance filter register. If the RXBnCTRL.RXM bits are set to 01 or 10, the receiver will only accept messages with standard or extended identifiers, respectively. If an acceptance filter has the RFXnSIDL.EXIDE bit set such that it does not correspond with the RXBnCTRL.RXM mode, that acceptance filter is rendered useless. These two modes of RXBnCTRL.RXM bits can be used in systems where it is known that only standard or extended messages will be on the bus. If the RXBnCTRL.RXM bits are set to 11, the buffer will receive all messages, regardless of the values of the acceptance filters. Also, if a message has an error before the EOF, that portion of the message assembled in the MAB before the error frame will be loaded into the buffer. This mode has some value in debugging a CAN system and would not be used in an actual system environment.

6) RECEIVE FLOWCHART:

7) INTERRUPTS:

The MCP2515 has eight sources of interrupts. The CANINTE register contains the individual interrupt enable bits for each interrupt source. The CANINTF register contains the corresponding interrupt flag bit for each interrupt source. When an interrupt occurs, the INT pin is driven low by the MCP2515 and will remain low until the interrupt is cleared by the MCU. An interrupt cannot be cleared if the respective condition still prevails. It is recommended that the bit modify command be used to reset flag bits in the CANINTF register rather than normal write operations. This is done to prevent unintentionally changing a flag that changes during the write command, potentially causing an interrupt to be missed. It should be noted that the CANINTF flags are read/write and an interrupt can be generated by the MCU setting any of these bits, provided the associated CANINTE bit is also set.

7.1) Receive Interrupt:

When the receive interrupt is enabled (CANINTE.RXnIE = 1), an interrupt will be generated on the INT pin once a message has been successfully received and loaded into the associated receive buffer. This interrupt is activated immediately after receiving the EOF field. The CANINTF.RXnIF bit will be set to indicate the source of the interrupt. The interrupt is cleared by clearing the RXnIF bit.

8) OSCILLATOR:

The MCP2515 is designed to be operated with a crystal or ceramic resonator connected to the OSC1 and OSC2 pins. The MCP2515 oscillator design requires the use of a parallel cut crystal. Use of a series cut crystal may give a frequency out of the crystal manufacturer's specifications. The MCP2515 may also be driven by an external clock source connected to the OSC1 pin and OSC2 left open.

8.1) Oscillator Start-up Timer:

The MCP2515 utilizes an Oscillator start-up Timer (OST) that holds the MCP2515 in reset to ensure that the oscillator has stabilized before the internal state machine begins to operate. The OST maintains reset for the first 128 OSC1 clock cycles after power-up or a wake-up from Sleep mode occurs. It should be noted that no SPI protocol operations should be attempted until after the OST has expired.

9) RESET:

The MCP2515 differentiates between two resets:

Hardware Reset - Low on RESET pin.

SPI Reset - Reset via SPI command.

Both of these resets are functionally equivalent. It is important to provide one of these two resets after power-up to ensure that the logic and registers are in their default state. A hardware reset can be achieved automatically by placing an RC on the RESET pin. The values must be such that the device is held in reset for a minimum of 2 μs after VDD reaches operating voltage, as indicated in the electrical specification (tRL).

10) MODES OF OPERATION:

The MCP2515 has five modes of operation. These modes are:

Configuration mode.

Normal mode.

Sleep mode.

Listen-only mode.

Loopback mode.

The operational mode is selected via the CANCTRL. REQOP bits. When changing modes, the mode will not actually change until all pending message transmissions are complete. The requested mode must be verified by reading the CANSTAT.OPMODE bits.

10.1) Listen-only Mode:

Listen-only mode provides a means for the MCP2515 to receive all messages (including messages with errors) by configuring the RXBnCTRL.RXM<1:0> bits. This mode can be used for bus monitor applications or for detecting the baud rate in 'hot plugging' situations. For auto-baud detection, it is necessary that there are at least two other nodes that are communicating with each other. The baud rate can be detected empirically by testing different values until valid messages are received. Listen-only mode is a silent mode, meaning no messages will be transmitted while in this mode (including error flags or acknowledge signals). The filters and masks can be used to allow only particular messages to be loaded into the receive registers, or the masks can be set to all zeros to allow a message with any identifier to pass. The error counters are reset and deactivated in this state. The Listen-only mode is activated by setting the mode request bits in the CANCTRL register.

11) SPI INTERFACE:

11.1) Overview:

The MCP2515 is designed to interface directly with the Serial Peripheral Interface (SPI) port available on many microcontrollers and supports Mode 0, 0 and Mode 1, 1.Commands and data are sent to the device via the SI pin, with data being clocked in on the rising edge of SCK. Data is driven out by the MCP2515 (on the SO line) on the falling edge of SCK. The CS pin must be held low while any operation is performed.

[Note: The MCP2515 expects the first byte after lowering CS to be the instruction/command byte. This implies that CS must be raised and then lowered again to invoke another command.]

11.2) Reset Instruction:

The Reset instruction can be used to re-initialize the internal registers of the MCP2515 and set Configuration mode. This command provides the same functionality, via the SPI interface, as the RESET pin. The Reset instruction is a single-byte instruction that requires selecting the device by pulling CS low, sending the instruction byte and then raising CS. It is highly recommended that the reset command be sent (or the RESET pin be lowered) as part of the power-on initialization sequence.

11.3) Read Instruction:

The Read instruction is started by lowering the CS pin. The Read instruction is then sent to the MCP2515 followed by the 8-bit address (A7 through A0). Next, the data stored in the register at the selected address will be shifted out on the SO pin. The internal address pointer is automatically incremented to the next address once each byte of data is shifted out. Therefore, it is possible to read the next consecutive register address by continuing to provide clock pulses. Any number of consecutive register locations can be read sequentially using this method. The read operation is terminated by raising the CS pin.

11.4) Read RX Buffer Instruction:

The Read RX Buffer instruction provides a means to quickly address a receive buffer for reading. This instruction reduces the SPI overhead by one byte, the address byte. The command byte actually has four possible values that determine the address pointer location. Once the command byte is sent, the controller clocks out the data at the address location the same as the Read instruction .This instruction further reduces the SPI overhead by automatically clearing the associated receive flag (CANINTF.RXnIF) when CS is raised at the end of the command.

11.5) Write Instruction:

The Write instruction is started by lowering the CS pin. The Write instruction is then sent to the MCP2515 followed by the address and at least one byte of data. It is possible to write to sequential registers by continuing to clock in data bytes, as long as CS is held low. Data will actually be written to the register on the rising edge of the SCK line for the D0 bit. If the CS line is brought high before eight bits are loaded, the write will be aborted for that data byte and previous bytes in the command will have been written.

11.6) Read Status Instruction:

The Read Status instruction allows single instruction access to some of the often used status bits for message reception and transmission. The MCP2515 is selected by lowering the CS pin and the read status command byte is sent to the MCP2515. Once the command byte is sent, the MCP2515 will return eight bits of data that contain the status. If additional clocks are sent after the first eight bits are transmitted, the MCP2515 will continue to output the status bits as long as the CS pin is held low and clocks are provided on SCK. Each status bit returned in this command may also be read by using the standard read command with the appropriate register address.

11.7) RX Status Instruction:

The RX Status instruction is used to quickly determine which filter matched the message and message type (standard, extended, remote). After the command byte is sent, the controller will return 8 bits of data that contain the status data. If more clocks are sent after the 8 bits are transmitted, the controller will continue to output the same status bits as long as the CS pin stays low and clocks are provided.

11.8) Bit Modify Instruction:

The Bit Modify instruction provides a means for setting or clearing individual bits in specific status and control registers. This command is not available for all registers.

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