Charge Recycling Differential Dual Rail Computer Science Essay

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Sushant Sakhalkar, Member, IEEE, Sushilkumar Pareek and Shahab Ardalan, Member, IEEEAbstract- Side channel attacks are a technique used by the hackers for obtaining the crucial information by Differential Power Analysis (DPA). We are developing a charge recycling differential dual rail domino logic for providing protection against the side channel attacks by reducing the current peaks .We are implementing a NAND & XOR gate logic using the charge recycling differential dual rail domino logic circuit to calculate the Maximum DPA and Area of the circuit. We are going to compare the results with the Sense Amplifier Based Logic (SABL), Enhanced Current Balanced Logic (ECBL), Dynamic Current Mode Logic (DyCML) and a CMOS Circuit.

Index Terms-Crdomino, Dpa, Sabl, Side Channel Attacks

INTRODUCTION

Ambient Intelligent Systems

Today there has been a rapid innovation in the field of electronics which has revolutionized the whole electronic market. These sophisticated electronic systems help to ease down the daily routine work of the people in an easy way. It reduces the amount of time required for completing the task and also the effort in doing that. An 'Ambient Intelligent Systems' is an electronic environment which is sensitive to the presence of people around it [4]. The response given by the system is also dependent on the number of people and things in its vicinity. A lot of Embedded Systems, sensors and wireless modules are employed to realize the functionality of ambient intelligent systems. Ex: 1) You can monitor the appliances, security of your home remotely from an application in your smartphone. (2)When you will reach home the face recognition system will recognize your face and will automatically open the door for you. (3) The smart lightning system in home will turn on the lights only in the perimeter where the person is present.

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Such systems employ a lot of sensors like temperature sensors, IR sensors, and pressure sensors for achieving the desired response. The lifetime of the sensors is very important in order for proper functioning of the system. Now the attacker can attack such system. Thus they can hack into the systems at the physical level. The attacker will launch such an attack which will prevent the sensor node from entering into its power conserving mode. Thus the battery of the sensor nodes will get drained. The node will not last till the expected time of operation. This will lead to malfunctioning of the system. Such an attack is very critical for the entire network on which the system is based. One of the techniques for launching the attack is 'Side Channel Attack' [5].

Side Channel Attacks

Side Channel Attacks is an attack based on the method based on side channel information [5]. Previously the attacker used to decode the cipher text based on some de-encryption based method. However today's encoding systems have multiple inputs and multiple outputs. They utilize these multiple inputs so that any required output can be produced by doing the permutations and combinations of the inputs.

The flow of the electrons will consume some power. It will also give rise to some electromagnetic radiations. Such variations are easily detectable externally. Thus the side channel information gives much important information such as time consumed to perform the required operation, the power consumed to satisfy the given logic. The attacker needs to have some basic technical knowledge of the architecture in order to know the exact working of the system. The attacker exploits such useful information from the system and along with some crypto analytical techniques he may be able to launch an attack on the nodes and degrade their working. If the internal mechanism and flow of any system is known to the attacker then he has the full liberty of bringing the entire node and the required system down. There are many different methods of 'Side Channel Attacks'. One of the most commonly used and well-known method is 'Differential Power Analysis' (DPA) [1].

Differential Power Analysis

This is one of the side channel attack in which power consumed by the circuit is closely analyzed. Every circuit consumes a specific amount of power during the entire operation of the circuit. The differential power analysis is divided into two parts 1) Data Collection: - This involves closely observing and noting the power that is consumed by the circuit. 2) Data Analysis: - Depending upon the power consumed by the circuit and by formulating some data dependent calculations we can arrive at the decoding the more there will be variation in the power, the more will be the probability of the circuit being hacked and malfunctioned circuit. Thus the entire operation of the circuit can be known from data analysis [4].After knowing the operation of the circuit it is possible to hack into the circuit by employing some crypto-analytic techniques. In every clock cycle depending on the inputs of the circuit the power consumed by the circuit will vary .The more there will be variation in the power, the more will be the probability of the circuit being hacked and malfunctioned.

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The later part of the report deals with section (II) A description of SABL logic, (III) Differential dual rail domino logic details, (IV) An introduction to charge recycling differential dual rail domino logic, (V) SABL and CR-DOMINO logic styles for implementing Nand & Xor gates, (VI) Experimental analysis of SABL & CR-DOMINO logics in terms of peak supply current and area .Finally a conclusion to end the report.

SABL

SABL (Sense Amplifier Based Logic) was invented for its use against the side channel attacks by DPA [2]. The main idea of the logic is to dissipate a constant amount of power throughout the working of the circuit .Thus hiding the signal activity from the hacker by leaving no information for the differential power analysis. In a normal logic whenever there is a switching at the input side, there's some static power dissipation for a very small amount of time. This gives rise to a strong peak in the supply current which can be easily detected by the hacker performing the differential power analysis. The main advantage of the SABL circuit is that it reduces the peak supply current thus making it difficult to perform the differential power analysis.

SABL is a logic style that has a constant charge in every transition cycle. It has a fixed capacitor load charge at every change at the input end i.e. it charges and discharges the capacitor load with a fixed amount of charge [1]. Now SABL is a dynamic and differential logic style. It has a precharge and an evaluation phase. During the precharge phase, both the output nodes are charged to the voltage VDD. Two precharge pmos's connected to the clock are used for this purpose. During the evaluation phase, one of the two outputs is discharged and the voltage of the other output node is held at VDD. SABL is a differential logic style as it has both the normal and the inverted outputs. Being a dynamic logic style SABL logic switches for only one event per cycle. Because of this, either output node 1 discharges or output node 2 discharges to ground. Thus there's constant power consumption by the circuit independent of the input to the circuit [1].

Fig1: SABL Inverter

Differential (Dual Rail) Domino Logic

The 'Differential (Dual Rail) Domino Logic' is a differential and dynamic logic style. The domino logic gives only non-complementary outputs. Therefore 'Differential (Dual Rail) Domino Logic' was designed to overcome this shortcoming [6]. It is a differential logic style since both, the complementary and non-complementary values of the input are given to the logic and we get complementary and non-complementary values of the output. It is also a dynamic logic style since it has alternate precharge and evaluation stage. Here this logic style uses two precharged Pmos loads for the precharge phase. The evaluation network consists of the logic which provides us with both complementary and non-complementary outputs.

In the evaluation phase, depending upon the state of the inputs one of the leg of the output will discharge to ground. So, the corresponding node voltage will be zero and it will turn on the keeper of the opposite output leg. This keeper will hold the output value at this node to high state. Likewise when the output leg which has output high, will discharge to ground it will turn on the keeper for opposite rail and thus that value of output will be held to a high state .Thus as one of the rail of the circuit discharges the opposite rail charges and vice versa. This guarantees that the capacitor will discharge a fixed amount of charge during every clock signal. Thus, it will make the output level independent of the signal activity. As the output level becomes independent of the signal activity, thus the variation in the power consumption will be very less. Therefore it will give very minimum chance for the attacker to analyze the variation in power consumption of the circuit. Owing to this advantage of this particular logic, there is a very less probability of the circuit being attacked and being malfunctioned.

Fig2: Differential (Dual Rail) Domino Nand

IV. CHARGE RECYCLING (CR) DIFFERENTIAL DUAL RAIL DOMINO

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This circuit is a modified version of 'Differential (Dual Rail) Domino Logic' style. In this logic style we have implemented only a single precharge Pmos load instead of two precharge Pmos load. This helps to reduce the load on the clock line. It will also be easier to drive the clock. . Here the circuit style is differential because we give both the complementary as well as non-complementary value of inputs. It also provides us with complementary and non-complementary outputs. During the precharge phase the Pmos will conduct and it will short both the output rails. So, there will be a transfer of current from rail which has higher voltage to the rail which is at lower voltage. The node will be charged to voltage of VDD- VTP . So in this case the circuit will be faster since it discharges the capacitor from VDD-VTP and not from VDD. This logic uses the concept of charge recycling. The charge stored during the precharge phase will be used to charge the node during the evaluation stage. So there will be less power drawn from the power supply. Hence the power dissipation will be less. We have connected the two static inverters at both the end in order to improve the noise immunity of the circuit. Also, by connecting static inverters, we are separating the output capacitors and internal capacitance [5].

In the evaluation phase, depending upon the state of the inputs one of the leg of the output will discharge to ground. So, the corresponding node voltage will be zero and it will turn on the keeper of the opposite output leg. This keeper will hold the output value at this node to high state. Likewise when the output leg which has output high, will discharge to ground it will turn on the keeper for opposite rail and thus that value of output will be held to a high state .Thus as one of the rail of the circuit discharges the opposite rail charges and vice versa. This guarantees that the capacitor will discharge a fixed amount of charge during every clock signal. Thus, it will make the output level independent of the signal activity. So, as the peak current reduces there will be a less probability for the hacker to exploit the power dissipated by the circuit. The range of the variation in the power consumed will also reduce drastically. Thus it will prove to be strong against the DPA.

Fig3: CR-Differential Domino Nand

NAND & XOR

The CR-DOMINO and SABL Nand logic gates are depicted in Fig.4 and Fig.5 respectively. CR-DOMINO XOR and SABL XOR are depicted in Fig.6 and Fig.7 respectively. Both the SABL & CR-DOMINO are dynamic logic circuits. But in the CR-DOMINO logic, the two precharge pmos's are replaced by a single pmos in the center.

Fig4: CR-Domino NAND

Fig5: SABL NAND

Fig6: CR-Domino XOR

Fig:7 SABL XOR

The CR-DOMINO Xor and Nand voltage waveforms are represented in Fig.8 and Fig.9 respectively. Both the circuits are implemented in a standard 45nm technology. The vertical markers correspond to four different input combinations and it can be seen from the waveforms that CR-DOMINO output satisfies the Nand and Xor logic. The circuit for Nand and Xor logic is simulated at a clock speed of 1GHz and it experimental analysis has proven that it can also be operated at a clock frequency of 10 GHz.

Fig7: SABL XOR

Fig8: Output of CR-DOMINO NAND

Fig9: Output of CR-DOMINO XOR

VI. ANALYSIS

The SABL & CR-DOMINO Nand and Xor supply current waveform is depicted in Fig.7 and Fig.8 respectively. It can be seen from the output waveforms that SABL Nand logic current is almost twice the peak current of CR-DOMINO Nand logic. Likewise, the peak current of CR-DOMINO Xor logic is also substantially less than the peak current of SABL Xor logic. Thus CR-DOMINO logic is better in terms of the the power dissipation of the circuit. Comparison of different logic styles for Nand and Xor gate in terms of Max. DPA and Area is depicted in Table 1 & Table 2.

Fig10: Current Peak of CR-DOMINO and SABL NAND

Fig11: Current Peak of CR-DOMINO and SABL XOR

Table 1: Characteristics of Various NAND Logic

Table 2: Characteristics of Various XOR Logic

VII. Conclusion

We have designed a logic style to secure devices against side channel attacks by differential power Analysis. Results show that through charge recycling and lower precharge voltages, Charge Recycling Differential Dual Rail Domino logic achieves a 47% reduction in the peak supply current and a 29% reduction in the average power consumption of SABL.