Most of the current portable devices are powered by rechargeable batteries. But the battery based systems have many problems such as the need to recharge or replace these batteries with the time. Also the batteries have a significant weight and size of the whole system and this size increases as the technology scales down. Another alternative for batteries is to utilize environmental sources energy.
Acquiring the environmental sources energy and converting it into a usable electrical energy is called Energy harvesting. Energy harvesting has been around for centuries in the form of windmills, watermills and passive solar power systems. This technology offers two advantages over battery-powered systems, virtually inexhaustible sources and no bad environmental effects. Because of these advantages, this technology is considered a good contributor to the world's energy needs.
In energy harvesting systems, milliwatts of energy can be scavenged from solar, vibrational, thermal and biological sources. Human body can be employed as input energy source for the energy harvesting transducers. In human body, energy can be harvested from the temperature difference between the body and the room, the body here is employed as a Thermal source, or from body gestures and activities, the body is employed in this case employs as a kinetic energy source. Our interest here is the thermal energy generator (TEG) that transforms the temperature difference between the environment and the human body into electrical energy.
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A TEG consists of a large number of thermocouples sandwiched between a hot and a cold plate as shown in figure 1. A thermocouple is made of a hole conducting (P-type) material and an electron conducting (n-type) material connected in series as in figure. When heat flows from the hot to the cold plate, free charge carriers (electrons or holes) move in the direction of heat flow causing a current and a net voltage is produced that can be driven through a load. Due to TEG's small size and working autonomous ability, they can be used in many applications like attachable medical devices, electronic wrist watches, self powered heat sensors and Bluetooth headsets.
Figure 1.1 Single Thermocouple
TEG can be modeled electrically as a voltage source, proportional to the temperature difference across it, in series with a resistor R. In many applications, such as harvesting power from the human body, this temperature difference is only a few degrees in the range of only 5-10 K. so the TEG's open-circuit voltage is in the range of Millivolts.
Figure 1.2 TEG Model
A large number of TEG's are connected electrically in series and thermally in parallel to get higher output voltage but this results in a larger volume and higher cost. Another practical solution is to boost TEG's output voltage to a higher voltage in order to suit any application. Two main techniques are used to implement a step-up DC-DC converter: switched-capacitor charge pump and boost converter with external LC. To achieve fully integrated system, a switched capacitor charge pump is chosen for this design.
Charge Pump Conventional Architectures
The output voltage of thermal electrical generator is very low, less than 1V so it can't be used directly to power any electronic circuits. The minimum voltage required for any transistor to turn on is around 0.7v. Step-up converters are used after the TEG to generate a higher voltage from the available low voltage.
Two main techniques are used to implement a step-up DC-DC converter: switched-capacitor charge pump and boost converter. The charge pump simply consists of some capacitors and switches. Boost converter needs external components such as inductors and capacitors to be implemented. To achieve a fully integrated system, a switched capacitor charge pump is chosen for this design.
The operation of the Charge pump simply depends on charging and discharging capacitances during successive phases and transferring the charge to the output load. To show this idea, consider the circuit in figure 2.1, it is called the voltage doubler and it consists of a capacitor and three switches. The operation is as follows, the capacitor C charges to VDD during the phase Î¦ in which S1and S3 are closed and S2 is open. After this phase the capacitor C has a charge of C*VDD .In the next phase S1 and S3 are open and S2 is open. Due to charge conservation concept the output voltage will be 2VDD. To get a voltage larger than 2VDD, this stage is cascaded .This chapter discusses the conventional architectures used in designing the charge pumps.
Figure 2.1 Voltage Doubler
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2.1 Dickson Charge Pump
Dickson charge pump is the most famous and basic charge pump because it is the first fully integrated pump and designers built any pump based on its idea. Dickson stage is composed of a diode -connected NMOS and a capacitor. Diode connected-NMOS works as the charge transfer device. The two clocks Î¦1 and Î¦2 are out of phase with amplitude VÎ¦, and are connected to alternate node through the capacitors .Figure 2.2 shows five stages of the Dickson charge pump
Figure 2.2 Five-Stage Dickson Charge Pump
2.1.1 Dickson Charge Pump operation
The operation of Dickson charge pump is as follows, initially when Î¦1 is low and Î¦2 is high, MD1 is ON &MD2 is OFF and the voltage at node 1 is , Where is the threshold voltage of NMOS diode-connected. When Î¦1 is high and Î¦2 is low, MD1 is OFF and MD2 is ON and the voltage at node 1 becomes
. MD2 will conduct until the voltage at node 2 is equal to
In the next half cycle, when Î¦2 is high, the voltage at node 2 is
Generally the voltage at node N can written as
And the output voltage after the last diode-connected is expressed as
This equation is derived assuming ideal condition, but if stray capacitances are taken into consideration, the transferred clock amplitude will be reduced by a factor and the output voltage can be written as
Also if a load is added, so a dc current will be driven from the pump and the output voltage will be reduced by the amount, where is the voltage drop per stage when the pump is supplying an output current. Since the total charge pumped by each stage per clock cycle is , the current supplied by the pump at a clock frequency, f, is given by
Rewrite the equation including the effect of the load current, the output voltage becomes
From (6), the pump will work only if
2.1.2 Dickson Equivalent circuit
Equation (6) can be written as
Equation (8) leads to an equivalent circuit to the charge pump as shown in figure 2.3 where V0 and Rout are defined as the open-circuit output voltage and output series resistance of the Pump respectively.
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Figure 2.3 Dickson Charge Pump equivalent circuit
The output node is charging and discharging through the load resistance RL. This will lead to a ripple, VR, at the output voltage. VR can be written as in equation (11)
As noticed from equation (11), increasing the value of the output capacitor or increasing the clock frequency will help to have a small ripple compared to. But increasing the clock frequency should be within a limit to not affect badly on the pump efficiency and power consumption.
2.1.3 Voltage fluctuating and pumping gain
There are two useful quantities should be defined here, Voltage fluctuation at each node, Î”V , and voltage pumping gain per stage, Gv. Î”V is defined as the change in voltage that occurs at each node from one clock cycle to the next. Î”V can be expressed as
by substituting from (11) in (6),the output voltage can now expressed as
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Figure 2.4 Voltage at nodes 1 and 2 of the pump
The voltage pumping gain per stage, Gv , is defined as the increase in voltage that occurs from one node to the next. Gv can be expressed as in the following equation
for Dickson Charge pump ,the gain is
Figure 2.4 shows the voltage fluctuation at each point and the threshold drop from node to the next node.
2.1.4 Dickson charge pump problems
Although Dickson charge pump has very simple architecture, it has a poor performance at low voltage input levels. Dickson's main problem is the threshold drop per stage as indicated in equation (2.15) and hence Î”V should be larger than to obtain a positive voltage step in each stage. Since the clock amplitude is usually equal to VDD, so at low voltage supply levels the value of Î”V will be decreased and this will affect badly on the gain.
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Also body effect problem is considered a significant problem in the Dickson charge pump. Body effect problem occurs due to increasing the source terminal voltage of NMOS from a stage to the next (V2<V3<â€¦..). Due to this problem, threshold voltage of Diode connected-NMOS increases with each stage. This means that as the output voltage of each stage increases, the voltage gain per stage decreases due to increasing body effect. When the threshold voltage of the last stage's transistor becomes equal to Î”V the output voltage will not increase even with the addition of subsequent stages.
These entire make Dickson Charge pump is not suitable for low voltage applications. Several methods have been proposed to avoid problems of drop and to increase the circuit efficiency such as the boosted pump clock scheme, a CTS scheme, and several hybrid versions of these combinations.
2.2 Charge Transfer Switch Scheme (CTS)
In Charge transfer switch scheme (CTS), Pass transistors are used in parallel with the diode connected devices. CTS are used instead of the diodes to transfer the charge between nodes, while diodes are used only for setting up the initial voltage at each pumping node. Charges are transfer from one stage to the next without suffering the problem of threshold voltage drop. The voltage pumping gain per stage can be now expressed as
Two techniques are used to control the CTS, Static and dynamic control. In both control schemes, the gate of the pass transistor is controlled by the next stage voltage, which is in opposite phase.
2.2.1 Static Charge Transfer Switch (Static CTS)
As shown in Figure 2.5 Static CTS uses the next stage higher voltage as a static control for the CTS's. For example, gate of MS1 is always connected to node 2.
Figure 2.5 Static CTS Charge Pump
The voltage at each pumping node at each phase is indicated in table 2.1, where V1 equals and is defined as in equation (2.13)
Table 2.1 Voltage at each pumping nodes
The operation is as follows; when Ï†1 is high and Ï†2 is low, MD2 will be turned ON to set the initial voltage at node 2. The gate-to- source voltage of MS2 is the difference between node 3 and node 2 which is equal to 2Î”V, if
Then MS2 is ON where Vtn is the threshold voltage of NMOS. In the next half cycle,Ï†1 is low and Ï†2 is high, MD2 will be turned OFF and the gate-to-source voltage of MS2 is now the difference between node 3 and node 1 which is equal to 2Î”V also.MS2 will be turned OFF only if
which is not valid. This will create reverse charge sharing problem. Although static CTS achieves higher gain than Dickson, it suffers from reverse charge sharing problem due to incompletely turning OFF of MS2 and this will reduce the efficiency.
2.2.2 Dynamic Charge transfer switch (Dynamic CTS)
The problem of Static CTS is solved by using dynamic control of the CTS's. As shown in Figure 2.6, each CTS is accompanied by an auxiliary circuit that contains of NMOS and PMOS transistors. So CTS's can be turned off completely in the required period and can be turned on by next stage high voltage as in Static CTS.
Figure 2.6 Dynamic CTS Charge Pump
As shown in figure (2.6) gate of Mp2 and Mn2 are connected to node 2.the source of Mp2 is connected to node 3 while the source of MN1 is connected to node 1. The voltage at each pumping node is still defined as in table 2.1.The operation of dynamic CTS is explained as follows. When is high and is low, the source-to-gate voltage of MP2 is V32 which is equal to , the gate-to-source voltage of MN2 is V21 which is zero, and MS2 will be turned ON if
where is the threshold voltage of PMOS and is the threshold voltage of NMOS. When is low and is high, the source-to-gate voltage of MP2 now is zero so MP2 will be turned OFF and the gate-to source voltage of MN2 is 2Î”V ,so Mn1will be turned ON If
and MS2 will be completely turned OFF. From equation (2.19), CTS's are difficult to turn ON in low voltage environment. So Dynamic CTS is not effective at low voltage applications.
2.2.2 Charge transfer switch output stage
In static and dynamic CTS, CTS's can't be used in the output stage since no signal is available for controlling CTS's. The circuit shown in figure 2.7 is used as the output stage of the pump. It contains of two diode-connected NMOS, MD0 and MD5. MD0 is used to push the charge to the output node while MD5 is used to generate a fluctuating voltage waveform to control the previous stage. MD5 is coupled to the clock by a capacitor C5.
Figure 2.7 Pump Output Stage
The operation of output stage is as follows, the source of MS4 is connected to node x and its gate is connected to node 4. When is high and is low, the voltage at node x equals where is the voltage fluctuation at node x which is larger than the nominal due to the absence of load current .The voltage at node 4 equals, then for Mp4
Where can be expressed as
By substituting from equation (2.22) in to equation (2.21), becomes
And the condition for MP4 to be ON is
Also the condition for MS4 to be ON is
Equations (2.24) and (2.25) limit the minimum level of the input supply voltage and the maximum achievable output voltage especially if increasing of among the stages due to body effect is taken into consideration. This limitation can be reduced by increasing the value of and this can be done by using a clock of higher amplitude instead of the normal clock Î¦1. A clock booster is required here to generate the higher amplitude clock. The driving capability of the required clock booster is not large since the loading of the generated clock is relatively small. Finally, the output stage will be as in figure 2.8.
Figure 2.8 Pump Output Stage with Clock Booster
2.3 Pelliconi Charge Pump
One stage of the charge pump proposed by Pelliconi is shown in Figure 2.9. The clock amplitude is equal to . The operation is as follows. After the initial transient, when is high and is low, is set to through M1 and is charged to and connected to through M2.
Figure 2.9 Pelliconi Charge Pump Single Stage
When is low and is high, V1 is set to through M0 and is charged to and connected to through M3. So the output is always after first stage. Pelliconi's stage may be cascaded as shown in figure 2.10 to produce an output voltage larger than .
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Figure 2.10 Pelliconi Charge Pump cascaded Stages
The gain of one stage is but this gain may be reduced due to the parasitic capacitance and stage output resistance. The gain after N stages is approximately given in equation
Where Cs is the parasitic capacitance on the internal nodes of the stage, and Rout is the stage output resistance. Also the output voltage after N stages can be written as in equation
Pelliconi charge pump have many advantages. First, its gain is larger than Dickson gain since it does not suffer from threshold drop. Second, body effect is eliminated by connecting each device substrate to its source so triple-well NMOS transistors are used. It also uses very simple non-overlapping clocking scheme, No specific output stage is needed and it has a completely symmetrical scheme.
The problems of Pelliconi appear at very low voltage levels applications. Since at very low voltage levels, cascading large number of stages is necessary to obtain the desired output voltage and this will result in large output resistance as indicated in equation (2.27 ) so the charge pump will be inefficient.
PROPOSED CHARGE PUMP
There are some issues should be taken in consideration while designing a charge pump. Some of these issues are power efficiency of the pump, output current requirements, output voltage ripples, pump power supply and die area. Power efficiency is a main issue in our design since the maximum output power of the TEG's is extremely small, about only a few milliwatts. Therefore, the charge pump should be carefully designed to extract as much power as possible from the TEG and transfer it to the electronic system.
Also input voltage levels or pump power supply is another important issue in our design, since the open voltage of the TEG is a few millivolts and is dependent on temperature difference. So the capability of working at very low voltage levels and high power efficiency are the two main issues in our charge pump design.
3.1 Charge pump core
Comparison is done between various charge pumps' architectures in table 3.1 to choose the suitable architecture for our design. For gain point of view, It is clear that Dickson charge pump has the lowest gain per stage due the threshold voltage drop while the other charge pumps don't suffer from this problem. The static CTS charge pump has a charge sharing problem due to incompletely turning OFF of the CTS's and this will affect badly on the efficiency which is a main issue in our design.
In the dynamic CTS charge pump, CTS's have a condition to turn ON as indicated in equation 2.19. So CTS's are difficult to turn on in low voltage environment and hence dynamic charge pump is difficult to be used at low voltage levels. In Pelliconi, Cascading larger number of stages results in higher output resistance and lower efficiency. This problem can be solved if the number of stages can be controlled. So Pelliconi architecture is the most suitable for our design.
Threshold drop per stage
Dickson Charge Pump
Charge sharing problem
Static CTS Charge Pump
CTS's are difficult to turned on in low voltage environment
Dynamic CTS Charge Pump
Cascading large number of stages
Pelliconi Charge Pump
Table 3.1 Comparison between various Charge Pumps
The architecture of the proposed charge pump is based on Pelliconi but the PMOS transistors are replaced with diode-connected NMOS transistors due to their low threshold voltage compared to that of the PMOS ones and this is shown in figure3.1. The threshold of the low threshold NMOS transistor in the TSMC 0.25Î¼m CMOS technology is slightly less than 200mV, while regular PMOS transistor threshold voltage is around 0.7.
Figure 3.1 Proposed Charge pump Stage
The diode threshold voltage drop will limit the performance of the proposed charge pump especially at low voltage input. To have a better performance an auxiliary circuit is added to each diode connected to make it more efficient in transferring charge. Also to overcome the problem of cascading a large number of stages, higher clock amplitude is used. The proposed charge pump now is composed of three blocks, the charge pump core, the auxiliary circuit and the clock booster.
3.2 The auxiliary circuit
Figure 3.2 shows two stages of the proposed charge pump with the auxiliary circuit added to each diode-connected The auxiliary circuit is composed of 2 NMOS transistors (Ms's and Mn's) and one PMOS (Mp's). The gate of Mp11 is connected to while its source is connected to . The gate of Mn11 is connected to and its source is connected to. The operation of the auxiliary circuit is explained as follows. when Î¦1 is low and Î¦2 is high (), the voltage at the nodes , , , and are , , , and ,
respectively. The source-to-gate voltage of Mp11 is so
Then MP11 is turned ON causing MS11 to turn ON also. Mn11 is turned OFF since its gate-to source voltage is zero. When Î¦1 is high and Î¦2 is low, the voltage at the nodes , , , and and are , , , and , respectively. The source-to-gate voltage of Mp11 is zero so it will be turned OFF. The gate-to -source voltage of Mn11 is . So if:
Figure 3.2 The Proposed Charge pump with the auxiliary circuit
then Mn11 is turned ON causing MS11 to turn OFF. Comparing (3.1) with (2.19), the proposed charge pump is more suitable for low voltage applications.
The output stage of the proposed charge pump is shown in Figure 3.3. It has no auxiliary circuit since no signal is available to control it. The controlling signal for the previous stage already exist at the nodes Vn1and Vn2, so no special output stage is required
Figure 3.3 Output stage of the proposed charge pump
3.4 The clock booster circuit
The clock booster circuit shown in Figure 3.4 is used to have a clock amplitude of . Clock boosting main role is to have a swing of at each node. Boosting the clock is a must for the auxiliary circuit to work and it also helps in improving the Charge pump performance. Also by clock boosting higher output voltage can be obtained with fewer stages and this will lead to smaller output equivalent resistance. As a result the efficiency will be improved.
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Figure 3.4 Clock Booster Circuit
The operation of the booster is explained as follows. When is high and
is low, then , , and are ON while , , and are OFF. Node x will charge to through . And the node will be connected to ground through . When When is low and is high, , , and are OFF while , , and are ON. The Node now will set to through . The same operation is done for the node
Simulations are done in this chapter to test the performance of the proposed charge pump and the clock booster. Also simulations are done to compare between the proposed charge pump and conventional architectures.
4.1 Proposed charge pump
Simulation is performed using TSMC 0.25Î¼m CMOS technology in SpectreÂ® to test the performance of six-stage charge pump while changing some parameters as current sink to the output, input voltage and clock frequency.
4.1.1Output Voltage Transient Analysis
The output voltage versus time curve is shown in figure 4.1, the transient analysis is performed at no load current and at a clock frequency of 1MHz.When the supply voltage is 300mV, the ideal output voltage after six stages is expected to be 3.9V but due to parasitic capacitances the output voltage is reduced to 3.75V.
Figure 4.1 Charge pump output voltage
The output voltage ripple is 16mV when the load capacitance is 25pF .This ripple is shown in figure 4.2.At the same load capacitance, the time required for the output to reach 90% of its steady state value is equal to 63.84Âµs.
Figure 4.2 Output Voltage Ripples
4.1.2 Efficiency versus Output Current Characteristics
Figure 4.3 shows the efficiency of the proposed charge pump versus output load current at different frequencies. The simulations are done at supply voltage of 0.3V and at different frequencies. The maximum efficiency at 500 kHz, 1 MHz and 1.5 MHz is 68.46%, 66.19 % and 61.1%respectively.
Figure 4.3 Efficiency versus Load Current
4.1.3 Load analysis
In this analysis pump output voltage is plotted versus pump output current. Simulations are done at frequency of 1MHz and at supply voltages of 0.3V, 0.4V and 0.5V. The simulation results are shown in figure 4.4.
Figure 4.4 Output voltage versus Load Current
4.2 Clock booster
Simulations are performed to test the performance of clock booster block
4.2.1 Output Clock and Input Clock
Figure 3.5 shows the input clock which has amplitude of 0.3V and a frequency of 1MHz and the clock after boosting. The boosted clock amplitude is 5. 7V and it has the same frequency. It is clear from figure 3.6 that the two boosted clocks have the same amplitude but they are out of phase.
Figure 4.5 Input clock and Boosted Clock
Figure 4.6 The Two non overlapping output clocks
4.2.2 Output Voltage versus Time at Different Input Voltages
Figure 4.7 shows the simulations results of the boosted clock at different input clock amplitude. The simulations are done at input power supply of 0.3V, 0.4V and 0.5 V.
Figure 4.7 The boosted clock at different
4.3 Comparison between the proposed charge pump and Pelliconi charge pump
Simulation is performed using TSMC 0.25Î¼m CMOS technology in SpectreR to compare between all NMOS Pelliconi charge pump shown in figure 4.8 and the proposed charge pump. To have a fair comparison, the same clock boosting scheme has been used for both circuits with the same value (25pF) of pumping capacitors. All simulations are performed at a clock frequency of 1MHz.
Figure 4.8 All NMOS Pelliconi Charge Pump
4.3.1 Output voltage versus number of stages comparison
Figure 4.9 shows comparison results of output voltage versus number of stages at VDD of 0.3V and Io = 2.8Î¼A. It is clear from the figure that the proposed charge pump offers about 10% higher output voltage at the same number of stages (e.g. for six stages, the output voltage of the proposed charge pump is 3.04V while it is 2.72V in boosted Pelliconi).
Figure 4.9 versus number of stages comparison
4.3.2 Efficiency versus load resistance comparison
The efficiency versus load resistance comparison is shown in Figure 4.10. Simulation are done at VDD = 0.3V and N = 6. The proposed pump maximum efficiency reaches 66% while it is about 57% in Pelliconi with clock boosting.
Figure 4.10 Efficiency versus load resistance comparison
4.3.3 Output voltage versus input voltage comparison
The comparison results of the output voltage versus input voltage are given
in Figure 4.11. The proposed charge pump has higher gain than Pelliconi charge pump with clock boosting as shown in the figure.
Figure 4.11 Output voltage versus Input Voltage Comparison
4.3.4 Output voltage versus output current comparison
The comparison results of the output voltage versus output current are given in Figure 4.12. The proposed charge pump has better drive capability than Pelliconi charge pump with clock boosting as shown below.