# Characteristic Of This Logic Style Computer Science Essay

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The constant delay characteristic of this logic style, regardless of the logic expression makes it suitable in implementing complicated logic expression such as addition. Moreover, Constant delay logic exhibits a unique characteristic where the output is pre-evaluated before the inputs from the preceding stage is ready. The simulation results show that the 4-bit parallel adder and subtractor obtained for constant delay logic style.

Keywords-adder, constant delay, pre-evaluated, feed back, parallel adder.

I. INTRODUCTION

The low power very large scale integration increases the demand for circuit, architecture, and layout design levels. At the circuit design level, power savings should be considerable because of implementing combinational circuits which exists by means of proper choice of a logic style.

Fast and energy-efficient single-cycle 64-bit addition is essential for today's high-performance microprocessor execution core [1].The different logic style method to implement low power VLSI circuit. There are many considerations are important in VLSI circuits, but that power, area and delay important considerations for VLSI design, every logic styles are the own advantages in terms of speed, area and power. There are other difficulties with the dynamic designs as well [2]. The differential power Analysis in particular is of great concern [3] modeling approach reflects the existence of the two modes of operation the most important features are: 1) the presence of fast and slow regions separated by critical slope (cs) line. 2) The critical input slope is a linear function on the output load [4]. Several dynamic threshold voltage MOSFET (DTMOS) logic styles were analyzed for ultralow-power use-from 1.5 down to 0.5 V. Since ordinary pass-transistor logic degrades as the voltages are reduced, we investigated the effects that a dynamic threshold has on various styles of pass-transistor logic[5]-[7], The rest of the paper organized as followed. section II design methodology, section III simulation result.

II. DESIGN METHODOLOGY

The power-delay product metric relates the amount of energy spent during the realization of a determined task, and stands as the more fair performance metric when comparing optimizations of a module designed and tested using different technologies, operating frequencies, and scenarios. Addition is a fundamental arithmetic operation that is broadly used in many VLSI system, such as application-specific architectures and microprocessors.

Many papers have been published regarding the optimization of low-power full-adders, trying different options for the logic style (emitter-coupled logic (ECL), pseudo-NMOS, complementary pass transistor logic(CPTL), double threshold CMOS(DTCMOS), MOS current mode logic(MCML), dynamic, differential domino, and the logic structure used to build the adder module. Adder circuit obtain the sum and carry outputs. First stage output depends on second stage output. Thus, the propagation delay and, in most of the cases, the power consumption of the full-adder depend on the delay and voltage swing of the signal and its complement generated within the cell.so, that increase the operational speed mean reduces the delay and critical path value.

A) Delay: Delay is one of the performance merits for digital system. The delay determines how fast digital circuit can run depend on circuit operating frequency. The delay defined as the propagation delay, tp, which measures system performances depends on change at the input and is measured between the 50% transition points of the input and output waveforms, as shown in figure 2.1.

(1)

response time of a system for a high to low.

response time of a system for a low to high.

The propagation delay a function of the slopes of the input and output signals, as shown in Figure1.The transition time between 10% and 90% of the rise and fall timing waveforms respectively [9].

Figure1 Definition of propagation delay and rise and fall time

Maximum propagation delay is the longest delay between an input changing value and the output changing value. The path that causes this delay is called the critical path. The Power consumption is important in digital system performances. The power consumption of MOS transistors can be categorized as dynamic and static (leakage) power consumption.

B) Static Power Consumption: Typically, CMOS inverters are used in the input and output stage of all the low voltage devices.

Figure 2 CMOS inverter mode for static power consumption

As shown in Figure 2, when input is at logic 0, the p-MOS goes to ON state and the n-MOS remains in the OFF state. The supply voltage VCC appears at the output terminal as logic 1. The opposite operation is performed when the input is at logic 1 with reference of ground terminal. In either logic there is no direct path from VCC to GND due to the switching activity of the device. The resultant quiescent current (DC) is zero. Hence, static power consumption is zero.

C) Dynamic Power Consumption: The dynamic power consumption of CMOS is estimated by addition of the transient power consumption (PT) and capacitive-load power consumption (PL). Switching activities of the MOS devices causes the transients power consumption. This current required to charge the internal nodes (switching current) and through current (current that flows from VCC to GND when both device turn on simultaneously during logic transition). The duration of the current spikes are affected by input signal switching, internal nodes switching and frequency change over. The negligible amount of through current is required for fast input transient of the gate compared with the switching current. So, the dynamic supply current is controlled by the internal capacitance of the IC and the charge plus discharge current of the capacitance. In capacitive-load power consumption, additional power is consumed in charging external load capacitance and is dependent on switching frequency [9]-[11].

D) Feed Through Logic: The dynamic logic families feed through logic rests the output nodes to low when the clock signal goes low, regardless of the input values, cascaded gates firstly rise to their switching threshold value of Vth (typically about Vdd/2), performing a partial transition to a high gain point. At this point all gates in the circuit are in a high gain point. This feature distinguishes the FTL from other logic families [12]. At Vth point any small variation in the input nodes would cause a fast variation of the voltage at the output node, and as the cascade stages evaluation their inputs in a domino like fashion. The output nodes make only a partial transition from the Vth point to the high or low level. Due to the reduction in both low to high and high to low propagation time delays, the FTL speed is high and is well suited to application where the critical path is made of a large cascade of inverting gates. Therefore the problems of non-inverting, charge redistribution and the need for output inverters are eliminated from the domino logics. In order to design the full adder, the three input CMOS inverter required. Since the carry is only the primary concern for performance. To get the carry the pull down transistor must be turned on (Vgs>Vth) if 2/3 inputs are high. If equal capacitors are selected then accord

Vfg = K1V1+K2V2+K3V3 (2)

= 0.33 (3)

Similarly K2 and K3 are also same. Here the Voltage is 1.1V so if only one of the input is high then Vfg(1.1*0.3=0.33) is less than threshold of the transistor. So the pull down transistor is not "on". when transistor M5 is turned on and current is flowing from BL to the storage node, the state of the node will not change[15] [16][18].

Figure 3 Full adder carry generation.

III.SIMULATION RESULT

Two groups to dividing by adder circuits: half adders and full adders. Three input bits add to used full adder but carry input signal comes from the previews adder, the sum and carry are two output to the next stage. Only two input considered to operate the half adder; carry inputs are disregard. Input x and y are two of the input variable signal, represent the two significant bits to be added. The third input, the carry from the previous lower significant position [5].

Subtractors are comparable to adders. Full subtractors are three inputs, that three inputs one of which is the borrow to the earlier subtractor. The two outputs are the difference and the borrow from the following unit. No borrow input having half subtractors [5].constant delay logic 4-bit parallel adder and subtractor circuit diagram shown in Figure 4

Figure 4 4-bit parallel adder and subtractor design using constant delay logic style

The mode input M =1, the circuit becomes a subtractor. One of the inputs of B and input M are given to all exclusive -OR gate. When M=0, then B EX-OR 0=B. The circuit performs A plus B when the input carry is 0 and the full-adders received the value B. When M=1, we have B EX-OR 1= B and Cin=1. The B inputs are all complemented and a 1 is added through the input carry. The circuit performs the operation A plus the 2's complement of B, i.e A-B

Figure 5 Timing waveform of 4-bit parallel adder and subtractor

Clock is high means X and out are pre-discharged and pre-charged to GND and VDD, respectively, at the same time IN=1 for the entire evaluation period that time direct path current flow PMOS to PDN. X rises to a nonzero voltage level and out experiences a temporary glitch.IN goes to 0 before CLK transits to low, X rises to logic 1 and out is discharge to VDD. Delay measured from CLK to out [16].

Timing waveform of 4-bit parallel adder and subtractor shown in Figure 5.Voltage vs time wave form of 4-bit parallel adder and subtractor shown in Figure 6.The power consumption is obtained as 0.905mW. The inputs and the outputs are shown in different colours in the waveform.

Figure 6 Voltage and timing waveform of 4-bit parallel adder and subtractor

CD logic does not require keeper and node X is always connected to either VDD or GND rail except during the contention mode. The inverter protects the internal node and makes the total internal capacitance predictable.

In the Figure 7, the voltage and the current waveforms are shown which is used to analyse the total power consumption of the circuit using micro wind tool [17]. The total power consumed is 0.866mw .The average drain current of these cell is about 9.281mA

Figure 7 Voltage and current waveform of 4-bit parallel adder and subtractor.

C:\Users\Sathish\Desktop\out\1.png

Figure 8 CD Logic 4-bit parallel adder and subtractor capacitance vs delay value.

Also Delay value of CD logic 4-bit parallel adder and subtractor shown in Figure 8. Delay value 0.013ns to 0.043ns depends on capacitance charging and discharging value.

Input time value (11.825ns to 4.14ns) depends on output frequency range (84.57MHZ to 0.24GHZ) value obtain. CD logic is used only to replace the critical path instead of the entire circuit and clock gating can reduce CD logic's power consumption.Delay value 0.013ns to 0.043ns depends on capacitance charging and discharging value.

VI. CONCLUSION

The performance discrepancy between dynamic and static logic is less obvious in next generation CMOS process, i.e, 45nm and below, because interconnect capacitance instead of drain capacitance begins to dominate the delay [16]. However, it is expected that CD logic will remain similar performance enhancement in the future since the improved performance is mainly contributed from both the constant number of transistors in the critical path and the pre-evaluated characteristic. Furthermore, the excessive leakage problem which begins to dominate the overall power consumption in deep-submicron technologies will also help CD logic since CD logic is in a disadvantageous position compared to other logic styles primarily in terms of dynamic power consumption. Hence, in advanced processes such as 45nm and below CD logic is expected to exhibit additional energy efficiency compared to its counterparts. Because of its high performance capability, CD-Logic is particularly suitable for high performance digital application, such as high speed parallel-prefix adder in a high performance arithmetic logic unit in a modern CPU.