Built In Self Test Computer Science Essay

Published: Last Edited:

This essay has been submitted by a student. This is not an example of the work written by our professional essay writers.

This paper presents a model for implementation of BIST structure using Verilog for VLSI circuits. Built-in Self Test is a design technique which allows a circuit to test itself. Linear Feedback Shift Register (LFSR) is used as Pseudo Random Binary Sequence (PRBS) generator for test pattern generation. BIST has gained popularity as an effective solution over circuit test cost, test quality and test reuse problem. BIST technique applied on various circuit under test (CUT) using Xilinx ISE 10.1 simulator.


Test time is a significant component of IC cost. It needs to be minimized and yet has to have minimum coverage to ensure zero-defect. The goal of testing is to apply a minimum set of input vectors to the device to determine if it contains a defect. Costs increase dramatically as faulty components find their way into higher levels of integration. Thus, there is a need for design for testability techniques. For any testing method should have high and easy to verify fault coverage, minimum test patterns to be generated, performance degradation should be minimum and should have reasonable hardware overload.

Built-In Self Test (BIST) provides a simple solution with above requirements. BIST reduces off-chip communication to overcome the limited access for input/output. It simplifies test pattern generation and simulation process. Test scheduling is used to reduce test time for testing multiple units simultaneously. Careful design and Hardware sharing reduces the hardware overhead

BIST is the most popular test solutions to test the embedded cores and the test patterns are not applied by external Automatic Test Equipments (ATEs) but instead generated by inbuilt testing circuit which saves the memory requirement during the test.

Design for testability

Owing to the size and complexity of modern VLSI circuits, design and test are no longer separate. Chips now need to be designed while paying attention to testing. Design for testability (DFT) refers to all those techniques and design practices that enable to test the chips. DFT ensures that test development/ execution time is kept low to be economical, while simultaneously simplifying the tasks of test, debug and diagnosis. DFT methods can be broadly classified into Ad-Hoc DFT and Structured DFT.

Ad-Hoc DFT: This category consists of local modifications made to a circuit with the aim of enhancing its testability. These methods generally involve consultation of good design practices learned from experience. Some examples are making flip-flops (FFs) initializable, avoiding asynchronous logic and combinational loops and inserting test points. Test point insertion may be supports by prior testability analysis. The ad-hoc approach needs manual inspection to identify potential testability issues and bad design practices. Results are unpredictable and it is difficult to automate in the general sense.

Structured DFT: It includes techniques that involve the inclusion of special logic in a circuit with the intent of systematically enhancing the testability and allowing the test execution to be carried out in a well defined manner. Scan-design is the most effective and widely used structured DFT technique. Logic Built-In Self Test (LBIST) is another popular structured DFT technique.

III. Built-in self-test (BIST)

The commonly used test strategies are as follows:

Stored Patterns: Stored-pattern approach stores the pre-generated test patterns to achieve certain test goals. It is often found in system level testing such as the power-on self test of a computer and microprocessor functional testing using micro programs

Exhaustive Testing: Exhaustive testing utilizes all possible inputs to the circuit under test (CUT). It guarantees that all detectable faults that do not produce sequential behaviour will be detected. The strategies are applied to complicate and well isolated small modules like PLAs.

Pseudorandom Testing: Pseudorandom testing applies a certain randomness property. The sequences of the test pattern are in a deterministic order. The fault coverage is determined by the test length and the contents of the patterns.

Weighted Pseudorandom Testing: Weighted pseudorandom testing applied pseudorandom patterns with certain 0s and 1s distribution to handle the random resistant faults undetected by the pseudorandom testing. It can effectively shorten the test length.

Pseudo Exhaustive Testing: Pseudo exhaustive testing partitions the CUT into several smaller sub circuits and test s each of them exhaustively. All detectable faults within the sub circuits can be detected. This method requires extra design effort to partition the circuit and deliver the test patterns and test responses.

BIST is a set of structured-test techniques for combinational and sequential logic, memories, multipliers and other embedded logic blocks.

Principle of BIST:

Test Controller

Response Verification


Test Generation

Fig 1: Block Diagram of BIST

Test patterns are generated and applied to the circuit under test (CUT) or device under test (DUT) and the response is verified.

In Built-In Self Test (BIST), Linear Feedback Shift Register (LFSR) is used to generate the test patterns and Multiple Input Signature Register (MISR) is used to verify the output against the correct response of the CUT as test response evaluation requires the compaction of the output sequence from a circuit under test (CUT) into a short signature of a few bits and the comparison of the fault-free signature with the predetermined fault-free signature to determine whether the CUT is good.

Fig 2: BIST structure

Logic Built-In Self Test (LBIST):

LBIST refers to a DFT methodology in which test is one of the functions of the system/chip. Certain additional constructs are built into the circuit in order to allow the circuit to test itself.

Fig 3: LBIST structure

The main components are Test-Pattern Generator (TPG), Output Response Analyzer (ORA) and a test control mechanism.

The TPG may include a pattern-generator along with optional auxiliary read-only storage.

The ORA typically include a response-compactor along with a signature analyzer which signals any differences detected from a stored reference value and it may also contain diagnostic logic.

In practice, a TPG may generate patterns for one or more CUTs and there may exist separate TPG + ORA structures for different partitions of the circuit. LBIST has become popular owing to the advances in powerful structured DFT techniques such as scan-design, test-data compression techniques and efficient output-response analysis techniques such as signature analysis and transition-count testing.

The advantages of LBIST over conventional ATE-based testing are given below:

1. As pattern-generation and output-analysis are done on-chip, LBIST helps to reduce complexity and cost or eliminate ATEs completely.

2. LBIST enables at-speed testing of circuits which may not be possible with external ATEs. At-speed test is essential for detecting performance-relate defects.

3. As test mechanisms are embedded into the chip, LBIST has a better access to the core logic to be tested.

4. A BIST-ed chip can be tested even after it is part of a system. It allows for possibility for testing both Online (either concurrently or non-concurrently with functional operation) and Offline (to perform either functional or structural testing)

5. LBIST simplifies test-partitioning and fault-diagnosis

6. It has been argued that while the cost of ATEs increases with each process generation, the associated BIST cost (overhead) decreases.

IV Test Pattern Generation for LBIST using LFSR

Various pattern generation schemes have been studied for LBIST. Exhaustive-testing involves the application of all possible 2n input patterns to an n-input combination circuit.

This method is impractical even for a moderately large n. Pseudo-exhaustive testing is a scheme which aims to approximate exhaustive-testing by partitioning the circuit and then exhaustively testing each partition. Partitioning may be done by considering separate fan-in cones of influence for each primary output or dividing the circuit into segments / sub circuits by methods such as described in.

Pseudo-Random testing is the most popular test-generation scheme. A Pseudo-Random Pattern generator (PRPG) is used to generate patterns that satisfy most of the required properties of random numbers while being predictable. A large amount of work has been done on estimating required test-length and

Fault-coverage for pseudo-random patterns. Various structures such as Cellular Automata, ROMs, binary-counters and their modifications have been studied for TPG. Linear Feedback Shift-Registers (LFSRs) are the most commonly used structures for PRPG. The main advantages of LFSRs are their low hardware overhead and output patterns with good quality of randomness.


Liner Feedback Shift Register (LFSR) is an n-bit shift register which pseudo-randomly scrolls between 2n-1 values, but does it very quickly because there is minimal combinational logic involved.

The all zeros case is not possible in this type of LFSR, but the probability of any bit being "1" or "0" is 50% except for that. Therefore, the sequence is pseudorandom in the sense that the probability of a "1" or "0" is approximately 50%, but the sequence is repeatable.

Like a binary counter, all 2n - 1 states are generated, but in a “random” order that is repeatable. The exclusive-OR gates and shift register act to produce a pseudorandom binary sequence (PRBS) at each of the flip-flop outputs. By correctly choosing the points at which we take the feedback from an n -bit shift register we can produce a PRBS of length 2n â€" 1, a maximal-length sequence that includes all possible patterns (or vectors) of n bits, excluding the all-zeros pattern.

In an LFSR, the bits contained in selected positions in the shift register are combined in some sort of function and the result is fed back into the register's input bit.

Fig 4: LFSR structure

The two common types of LFSRs- external LFSR and internal LFSR

(a) An External-XOR/Standard/Fibonacci LFSR is a circular shift-register with a feedback path composed of one or more XOR gates whose inputs are derived from specific bits of the register. The bits contributing to the feedback path are known as `taps'. Thus, an external-XOR LFSR has a feedback bit which is a linear (modulo-2) sum of two or more of its bits.

Fig 5: External LFSR

In an Internal-XOR/Modular/Galois LFSR, each XOR gate is placed between two adjacent LFSR stages (D flip-flops).

Fig 6: Internal LFSR

Fig 7: 3-bit minimal-length LFSR

Feedback around an LFSR's shift register comes from a selection of points (taps) in the register chain and constitutes XOR-ing these taps to provide tap(s) back into the register.

Register bits that do not need an input tap, operate as a standard shift register. It is this feedback that causes the register to loop through repetitive sequences of pseudo-random value. The choice of taps determines how many values there are in a given sequence before the sequence repeats. The implemented LFSR uses a one-to-many structure, rather than a many-to-one structure, since this structure always has the shortest clock-to-clock delay path. The feedback is done so as to make the system more stable and free from errors. Specific taps are taken from the tapping points and then by using the XOR operation on them they are feedback into the registers.

Table 1: Maximal-length sequence for 3-bit LFSR

Signature Analysis

Signature Analysis is a compression technique based on the concept of cyclic redundancy checking. The good and faulty circuits produce different signatures. Test Patterns for BIST can be generated at-speed by an LFSR with only a clock input. The outputs of the circuit-under-test must be compared to the known good response.

In general, collecting each output response and off-loading it from the circuit under test for comparison is too inefficient to be practical. The general solution is to compress the entire output stream into a single signature value

MISR - Multiple-Input Signature Register

A serial-input signature register can only be used to test logic with a single output. The idea of a serial input signature register can be extended to multiple-input signature register (MISR).

There are several ways to connect the inputs of LFSRs to form an MISR. Since the XOR operation is linear and associative, ( A xor B) xor C = A xor (B xor C ), as long as the result of the additions are the same then the different representations are equivalent. If we have an n -bit long MISR we can accommodate up to n inputs to form the signature. If we use m < n inputs we do not need the extra XOR gates in the last n â€" m positions of the MISR. MISR reduce the amount of hardware required to compress a multiple bit stream. LFSR and/or MISR circuit is implemented using a memory already existing in a circuit to be tested.

Fig 8: MISR

If we apply a binary input sequence to LFSR, the shift register will perform data compaction (or compression) on the input sequence. At the end of the input sequence the shift-register contents, Q0Q1Q2, will form a pattern that we call a signature . If the input sequence and the serial-input signature register (SISR) are long enough, it is unlikely (though possible) that two different input sequences will produce the same signature.

If the input sequence comes from logic that we wish to test, a fault in the logic will cause the input sequence to change.

Fig 9: Single Input Signature Register (SISR)

This causes the signature to change from a known good value and we shall then know that the circuit under test is bad. This technique, called signature analysis, was developed by Hewlett-Packard to test equipment in the field in the late 1970s. The simplest form of this technique is based on a single input LFSR. Every LFSR has a characteristic polynomial that describes its behaviour. Degree of polynomial is given by the number of shift registers. Ex: for the fig shown, the characteristic polynomial is given by

P(x) =1+x2+x3

The characteristic polynomial that causes an LFSR to generate maximum length PRBS are called primitive polynomial.

simulation results

LFSR gate level netlist

LFSR output

Circuit under test

a) Fault free Circuit Under Test

b) Faulty Circuit Under Test

c) MISR output due to fault free CUT

d) MISR output due to faulty CUT


In this paper we have illustrated an implementation of BIST logic using Verilog in Xilinx ISE 10.1 Simulator. LFSR is used as a pseudorandom sequence generator. MISR is used as output response analyser (ORA). Behaviour of BIST testing on fault free CUT and faulty CUT is done.

Signature obtained using fault free CUT is 7

Signature obtained using faulty CUT is 0