ASIC is defined as Application Specific Integrated Circuit. It is an integrated circuit which is used for a special application rather than using it for a general application. It is often referred as system on chip (SOC). Normally the final design of ASIC consists of several number of logic gates which is equal to several number of transistors (as one logic gate consists of four transistors). It is very difficult to do the design manually because there will be more chances of going wrong as the design is complex. So for this reason we use some powerful tools called as HDL's, which are commonly called as Hardware Description Languages. Examples of these languages are Verilog and VHDL.
ASIC DESIGN FLOW:
The ASIC design flow typically consists of these stages which are described below,
POST SYNTHESIS TIMING ANALYSIS
FLOOR PLANNING AND PLACEMENT
POST LAYOUT TIMING ANALYSIS
DRC and LVS
The ASIC design flow starts with specification, in which the detailed description of the design in mentioned in this stage. This stage clearly explains about the requirements and functionality which is required to achieve. This is normally represented in high level language.
We then write a behavioural model once the specifications are done. Behavioral model is used to check if the functionality is met or not according to specification. As we know design is a continuous refinement of specifications. Behavioral description is done by using HDL's. This can be done either in VHDL or verilog. One of the most commonly used tool for the behavioural design is MODELSIM ( from Xilinx). We can check the functionality of the design using the simulator. There is a tool called X-HDL 3 which can directly convert from behavioural to RTL. But even this tool has some drawbacks. It cannot understand complex codes. We can solve this problem by using PERL SCRIPTS.
RTL DESIGN AND VERIFICATION:
We then write an RTL model of the VHDL and verify it with the behavioural model for its functional correctness. We write the RTL design model either in VHDL or verilog. Let us assume that the project is designing a digital counter, then the file we can get in this stage is digital_counter.vhd. MODELSIM from Xilinx supports for behavioural as well as RTL design.
DFT is called as Design for Testability; we cannot easily find the faults that are occurred during ASIC manufacturing process. To find the faults during the manufacturing process we use some techniques called DFT insertion. In this process we add some piece of hardware during manufacture for easy testability. The hardware include,
Scan Cell insertion: We will insert a boundary scan cell to each node of the design.
BIST: Built in self test, it inserts some test patterns and checks the output with the result that is present in the RAM.
ATPG: Automatic test pattern generation, in this we generate some pattern of test vectors for testing the design. This can be done by using some patterns called PRPG and signature analyzer.
The verified RTL in the earlier stage undergoes to logic sysnthesis. Logic synthesis is the format of converting the RTL design in to net list or technology dependant libraries. In this stage the RTL description is mapped in to the libraries that are present in the foundary. The logic synthesis is done by logic analyzer.
The synthesis can be done using many tools that are persent in the market. Some of them are Xilinx synthesizer from XILINX, Build gates from CADENCE and Design vision from SYNOPSIS. These tools convert the RTL to PDK technology libraries and it also includes some of the special information like capacitance and timing information. Build gates uses .alf file and design vision uses .db file from the PDK library file.
Now let us consider the steps that are involved in design vision,
Read the VHDL file
Set the .db file into the library
Analyze the deign
Elaborate the design
Compile the design
Schematic of Design after compilation
After the net list is done, the technology of the ASIC is chosen according to the application. There are different types of ASIC technologies, they are
This type of design is called as "Design from scratch". This type of design is good in terms of less area and high performance. But cost is high and risk is also high. It also takes more time for manufacture.
Standard cell uses pre defined cells such as AND, OR, FLIP FLOP etc. These are most efficient to use because of their low cost, less time and less risk.
In this type of technology, transistors are pre defined and only the interconnections are made by the user. The gate arrays are three type,
In channelled gate array there will be space in between the rows of the cells for their interconnections. Manufacturing time is very less. But only drawback is that, gates are not utilised effectively.
In the channel less gate array there will be no space available for interconnections. Routing is done on the top of the rows.
In the structured gate array, it is a combination of gate array and standard cell. In this type we can embed some standard cells into the design.
According to the application, we choose the technology.
Let us consider a scenario where the ASIC is to be selected according to requirement. The requirements are, Medical device, Low power, Analogue to digital sections, Development cycle is less than 3 months.
ASIC TYPE LOW POWER A TO D DEVELOPMENT CYCLE
FULLCUSTOM 1 4 1
STANDARD CELL 2 4 3
GATE ARRAY 3 1 3
FPGA 3 1 4
CPLD 4 1 4
If we add all the technologies together we will get standard cell highest. According to the above scenario, Standard cell is the best suitable technology.
The net list which is generated is undergone in to formal verification to see whether the generated net list is equal to the RTL description or not.
The generated net list is opened in to Virtuso, in which it is represented as a schematic. The circuit is checked with an "analogue simulator" for its correct operation.
POST SYNTHESIS TIMING ANALYSIS:
The timing results are analyzed after synthesis and we also check the performance of our design. The RTL description can also be changed accordingly until we get the optimal timing. This process is repetitive until the goal is reached.
In this stage sdf's are added to the PDK libraries that are present. SDF's are standard delay files. These files contain all the delay and timing information.
Top Hierarchy of the Design
To use the silicon ensemble software, a .lef file and a layer .map file are needed. . lef file explains about the placement of pins and .map file describes the layers.
Once we achieved the timing constrains we then look into the floor plan, in this stage we will decide which component to place where in the die. This step also includes the insertion of "clock tree". For digital circuits it is done automatically and for analogue and mixed signals the placement is done manually.
We use software called silicon ensemble for floor plan. It also defines the distance of VDD and GND, area of the floor plan and density of the cells. The floor plan window can be seen below,
Floor plan window
The routing includes the interconnections between the blocks that are placed on a die. We can select the routing such that the routing is done automatically without wastage of any place. For digital circuits it is done automatically and for analogue and mixed signals the routing is done manually.
Cells after Routing
POST LAYOUT TIMING ANALYSIS:
The system is again checked with the performance requirements. If the requirements are not met the floor plan can be changed and the routing options can be changed. This is done until the performance requirements are met. The actual timing check is done during this stage because, until this stage the device is not placed and routed. The net timing can be calculated at this stage.
DRC: Design Rule Checking is to is whether the design in made in industry standards or not. The design rules include the representation of design in the form of polygons. There are two types of design rules which we commonly use they are lambda based design rules and micron based design rules.
LVS: Layout versus Schematic, this is to check whether the functionality of the net list is equal to the design after layout.
Tape out format is GDS II, it is a binary file. This file is handed to the industry for fabrication. GDSII format is a standard industry format which is used for IC layout. This format consists of some geometrical shapes and text labels. The GDSII file format is in binary format. The binary format is used to create photo masks by using different powerful tools. It is first designed for photos masking in IC's. But, because of its features it finally became industry standard for layout.
These files are first produced on magnetic tapes. So they are referred as GDS II tape out files. The objects in the tape out are combined using some techniques for identification. The techniques include layer number, text type which corresponds to "layers of material" utilised in the manufacturing of an IC. Likewise all the parts are integrated and finally they reflect the design of a physical layout. GDSII can convert 2D format of the layout to 3D format and also it can converts the binary format to the human readable formats.
TOOLS USED IN THE DESIGN FLOW:
This is a product of cadence. Here, this tool can be used to synthesise the design.
Universal platform support:
This supports almost all operating systems.
This saves about 50 percent of time and produces good results. This also offers improvement of overall current and capacity.
Build gate produces a high version of automated solutions.
This is a auto place and root tool from cadence. It is meant to place the cells efficiently and quickly.
Fast processing to tape out with timing and design features.
It can predict the "technology engine" throughout the design flow.
This supports the foundry requirements of 130nm.
Modelsim is a tool from Xilinx and if the design contains some digital information, this tool can be used.
Xilinx synthesizer is also a tool from Xilinx. It is mainly used for FPGA synthesis.
DATA FORMATS USED IN THE DESIGN FLOW:
If we use different tools from different vendors, it may create a problem because, it will be difficult if the tool doesn't support the data format.
This language is used to describe a circuit. It supports multiple vendors and multiple design environments. The programming styles of VHDL are behavioural, structural and RTL.
It is more suitable for logic simulation. It is used to describe a circuit.
For that we use EDIF which is known as Electronic Data Interchangeable Format. The main objective of this is to interchange the data formats between the tools.
Used for timing information. We will get good results if the timing information of a design is known.
Format used for the layout and production. It is a binary file.
The most important aspect in ASIC technology is the past cost. This varies from 1$ to 100$ per device. For any device there are two types of costs, fixed cost and variable cost.
Product cost= (fixed cost + variable cost) * products sold.
Fixed cost in independent of number of items sold and cost per product becomes more if less number of products are sold. Variable cost includes manufacturing costs, assembly costs etc.
Total part cost=(fixed cost+ variable cost )*volume of parts.
Chart showing break even volumes of ASIC technologies
Let us consider a product life time is 18 months and sales increases linearly at $10 million per quarter and product reaches peak sales, product reaches to the end of product life. The model is shown below,
Product life cycle
As the above graph shows because of the two weeks delay the revenue loss is 13%.
TIME TO MARKET:
The revenue loss of the product depends on half life of the product and the delay that happened while introducing the product to the market.
Revenue lost = (3hd-d) 2 / 2h2
Where 'h' is half life of product and 'd' is delay.
Libraries are the important units of ASIC design. For FPGA's the companies provide some standard libraries to the user in the form of 'design kit'. But there are many other options like some times the vendor provides the libraries or we can get the libraries from the third party or we can design our own libraries. The vendor library normally consists of empty cells. These are filled by the vendor during the manufacture process of the chip. Normally the libraries are made by their own. But, created libraries should have the following information,
Wire load model
ASIC libraries contain many number of sequential and combination cells to perform the logic operation. They are arranged together according to the required function. The library consists of many models. Out of which some of them are AND, OR, NOT, NAND, NOR, OR, FLIP FLOPS, XOR, XNOR, etc.
The ASIC libraries should be very efficient and robust. They are usable by anyone without any difficulty. They should be portable and cost should be less.
The ASIC design flow has been proposed from VHDL to GDS-II tape out. The tools are explained briefly in the design flow and cost of the design flow is estimated. The asic libraries are described briefly. The main use of following an ASIC design flow is it gives clear idea to the designer where we are and where we need to go ahead. It also clearly specifies the steps involved in the design for future use.