Analysing Data On The Controller Area Network Computer Science Essay

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Aim= The aim of the project is to analyse data on controller area network (CAN) bus, in other words we should extract the data field from message frame (packet).

Hardware Topology =

Stand-Alone CAN-BUS Analyser circuit design:

CANH These both are connected on one circuit board








68HC11F1-development board






So from the topology we can say that the CAN differential signal is connected to CAN transceiver (MCP2551) which in turn is connected to CAN controller (MCP2515) with Tx and Rx pins accordingly, one for transmitting and one for receiving. These two can be placed in one board which must be connected to MC68HC11F1 development board. This connection is done using SPI (serial protocol interface) between CAN controller (MCP2515) and 68hc11 (Motorola microcontroller).Thus the development (MC68HC11F1) board is connected to a laptop using RS232 interface.

Some Data Related to project =

Basic Topology of CAN =

CAN_H (can _high) And CAN_L (can _low) =

CANH and CANL is a "differential" pair. CANL, CANH and ground (not necessary when the nodes or isolated from dc and ac) are the three different lines that are generally include in CAN. The value is '1' when the difference between CANL and CANH is positive and greater than a certain minimum voltage and '0' when the difference is negative. When design needs lengthy cable with twisted pair type of cable then CAN bus with two lines CANH and CANL is used. If some disturbance occurred in the cable, it is going to affect both wires in same way, which is in result cancelled. In Higher communication speed there should be no reflections in the cable which is achieved by balancing line using nodes with same cable impedance.

CAN Data Extended Frame =

Based upon the CAN 2.0b standards all packets and schema on CAN bus are designed.  CAN bus can assume either of the two positions, dominant (less logical) or recessive (more logical).  For an example if two devices are pointing the CAN bus concurrently, one is having dominant bit another is having recessive bit, generally by default bus will presume the dominant state. While transmitting the value of the bus is read by all devices. When a device is passing a recessive bit but is reading a dominant bit, it will wait until that device is finished to reattempt transmission even it knows that another device is transmitting.  By this way system allows easy connection of several devices to the bus without any supplementary collision detection. This system uses only Standard Data Frames.  Each one of the frame contain one dominant start bit, to establish message priority and recognition a 32-bit arbitration field is used, data length code is included in a 6-bit control field, a data field is ranging from 0 to 8 bytes, for error detection a 16-bit cyclic redundancy check (CRC) field is used, and a 7-bit end-of-frame field.  In this standard, top priority is given to frames with lesser values of the arbitration field i.e. dominant bits with high essential positions. So with this standard data frame we could be dealing with 128-bits in total.

Extended frame format =

Field name

Number of Bits




Denotes the start of frame transmission

Identifier A


First part of the (unique) identifier for the data

Substitute remote request (SRR)


Must be recessive (1)Optional

Identifier extension bit (IDE)


Must be recessive (1)Optional

Identifier B


Second part of the (unique) identifier for the data

Remote transmission request (RTR)


Must be dominant (0)

Reserved bits (r0, r1)


Reserved bits (it must be set dominant (0), but accepted as either dominant or recessive)

Data length code (DLC)*


Number of bytes of data (0-8 bytes)

Data field

0-8 bytes

Data to be transmitted (length dictated by DLC field)



Cyclic redundancy check

CRC delimiter


Must be recessive (1)

ACK slot


Transmitter sends recessive (1) and any receiver can assert a dominant (0)

ACK delimiter


Must be recessive (1)

End-of-frame (EOF)


Must be recessive (1)

The two identifier fields (A & B) combined form a 29-bit identifier

Physical CAN connection according to ISO 11898-2 =

Schematics for CAN Transceiver and Controller:

RS232 Interface Schematic:

Power Description:

MCP2551 Transceiver:

1) Features:

1 Mb/s process are supported

ISO-11898 physical layer standard requirements are implemented

Applicable for both 12Volts and 24Volts systems

To condense RFI emissions externally-guarded slope is used

Identification of root cause i.e. permanent dominant on TXD input

Protected voltage brown-out and power-on reset

CAN bus will not be disturbed by either brown-out event or unpowered node

Less current supply operation

Safe guard against damage caused by short-circuit(positive or negative battery voltage)

High-voltage passing is prevented

Protecting by automatic thermal shutdown

Can be connected up to 112 nodes

Due to differential bus operation there is a high noise resistance

Temperature ranges for Extended (E): -40°C to +125°C and for Industrial (I): -40°C to +85°C


The MCP2551 CAN outputs will drive a minimum load of 45Ω, allowing a maximum of 112 nodes to be connected (given a minimum differential input resistance of 20 kΩ and a nominal termination resistor value of 120Ω).

3) Pin Descriptions:


TXD is a TTL-compatible input pin. The data on this pin is driven out on the CANH and CANL differential output pins. It is usually connected to the transmitter data output of the CAN controller device. When TXD is low, CANH and CANL are in the dominant state. When TXD is high, CANH and CANL are in the recessive state, provided that another CAN node is not driving the CAN bus with a dominant state. TXD has an internal pull-up resistor (nominal 25 kΩ to VDD).

2) GROUND SUPPLY (VSS): Ground supply pin.

3) SUPPLY VOLTAGE (VDD): Positive supply voltage pin.


RXD is a CMOS-compatible output that drives high or low depending on the differential signals on the CANH and CANL pins and is usually connected to the receiver data input of the CAN controller device. RXD is high when the CAN bus is recessive and low in the dominant state.

5) REFERENCE VOLTAGE (VREF): Reference Voltage Output (Defined as VDD/2).


The CANL output drives the low side of the CAN differential bus. This pin is also tied internally to the receive input comparator.


The CANH output drives the high-side of the CAN differential bus. This pin is also tied internally to the receive input comparator.


The RS pin is used to select High-speed, Slope-control or Standby modes via an external biasing resistor.

4) Block diagram:

5) Operating Modes:

Three types of modes operation that are allowed to select in RS pin are as follows:




When in High-speed or Slope-control mode, the drivers for the CANH and CANL signals are internally regu­lated to supply controlled balance in order to lessen EMI emissions. Additionally, the slope of the signal transitions on CANH and CANL can be controlled with a resistor connected from pin 8 (RS) to ground, with the slope proportional to the current output at RS, further reducing EMI emissions.


High-speed mode is selected by connecting the RS pin to VSS. In this mode, the transmitter output drivers have fast output rise and fall times to support high-speed CAN bus rates.


Slope-control mode further reduces EMI by limiting the rise and fall times of CANH and CANL. The slope, or slew rate (SR), is controlled by connecting an external resistor (REXT) between RS and VOL (usually ground). The slope is proportional to the current output at the RS pin. Since the current is primarily determined by the slope-control resistance value REXT, a certain slew rate is achieved by applying a respective resistance. Figure 1-1 illustrates typical slew rate values as a function of the slope-control resistance value.


The device may be placed in standby or "SLEEP" mode by applying a high-level to RS. In SLEEP mode, the transmitter is switched off and the receiver operates at a lower current. The receive pin on the controller side (RXD) is still functional but will operate at a slower rate. The attached microcontroller can monitor RXD for CAN bus activity and place the transceiver into normal operation via the RS pin (at higher bus rates, the first CAN message may be lost).

Test circuit for MCP2551:

CAN Controller (MCP2515):

1) Description:

MCP2515 is a Microchip Technology of standalone Controller Area Network (CAN) is a controller that imple­ments the CAN specification with version 2.0B. Which is able to handle both pass on and retrieving the standard, extended data and also remote frames. To filter unnecessary messages acceptance masks two and acceptance filters six are there in MCP2515, which in turn dipping the host MCUs operating cost. By using industrial standard Serial Peripheral Interface, SPI MCP2515 interacts with Microcontrollers(MCUs).

2) Features:

Implements CAN V2.0B at 1 Mb/s:0 - 8 byte length in the data field -Standard and extended data and remote frames.

Filters, masks and receive buffers: Six 29 bit filters, Two 29bit masks and Two receive buffers with priority message storage

Data byte filtering on the first two data bytes (applies to standard data frames).

Three transmit buffers with prioritization and abort features.

High-speed SPIâ„¢ Interface (10 MHz): -SPI modes 0,0 and 1,1.

One-shot mode ensures message transmission is attempted only one time.

Clock out pin with programmable prescaler: Can be used as a clock source for other device(s).

Start-of-Frame (SOF) signal is available for monitoring the SOF signal: Can be used for time-slot-based protocols and/or bus diagnostics to detect early bus degradation.

Output pin is Interrupt with selectable enables.

Buffer Full output pins configurable as: Interrupt output for each receive buffer -General purpose output.

Request-to-Send (RTS) input pins individually configurable as, Control pins to request transmission for each transmit buffer -General purpose inputs.

Low-power CMOS technology, Operates from 2.7V - 5.5V -5 mA active current (typical) -1 µA standby current (typical) (Sleep mode).

Temperature ranges sustain to Industrial (I) 40°C to +85°C and Extended (E) 40°C to +125°C.





I/O/P Type


Alternate Pin Function





Transmit output pin to CAN bus






Receive input pin from CAN bus






Clock output pin with programmable prescaler

Start-of-Frame signal





Transmit buffer TXB0 request-to-send. 100 kΩ internal pull-up to VDD

General purpose digital input. 100 kΩ internal pull-up to VDD





Transmit buffer TXB1 request-to-send. 100 kΩ internal pull-up to VDD

General purpose digital input. 100 kΩ internal pull-up to VDD





Transmit buffer TXB2 request-to-send. 100 kΩ internal pull-up to VDD

General purpose digital input. 100 kΩ internal pull-up to VDD





Oscillator output






Oscillator input

External clock input





Ground reference for logic and I/O pins






Receive buffer RXB1 interrupt pin or general purpose digital output

General purpose digital output





Receive buffer RXB0 interrupt pin or general purpose digital output

General purpose digital output





Interrupt output pin






Clock input pin for SPIâ„¢ interface






Data input pin for SPI interface






Data output pin for SPI interface






Chip select input pin for SPI interface






Active low device reset input






Positive supply for logic and I/O pins






No internal connection

Note: Type Identification: I = Input; O = Output; P = Power

4) Transmit/Receive Buffers/Masks/Filters:

The MCP2515 has three transmit and two receive buffers, two acceptance masks (one for each receive buffer) and a total of six acceptance filters. Figure below shows a block diagram of these buffers and their connection to the protocol engine.


1 Receive Message Buffering:

The MCP2515 has two full receive buffers with several reception filters for each. Which also include separate Message Assembly Buffer (MAB) that acts as third receive buffer


MAB is one of the three receiving buffers, which is dedicated to collect the next message from the bus. The MAB assembles all messages received and if the filtering conditions are satisfied these messages are sent to the RXBn.

1.2 RXB0 AND RXB1:

The remaining two receiving buffers are RXB0 and RXB1, which will receive a complete message from the protocol engine via the MAB. Once the message is accepted the entire contents of the MAB is sifted to receive buffer.

Which means that, the entire receive buffer is overwritten with the MAB contents irrespective the type of the identifier either standard or extended and the no. of data bytes retrieved. Therefore, when any message is received all registered contents in the buffer are assumed to be modified. MCU can process one buffer when another buffer is vacant for message receiving, or for holding a previously received message.


When a message is moved to receive buffers, the correct CANINTF.RXnIF bit is set. In order to allow to receive new messages to the buffer CANINTF.RXnIF bit must be unoccupied by the MCU. Before the MCP2515 tries to update a new message to the receive buffer the bit provides a positive keep out to ensure that the MCU has completed with the message. If the CANINTE.RXnIE bit is set, disrupt will be created on the INT pin to specify that a valid message has been received.

5.2 Receive Priority:

RXB0, the higher priority buffer, has one mask and two message acceptance filters associated with it. The received message is applied to the mask and filters for RXB0 first. RXB1 is the lower priority buffer, with one mask and four acceptance filters associated with it. In addition to the message being applied to the RB0 mask and filters first, the lesser number of acceptance filters will make the match on RXB0 more controlled and entail to more priority for that buffer.


Additionally, the RXB0CTRL register can be configured in such a way that when RXB0 consists a valid message and will receive another valid message, the new message will be passed to RXB1 without creating any overflow error, irrespective of the acceptance criteria of RXB1.

5.2.2 RXM BITS:

The RXBnCTRL.RXM bits are set as special receive modes. Normally, these bits are cleared to 00 so that it is enable for reception to all valid messages that are determined by the suitable acceptance filters. In this particular case to decide whether to accept or not to accept either standard or extended messages is obtained by the acceptance filter register of RFXnSIDL.EXIDE bit. The receiver will only approve messages with standard or extended identifiers, respectively when the RXBnCTRL.RXM bits are placed to either 01 or 10. If an acceptance filter has the RFXnSIDL.EXIDE bit is placed in such a way that it is not communicating with the RXBnCTRL.RXM mode, that acceptance filter is turn into useless. These two modes of RXBnCTRL.RXM bits can be used by the systems when it is recognize that only either standard or extended messages are on the bus. When RXBnCTRL.RXM bits are placed to 11, all messages are obtain in the buffer, in spite acceptance filters values. When there is an error in the message earlier EOF then that part of the message is collected in the MAB prior to the error frame is loaded to the buffer. Some value is present in this mode to debug CAN system which is not used generally in the actual system environment.



The MCP2515 has eight sources of interrupts. The CANINTE register contains the individual interrupt enable bits for each interrupt source. The CANINTF register contains the corresponding interrupt flag bit for each interrupt source. When an interrupt occurs, the INT pin is driven low by the MCP2515 and will remain low until the interrupt is cleared by the MCU. An interrupt cannot be cleared if the respective condition still prevails. It is recommended that the bit modify command be used to reset flag bits in the CANINTF register rather than normal write operations. This is done to prevent unintentionally changing a flag that changes during the write command, potentially causing an interrupt to be missed. It should be noted that the CANINTF flags are read/write and an interrupt can be generated by the MCU setting any of these bits, provided the associated CANINTE bit is also set.

7.1) Receive Interrupt:

When the receive interrupt is enabled (CANINTE.RXnIE = 1), an interrupt will be created on the INT pin once a message has been successfully received and loaded into the associated receive buffer. This interrupt is activated immediately after receiving the EOF field. The CANINTF.RXnIF bit will be set to indicate the source of the interrupt. The interrupt is cleared by clearing the RXnIF bit.


The MCP2515 is designed to be operated with a crystal or ceramic resonator linked to OSC1 and OSC2 pins. The need of Parallel cut crystal is required in MCP2515 oscillator design instead of a series cut crystal which may cause out of frequency of the crystal manufacturing specifications. MCP2515 may also be driven by an external clock source connected to the OSC1 pin and OSC2 left open.

8.1) Oscillator Start-up Timer:

The MCP2515 utilizes an Oscillator start-up Timer (OST) that holds the MCP2515 in reset to ensure that the oscillator has stabilized before the internal state machine begins to operate. The OST maintains reset for the first 128 OSC1 clock cycles after power-up or a wake-up from Sleep mode occurs. It should be noted that no SPI protocol operations should be attempted until after the OST has expired.


The MCP2515 differentiates between two resets:

Hardware Reset - Low on RESET pin.

SPI Reset - Reset via SPI command.

Both of these resets are functionally equivalent. It is important to provide one of these two resets after power-up to ensure that the logic and registers are in their default state. A hardware reset can be achieved automatically by placing an RC on the RESET pin. The values must be such that the device is held in reset for a minimum of 2 μs after VDD reaches operating voltage, as indicated in the electrical specification (tRL).


The MCP2515 has five modes of operation. These modes are:

Configuration mode.

Normal mode.

Sleep mode.

Listen-only mode.

Loopback mode.

The operational mode is selected via the CANCTRL. REQOP bits. When changing modes, the mode will not actually change until all pending message transmissions are complete. The requested mode must be verified by reading the CANSTAT.OPMODE bits.

10.1) Listen-only Mode:

Listen-only mode provides a means for the MCP2515 to receive all messages (including messages with errors) by configuring the RXBnCTRL.RXM<1:0> bits. This mode can be used for bus monitor applications or for detecting the baud rate in 'hot plugging' situations. For auto-baud detection, it is necessary that there are at least two other nodes that are communicating with each other. The baud rate can be detected empirically by testing different values until valid messages are received. Listen-only mode on that other hand known as silent mode, in which there is no transmission of the messages including error flags or acknowledge signals. To allow only certain particular messages to be loaded into the receive registers

Filters and masks are used. Masks can be set to all zeros to allow a message with any identifier to pass. The error counters are reset and deactivated in this state. The Listen-only mode is turn on by setting the mode request bits in the CANCTRL register.


11.1) Overview:

The MCP2515 is designed directly to supports Mode 0, 0 and Mode 1, 1 and designed interface with Serial Peripheral Interface (SPI) port accessible by huge microcontrollers. Commands and data can be sent to the device by using SI pin, with a data regulator on the increasing end of SCK. Data is being sending out by the MCP2515 on the SO line lying on the declining edge of SCK. While any operation is going on the CS pin must be held low.

[Note: The MCP2515 expects the first byte after lowering CS to be the instruction/command byte. This implies that CS must be raised and then lowered again to invoke another command.]

11.2) Reset Instruction:

The Reset instruction can be used to re-initialize the internal registers of the MCP2515 and set Configuration mode. This command provides the same functionality, via the SPI interface, as the RESET pin. The Reset instruction is a single-byte instruction that requires selecting the device by pulling CS low, sending the instruction byte and then raising CS. It is highly recommended that the reset command be sent (or the RESET pin be lowered) as part of the power-on initialization sequence.

11.3) Read Instruction:

The Read instruction is started by lowering the CS pin. The Read instruction is then sent to the MCP2515 followed by the 8-bit address (A7 through A0). Next, the data stored in the register at the selected address will be shifted out on the SO pin. The internal address pointer is automatically incremented to the next address once each byte of data is shifted out. Therefore, it is possible to read the next consecutive register address by continuing to provide clock pulses. Any number of consecutive register locations can be read sequentially using this method. The read operation is terminated by raising the CS pin.

11.4) Read RX Buffer Instruction:

The Read RX Buffer instruction provides a means to quickly address a receive buffer for reading. This instruction reduces the SPI overhead by one byte, the address byte. The command byte actually has four possible values that determine the address pointer location. Once the command byte is sent, the controller clocks out the data at the address location the same as the Read instruction .This instruction further reduces the SPI overhead by automatically clearing the associated receive flag (CANINTF.RXnIF) when CS is raised at the end of the command.

11.5) Write Instruction:

The Write instruction is started by lowering the CS pin. The Write instruction is then sent to the MCP2515 followed by the address and at least one byte of data. It is possible to write to sequential registers by continuing to clock in data bytes, as long as CS is held low. Data will actually be written to the register on the rising edge of the SCK line for the D0 bit. If the CS line is brought high before eight bits are loaded, the write will be aborted for that data byte and previous bytes in the command will have been written.

11.6) Read Status Instruction:

The Read Status instruction allows single instruction access to some of the often used status bits for message reception and transmission. The MCP2515 is selected by lowering the CS pin and the read status command byte is sent to the MCP2515. Once the command byte is sent, the MCP2515 will return eight bits of data that contain the status. If additional clocks are sent after the first eight bits are transmitted, the MCP2515 will continue to output the status bits as long as the CS pin is held low and clocks are provided on SCK. Each status bit returned in this command may also be read by using the standard read command with the appropriate register address.

11.7) RX Status Instruction:

The RX Status instruction is used to quickly determine which filter matched the message and message type (standard, extended, remote). After the command byte is sent, the controller will return 8 bits of data that contain the status data. If more clocks are sent after the 8 bits are transmitted, the controller will continue to output the same status bits as long as the CS pin stays low and clocks are provided.

11.8) Bit Modify Instruction:

The Bit Modify instruction provides a means for setting or clearing individual bits in specific status and control registers. This command is not available for all registers.