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In today's digital world, analog-to-digital converter (ADC) continues to play a vital role. When interfacing with real world, inputs and outputs are usually analog. ADCs are important building blocks in many electronic applications such as digital communication system, data acquisition system and industrial automation system.
There are different types of ADCs and each conversion method has its own set of advantages and disadvantages. Flash A/D conversion is the fastest possible way to quantize an analog signal. In order to achieve N-bits from a flash ADC, it requires 2N-1 reference levels and digital encoding circuits. Dual slope converter gives high resolution but A/D conversion rate is low. In order to achieve N-bit resolution, a successive approximation ADC requires N clock cycles and the performance is limited by digital to analog converter (DAC) linearity. The advantage of pipeline ADC is that the conversion rate does not depend on the number of stages. The overall speed is determined by the speed of the single stage. The disadvantage is that the circuitry is more complex. These are Nyquist rate converters; the sampling rate can be as low as Nyquist criterion requires i.e. twice the bandwidth of the input signal. (Kevin M.Daugherty (1995) and Phillip E.Allen, Douglas R.Holberg (2004)).
1.1 Delta-Sigma ADC
Delta-Sigma ADC provides high resolution by over sampling (many times the Nyquist rate) and feedback integration and converts resolution in time to resolution in amplitude. The sampling rate is much higher than Nyquiste rate. The Delta-Sigma ADC, which is also known as Delta-Sigma Modulator (DSM), generally requires fewer and simpler components than Nyquist-rate converters and is more robust against circuit imperfections. As a result, DSMs are ideal for on-chip VLSI implementation in relatively low bandwidth applications such as controllers for dc motors. The DSM achieves quantization noise shaping i.e. it pushes the quantization noise outside the signal band. The quantizer output toggles about the input signal so that the average quantizer output is approximately equal to the average of the input. In both communications and power electronics, the aim is to design the DSM such that the input signal is passed through the system with minimal distortion from noise for full range of amplitude and frequency of input signal. The DSM with scalar/vector quantizer is capable of driving single-phase/three-phase bridge type switching converters directly (Glen Luckjiff and Ian Dobson (2005)). The unit of input and output quantities of different blocks mentioned in the different block diagrams in this thesis is in Volts.
In the case of conventional DSMs, TU refers to the update period. It is the period during which average values of input and output are taken. The period TC refers to the sampling period (the period at which the input signal is sampled) and also the operating clock period of DSM.
In the case of proposed DSMs and proposed multipliers (except in DSM4), TU refers to the update period and also the sampling period. The period TC refers to the operating clock period of DSM.
1.1.1 Conventional First-Order DSM
The conventional discrete first-order DSM is shown in Fig.1.1. The sampling of input signal and DSM operation is performed by the same clock signal with period TC. The input is an analog signal ranging from -1 to +1 and the output is a digital signal either -1 or +1. Both input and output are normalized to supply voltage of the circuit. The sampled analog input signal and the quantized output signal are fed to the summing unit. The error signal from the summing unit is integrated and quantized by the single bit quantizer. The feedback forces the average value of the quantized signal to track the average input. Any difference between the input and output accumulates in the integrator and eventually corrects itself due to negative feedback. Let the first-order DSM, which is shown in Fig.1.1, is operating at the clock with period TC and the average values of input and output are taken during the update period TU ( TU >> TC ).
Figure 1.1 Conventional First-Order DSM
In Fig.1.1, x(i), x1(i) and y(i) represent the ith sample of input signal, integrator output and quantizer output respectively. The quantization error signal during ith sampling period is denoted as e(i). The average value of normalized input during update period TU = , where N is the number of samples in TU and n is the feedback gain. The average value of output during update period TU =.
In Delta-Sigma Modulator with feedback gain n,
Where is said to be normalized input. If the feedback gain is unity, equation (1.1) can be rewritten as,
The difference equations which governs the first-order DSM is given by,
z transform of equation (1.3) gives,
where z-1 is the signal transfer function (STF) and (1-z-1) is the noise transfer function (NTF). From NTF it can be obtained that for time varying signal, the power of quantization noise is proportional to, where f is the normalized frequency ( fB / fS). The signal bandwidth is fB and the sampling frequency is fS which is the clock frequency fC. In the signal band, f << 1 since fS >> fB. The NTF shows high-pass response, which suppresses the quantization noise at and near dc (in the signal band) and amplifies it out of band, at and near fS/2.
The average values of x(i) and y(i) can be obtained by putting z=1 in equation (1.4). If the average value of e is finite, Y(1) = X(1) i.e. the average value of the digital output during certain period TU is equal to the average value of the sampled analog input signal during TU. For dc input since X(1) is constant, if the circuit operates for sufficiently long time, the average value of the digital output will be good approximation of the input.
Constant and rational input, results in periodic output i.e. the output bit pattern (-1 or +1) repeats after certain period. It follows that if the input is constant but not rational, the output is not periodic. The periodic sequences generated by rational dc inputs are called pattern noise or limit cycles. The amplitude of limit cycles does not change with time but is a complicated function of input. The frequency of limit cycle also depends upon the amplitude of input. This limit cycle generates in-band noise which is maximum near simple rational values such as x = 0, ï‚±1/2, ï‚±1/3, etc. (Richard Schreier, Gabor C. Temes (2005).
The first order modulator is stable as long as the input signalï‚£1 for both constant and time varying input signals. The performance of first order modulator in terms of resolution, idle-tone generation (pattern noise) and signal to quantization noise ratio (SQNR) is inadequate for most applications. For simplicity the symbol SNR is used instead of SQNR. The second order modulator overcomes the above disadvantages at the expense of reduction in the input signal range and otherwise resulting in instability (Richard Schreier, Gabor C. Temes (2005) and Norsworthy S.R., Schreier R. and Gabor C. Temes (1997)).
1.1.2 Conventional Second-Order DSM
The conventional discrete second order DSM (n=1) in which the sampling of input signal and DSM operation is performed by single clock signal with period TC is shown in Fig.1.2. The unit D is the delay unit of one clock period (TC). In Fig.1.2, x(i), x1(i), x2(i) and y(i) represent the ith sample of input signal, first integrator output, second integrator output and quantizer output respectively. The quantization error signal during ith sampling period is denoted as e(i).
Figure 1.2 Conventional Second-Order DSM
The difference equation governing the second-order DSM, is given by,
y(i) = x(i) + e(i) -2e(i-1) +e(i-2) (1.5)
Taking z transform of equation (1.5) gives,
where STF is unity and NTF is (1-z-1)2. For time varying input signal, the power of quantization noise is proportional to. The SNR of second-order DSM is satisfactory when the input signal ranges from -0.4 to +0.4. Outside this range the SNR falls rapidly. Instability occurs when the absolute amplitude of input signal exceeds 0.55. Under this situation, due to the non linear nature of the quantizer and also due to signal dynamics in the feed back system, the input to the quantizer increases rapidly even if the input signal is withdrawn. The modulator output does not alter between -1 and +1 as it does when the modulator is properly functioning (Richard Schreier, Gabor C. Temes (2005) and Norsworthy S.R., Schreier R. and Gabor C. Temes (1997)).
From equation (1.6), one can say that for dc input, if the circuit operates for sufficiently long time, the average value of the digital output will be good approximation of the input as in the case of first-order DSM. The in-band quantization noise signal is very low for dc signal when compared with first-order DSM. The modulus of input dc signal can be increased to 0.7 without making the DSM unstable.
1.2 Previous Works to Improve Stability and Limitations
Dunn C and Sandler M. (1994) proposed to reset the integrators to improve stability. Resetting the integrators is faster to recover from instability but it is worse in terms of SNR in the unstable input range. Stikvoort E.F.(1988) proposed to clip the integrators at some predetermined level. Clipping the integrators has good SNR but is slow in recovering. Activating local feedback loops around the integrators leads to excellent speed of recovery and SNR but needs very complex circuitry (Au S. and Leung B. (1997) and Moussavi S. and Leung B. (1994)). The method of reducing the order of the loop filter yields better SNR than the method of clipping the integrators and is very fast in recovery from overload but needs complex circuitry. (Pneumatikakis A.,Constantinides A., Bourdopoulos G. and Deliyannis T. (1999) and George I.Bourdopoulos (2004)). Chapter 2 includes the latest stabilization techniques
(Maghari N., Kwon S., Temes G.C. and Moon U. (2006), Maghari N., Kwon S., Temes G. C., and Moon U. (2007) and Maghari N., Temes G.C. and Moon U.(2008)).
1.3 Switching Converters
In switching converters (SCs), the average dc output voltage must be controlled to a desired level and is proportional to the switching control signal. SCs use one or more switches to transform dc from one level to another. In a SC, with the given supply voltage, the average output voltage is controlled by controlling the on and off durations of a switch. The property that the DSM output can directly drive the bridge type SC is made use in proposed SC. In SCs, energy is received from dc sources, such as batteries or overhead trolley wires. This is useful in battery driven vehicles, particularly forklift trucks, cranes and in traction systems.
In dc motor speed control application, SCs are mainly used for the speed control of dc series motors because the field inductance of the series motor helps to maintain constant armature current during the off period. It can also be used for the speed control of separately excited dc motors but an additional inductance is to be incorporated in series with the armature (Sen P.C (2001)).
1.3.1 Conventional DSM Based SC and Its Limitations
Number of applications in industrial electronics uses conventional DSM. One such application in power electronics is conventional DSM based SC which is used to control the speed of dc motor. The range of output signal of the SC with conventional DSM is very much limited at different over sampling ratio due to poor SNR and unstable condition.
SC with the conventional second order DSM cannot be used for the full range of normalized input signal (-1 to +1). The DSM becomes unstable when the modulus of input signal is above 0.55. The output of second integrator saturates the operational amplifier which is used as comparator in the quantizer and hence, the SC becomes unstable. When the modulus of input signal is above 0.4, the in-band noise signal increases and SNR falls (Glen Luckjiff and Ian Dobson (2005))
1.4 Identification of Area of Work
The first configuration of proposed SC is shown in Fig.1.3. The proposed SC
Figure 1.3 First Configuration of Proposed SC
consists of control circuit and power circuit. The control circuit, which is the proposed DSM, is the first part of area of work of this thesis. The control signal is single analog input signal. The output of the control circuit is pulsating dc signal. The average value of the pulsating dc signal during the update period TU is equal to the average value of the control signal during period TU. The output of the power circuit is also pulsating dc but with high voltage (for example ï‚±48 V) and high current rating. The pulsating dc through running average filter is applied to the armature of single-phase or three-phase dc motor and the speed can be controlled in both the directions. This configuration is applied in forklift trucks, cranes, traction systems etc.
The second configuration of proposed SC is shown in Fig.1.4. The control circuit of second configuration is the proposed multiplier which is the second part of area of work of this thesis. The proposed multiplier multiplies two (or more) analog input signals and gives pulsating dc (digital) at the output. The remaining working of the circuit is same as in configuration I. In this configuration, the control signals are multiple analog signals and the speed of the dc motor is needed to be controlled proportional to the product of the analog signals. Some of these signals are control voltage from the operator, load cell voltage, motor temperature sensor voltage, voltage from the end limit switches etc. The control signal can also be a digital signal. Both configurations are functioning for the full range of input signal in stable condition with better SNR and spectral response when compared to conventional SCs.
Figure 1.4 Second Configuration of Proposed SC
The main objectives of the present thesis are;
(i) to propose stable, wide input range DSM for single input signal which should be capable of driving single-phase/ three-phase bridge type power circuit efficiently (maximum range of output with minimum error signal, better SNR and spectral response).
(ii) to propose stable, wide input range DSM based multiplier which can multiply two (or more) analog signals and give digital output and should be capable of driving single/three-phase bridge type power circuit efficiently.
(iii) to propose vector quantizer which when used with proposed DSM or with proposed multiplier gives the three phase output proportional to the input signal or product of the input signals respectively.
1.5 Control Signals in Industries
The industrial control signal has low frequency varying from 0 to 5 kHz. This facilitates the sampling of input signal and DSM operation at two different clock frequencies TU and TC such that TU >> TC. In this situation, the DSM is operating on dc signal and so the in-band quantization noise signal is less. The output from the SC can be used to control the speed of a dc motor which is a low bandwidth application.
1.6 Proposed Modules
In this thesis, four Delta-Sigma Modulator (DSM) configurations, three multiplier configurations and a vector quantizer are proposed. These proposed modules are used to develop single phase/three phase switching converters (SCs) with single-input/multiple-inputs. The performance of SCs with proposed modules is better than the existing SCs.
1.6.1 Proposed DSMs
In the conventional second order DSM, the sampling of input signal and DSM operation is performed at the same frequency. A higher order DSM is basically an unstable system. The approximate conditions for stability cannot be used for the design of a DSM for industrial applications where risk is involved. The conventional discrete DSM with unity or non unity feedback gain (n), cannot be used for the full range (-n to +n) of time varying input signal since the DSM becomes unstable when the modulus of input signal is above 0.55n.
In this thesis, a second order DSM in which the sampling frequency of input signal and DSM clock frequency are different, is proposed as the first configuration (DSM1). The normalized input range of first configuration is limited to -0.7 to +0.7. The SNR is better than the conventional DSM. In the proposed second configuration (DSM2), the DSM is operated with input signal dependant feedback gain and input signal dependant DSM operating period. The sample of input signal which is fed to DSM, the sample of input signal in the feedback and the sample of input signal which controls the operating period of DSM are all samples of input signal with sampling period TU whereas the DSM operating clock period is TC. The selection of TU is much larger than TC. DSM2 can operate for a full range of normalized input signal and with better SNR without causing instability. The oscillation at the output of DSM for zero input is no longer present. In the output spectrum near the signal frequency, the noise level is well below the signal level. The PSD is comparable with the conventional DSM and hence DSM2 is suitable for applications in power electronics. The third configuration (DSM3) is the combination of the first two configurations (DSM1 and DSM2). When the modulus of normalized input signal is in the range of 0 to 0.7, DSM1 operates and when it is above 0.7, DSM2 operates. DSM3 gives better SNR in the lower range compared to DSM2. The construction of DSM4 is similar to DSM2. The sample of input signal in the feedback and the sample of input signal which controls the operating period of DSM are the samples of input signal with sampling period TU whereas sampling of input signal and DSM operation is performed by the clock with period TC. The performance of DSM4 is comparable with DSM2. The SCs with proposed DSMs (DSM2, DSM3 and DSM4) can function for the full range of normalized input signal (-1 to +1) and are stable.
The proposed DSMs (DSM2, DSM3 and DSM4) can operate for the full range of input signal without causing instability and SNR never falls continuously after certain amplitude of the input signal. In the adaptive order reduction technique, which is proposed by George I. Bourdopoulos (2004) and also in the technique of clipping the output of integrators which is proposed by Stikvoort E.F. (1988), the SNR falls after -5.5 dB (numerical value 0.53).
1.6.2 Proposed Multiplier Configuration 1(MUL1)
In MUL1, a new technique is proposed for multiplication of two sampled analog signals and the result is in digital form. The analog signals that are to be multiplied are fed to the inputs of two different second order DSM1s after sampling at different sampling rates. The operating clock periods of the two DSM1s are also different. The output of the DSM1 which is operating at higher clock frequency is inverted or not inverted depending on the bit state at the output of low frequency DSM1. The resulting bit stream at the output of DSM1 which is operating at high frequency is the digital representation of the product of the two analog signals.
1.6.3 Proposed Multiplier Configuration 2 (MUL2)
In MUL2, a new technique which is better than that used for MUL1 is proposed for multiplication of two sampled analog signals and the output is in digital form. One analog signal is fed to the input of first DSM1 after sampling. The sampled output of the second analog signal is negated or not negated depending on the bit state at the output of first DSM1 and is fed to the input of second DSM1. The resulting bit stream at the output of second DSM1 is the digital representation of the product of the two analog signals. For considered low frequency analog signals with normalized amplitudes ranging from -0.7V to +0.7V, the maximum absolute value of error signal in the proposed multiplier is 0.03% of full scale of supply voltage (FS) when the sampling period of analog signals is 0.01sec. and the DSMs operating clock period is 0.1μsec.
1.6.4 Proposed Multiplier Configuration 3 (MUL 3)
In MUL3, a new technique which is better than that used for MUL2 is proposed for multiplication of two sampled low frequency analog signals and the result is in digital form. Out of the two signals, first signal is fed to the input of DSM1. The operating period of the DSM1 circuit is varied directly in proportion to the absolute amplitude of the second analog signal. In this case, the average value of the digital output of quantizer is equal to the product of normalized samples of analog signals in each sampling period. For considered two low frequency analog signals with normalized amplitude of first signal ranging from -0.7 to +0.7 and normalized amplitude of second signal ranging from -1 to +1, the maximum absolute value of the error signal in the proposed multiplier is 0.26mV (0.026%) when the sampling period of analog signals is 0.01sec. and the DSM circuit operating clock period is 0.1μsec. whereas the reported minimum error in the conventional multipliers is 0.05%. (Zhangcai Huang, Yasuaki Inoue, Hong Yu and Quan Zhang (2006)).
1.6.5 Proposed Vector Quantizer (VQ)
Conventional DSM with hexagonal quantization results in significant improvement in spectral performance and SNR. But the range of input signal cannot be extended to full scale (Glen Luckjiff and Ian Dobson (2003)). In the case of scalar single bit quantizer the quantizer input, xq is quantized to +1 for any positive value or zero. The quantizer input is quantized to -1 for negative values. The idea of scalar quantization is extended to vector quantization. The proposed vector quantizer is shown in Fig.1.5. The circle of radius (xq)max is divided into six equal sectors. The vector falling in any sector is represented by the representative vector in each sector. Each representative vector bisects the corresponding sector and the magnitude is 1. The vector quantizer gives three-phase output which drives conventional half-bridge three-phase power circuit.
1.7.1 Single-Input Single-Phase SC with Proposed DSM
The SC with conventional second order DSM cannot be used for full range (-1 to +1) of input signals. The DSM becomes unstable when the modulus of input signal is above 0.55. The SC with proposed DSM3 can operate for the full range of input signal without causing unstable situation. The upper bounds of the integrator outputs never increase abruptly. The range of converter output voltage is increased by 45% ((1-0.55)-100).
1.7.2 Two-Inputs (or Multiple-Inputs) Single-Phase SC with Proposed MUL3
The proposed two inputs (or multiple inputs) single phase SC consists of MUL3 (or combination of MUL2 and a portion of MUL2) and single-bit scalar quantizer. The single phase SC when driven by considered two low frequency input signals, the absolute maximum value of the error signal is 20mV (0.04%) at the converter output with supply voltage ï‚± 48V.
1.7.3 Single-Input Three-Phase SC with Proposed DSM and Proposed VQ
The three-phase SC with conventional DSM and with hexagonal quantizer, which is proposed by Glen Luckjiff and Ian Dobson (2005), improves the SNR and also the spectral response but not the range of the input signal. In the proposed three-phase SC (with Proposed DSM and Proposed VQ), the input signal can be increased to full scale and is stable. The SNR is better than the conventional DSM based three-phase SC with hexagonal quantizer. The overall maximum percentage of difference in phase voltages is 6mV at the output of vector quantizer, for the considered example.
1.7.4 Two-Inputs Three-Phase SC with Proposed MUL3 and Proposed VQ
In this SC, the control circuit consists of MUL3 and proposed VQ. The three-phase SC when driven by two low frequency input signals, the overall maximum difference in phase voltages is 18mV for the considered example.
1.8 Organization of Thesis
Chapter 1 gives the introduction of proposed modules and the application of modules in developing 1Ð¤, 3Ð¤ SCs.
Chapter 2 describes the works on the state-of-the-art. The limitations on the existing works are brought out.
Chapter 3 describes the details on proposed four configurations of DSM, proposed three configurations of multiplier and proposed vector quantizer. This chapter also explains how these modules are used to develop single-input single- phase SC, multiple-inputs single-phase SC, single-input three-phase SC and multiple- inputs three-phase SC using the proposed modules.
Chapter 4 gives the MATLAB simulated outputs of proposed DSMs, proposed multipliers and proposed single/three phase SCs with single/multiple input signals.
Chapter 5 gives the overall conclusion, projecting the advantages of proposed modules and proposed SCs, compared with conventional ones and the state-of-the-art references.