# Addition of binary numbers

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### INTRODUCTION

The process known as serial addition of binary numbers is well known in the computing and units capable of performing such serial binary addition ordinarily comprise a basic portion of more complex computation devices. In the past, such serial adders for binary numbers have employed vacuum tube circuitry for the most part and have accordingly been subject to the disadvantages that they are relatively in large size, fragile in configuration and are subject to operating failures. These factors raise serious questions of disposition of components and problems of maintenance. The present invention serves to obviate the foregoing difficulties and in essence provides a serial adder structure capable of performing full addition of binary numbers. It is accordingly an object of the present invention to provide an improved serial adder for use in computing applications.

An object of the present invention resides in the provision of an improved serial adder for binary digital applications employing magnetic amplifiers as components thereof. Another object of the present invention is the provision of the serial adder for binary numbers which adders can be made in relatively smaller sizes. A still further object of the present invention resides in the provision of a computation device comprising, in combination, a plurality of magnetic amplifiers and a plurality of gating devices so interconnected with one another that the mathematical process known as a serial bit addition. The binary adder of the present invention includes provision for selective coupling the input train pulses to be added as well as carry pulses produced by the device itself to the plurality of gates, and the gates are adapted by themselves to selectively pass signal pulses required for the operation or inhibition of the plurality of magnetic amplifiers mentioned above. In digital systems, digital signal processing and control systems we can control it when we are able to count. Addition is the fundamental operation for all these systems.

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The fastness and accuracy are highly influenced by the adders we are use for the circuit design. Adders are very important components in the digital components because of their extensive use in digital operations such as multiplication, subtraction and division. The execution of binary operations inside a circuit would be greatly advanced by improving the performance of the digital adders. The main aim of designing the bit serial adder is to

Perform one bit at a time, using the first bit operation results to influence the processing of subsequent bits. It reduces the amount of hardware required as it passes all the bits in the same logic. However this approach needs 1/nth part of hardware when compared to the n-bit parallel adders. As we are using 1-bit instead of n-bits its structure reduces the signal routing and performs at high speed as we are using 1bit register for the temporary storage and one full adder rather than an n-bit adder. The reduction in the price of the logic results in taking n clock cycles to execute this serial hardware, whereas parallel hardware executes in one clock cycle. This bit structure deals with the bit stream hence this have been successfully used in many applications like digital systems, digital signal processing, control systems etc. It was extremely popular in 2-5u technology range. The performance of a digital circuit block is gauged by analysing its power dissipation, layout area and its operating speed.

### BACKGROUND

### CMOS (COMPLEMENTARY METAL OXIDE SEMI-CONDUCTOR)

CMOS is also a type of semiconductor that holds data without any type of external source. CMOS plays an important role in the designing of logic gates by using transistors. In PMOS the switch is on if the input value is ‘0'. Here switch means transistor. And in NMOS if the input value is ‘1' then the transistor is on in other case it is in off state. The PMOS and NMOS transistors can be represented as follows.

CMOS is a transistor circuit that can be formed by the combined implementation of PMOS and NMOS transistors.

By using basics of transistors, the simple NOR gate can be designed as shown in the below figure. This figure gives us how this NOR gate works for different inputs which are usually ‘1' and ‘0'. As shown in the figure VDD is source voltage or logic ‘1' and GND is the ground or logic ‘0'

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From the above figures it shows the logic gates implementation using transistors. For the implementation of remaining logic gates we should first analyse the behaviour of transistors when connected in series and parallel.

Connection of NMOS in series will be as shown in the figure.

Connecting PMOS in series will be as shown in the figure.

Next we will see the behaviour of NMOS and PMOS when connected in parallel.

Connection of NMOS transistors in parallel

Connection of NMOS transistors in parallel

If the NMOS transistors are connected serially then the current will flows when both the input values are ‘1'. If both the inputs are not ‘1' then the output will be undefined. In the case of parallel connection the current flows if any of the inputs are ‘1'. That means both the inputs need not to be ‘1'. And the output is undefined in all the other cases.

For PMOS connected in series the current will flow when both the input values are ‘0'.otherwise the output is undefined. In the case of parallel connection the current will flow if anyone of the inputs is ‘0'.

### LOGIC GATES

We need to spend some time in discussion of combinational logic, which is the part of sequential logic most of the time. It is well known that logic decisions can be made with the help of universal gates are NAND, NOR. These gates will generate the output depending on the input values. Here are the logic gates we are discussing below.

### NOT GATE

NOT gate is used for many design applications. It outputs exactly opposite to the input signal hence it is also known as inverter. Its symbol is as represented below.

Alternative symbol for not gate is as shown below

Its truth table is as shown below

input |
Output |

0 |
1 |

1 |
0 |

### AND GATE

In this gate the output will be high if and only if all the inputs are high i.e. both the inputs must be 1.The output will becomes low i.e.0 if any one of the inputs are 0.The two input and gate symbol will be represented as shown below.

Input A

Input B Output

### TWO INPUT AND GATE

A two input AND gate truth table looks like this

A |
B |
OUTPUT |

0 |
0 |
0 |

0 |
1 |
0 |

1 |
0 |
0 |

1 |
1 |
1 |

### OR GATE

Our next gate is or gate. In this the output is high when any one of the inputs are in high state i.e. 1.And the output is low when both the inputs are low i.e. 0.Its symbol is as shown in the figure below.

And its truth table is as shown below.

A |
B |
OUTPUT |

0 |
0 |
0 |

0 |
1 |
1 |

1 |
0 |
1 |

1 |
1 |
1 |

### NOR GATE

NOR gate is also an orgate.But the difference is its output is inverted. Its symbol is represented as shown below.

The output of NOR gate is exactly opposite to the OR gate as shown below.

By this truth table we can know that the output will be high when both the input values are low i.e. 0.

Negative-AND

This gate works just like AND gate but with all its inputs connected to NOT gate. It's logical behaviour is not similar to NAND gate but its truth table is similar to NOR gate.

Its truth table is as represented below.

A |
B |
OUTPUT |

0 |
0 |
1 |

0 |
1 |
0 |

1 |
0 |
0 |

1 |
1 |
0 |

Negative-OR gate

This gate also similar to OR gate but with all inputs connected to the NOT gate. The truth table and behaviour of negative-OR is similar to the NAND gate truth table.

Its truth table is as shown below.

A |
B |
OUTPUT |

0 |
0 |
1 |

0 |
1 |
1 |

1 |
0 |
1 |

1 |
1 |
0 |

### XOR GATE

In XOR gate the output is high when both the inputs are at different logic levels i.e. 1 and 0 or 0 and 1.and is low when both the inputs are 0 or both the inputs are 1.its symbol is as shown below.

Its truth table is as shown below.

A |
B |
OUTPUT |

0 |
0 |
0 |

0 |
1 |
1 |

1 |
0 |
1 |

1 |
1 |
0 |

### XNOR GATE

It is exactly opposite to the XOR gate .In XNOR gate the output is high only when both the inputs are ‘0' and both the inputs are ‘1' conversely the output is low when two inputs are both 0 and 1 or either 1 and 0.its symbol is represented as shown below.

The truth table of XNOR gate is as shown below

A |
B |
OUTPUT |

0 |
0 |
0 |

0 |
1 |
1 |

1 |
0 |
1 |

1 |
1 |
0 |

### NAND GATE

NAND gate was constructed by inverting the AND gate that means adding NOT gate to the output of AND gate. This gate is also known as universal gate.

Its truth table is as shown below

A |
B |
OUTPUT |

0 |
0 |
1 |

0 |
1 |
1 |

1 |
0 |
1 |

1 |
1 |
0 |

### TRANSMISSION GATE

Sometimes we need to disconnect the logic gates output from common node in order to allow another gate to drive the node. This can be possible only by using the transmission gate. This action prevents the driving conflicts of these nodes. The transmission gate is as shown in the below figure.

### IN OUT

C

As shown in the above figure transmission gate have one signal input, one control input and one output. Its operation principle is as follows. The output follows the signal input if logic one is applied to the controlled input and the output goes to high impedance state in the case of logic zero, where the input signal is disconnected from the output. This can be used in data switching and multiplexer applications. CMOS transmission gate is as shown in the below figure.

CMOS transmission gate operation is as follows. MNO and MPO are cut-off if the value of C is ‘0'. The operation state of CMOS transmission gate is high. The output follows the input signal and MNO and MPO are linear if C is equal to VDD. Only two MOSFETs are required for the construction of transmission gate.

### CHAPTER 1

### BASIC ADDER UNIT

Addition of two binary numbers is the most basic arithmetic operation i.e. two bits. A combinational circuit which can add only two bits is known as half adder. A full adder is one that adds more than two bits i.e. three bits. Full adder uses two adders in its implementation. In this study full adder is the basic addition employed in all adders.

### HALF ADDER

Half is a basic adder circuit that can perform addition of two bits and gives the output of sum and carry. Half adder circuit uses an Exclusive-OR and AND gates for sum and carry outputs. XOR gate gives the sum output and carry output is given by the AND gate. X and Y are inputs S is sum and C0 is carry.

S = X.Y' + X'.Y = X Å Y

C = X.Y

Its schematic representation is as shown in the figure.

The truth table of half adder is as shown below.

X |
Y |
SUM |
C0 |

0 |
0 |
0 |
0 |

0 |
1 |
1 |
0 |

1 |
0 |
1 |
0 |

1 |
1 |
0 |
1 |

K-MAPPING of half adder circuit is given as shown below.

Sum, S = X Å Y

Carry, C0 = X.Y

FULL-ADDER

Full adder can be formed by combining two half-adder circuits followed by the OR gate. It can perform the addition of three bits along with the carry input given as output from the previous one. The difference between half adder and full adder is that half adder cannot count more than two bits and cannot add the carry input which will be possible in full adder circuit. In this circuit, sum output is given by the XOR gate and the carry output is given by the AND gate followed by the OR gate. The block diagram of full adder circuit is as shown below.

### FULLADDER

Sum S = X Å Y Å CI = (X Å Y) Å CI

Carry C0 = (X .Y) + (X Å Y).CI

As shown in the above figure X, Y and CI are the adder inputs.

The truth table of the above circuit is as shown below.

## X |
## Y |
## CI |
## SUM |
## C0 |

0 |
0 |
0 |
0 |
0 |

0 |
0 |
1 |
1 |
0 |

0 |
1 |
0 |
1 |
0 |

0 |
1 |
1 |
0 |
1 |

1 |
0 |
0 |
1 |
0 |

1 |
0 |
1 |
0 |
1 |

1 |
1 |
0 |
0 |
1 |

1 |
1 |
1 |
1 |
1 |

By using K-mapping we will get SUM and CARRY as follows

Sum S,

Carry c0,

### SERIAL ADDER

The process known as serial addition of binary numbers is well known in the digital and units capable of performing such serial binary addition ordinarily comprise a basic portion of more complex computation devices. In the past, such serial adders for binary numbers have employed vacuum tube circuitry for the most part and have accordingly been subject to the disadvantages that they are relatively in large size, fragile in configuration and are subject to operating failures. These factors raise serious questions of disposition of components and problems of maintenance. The present invention serves to obviate the foregoing difficulties and in essence provides a serial adder structure capable of performing full addition of binary numbers. It is accordingly an object of the present invention to provide an improved serial adder for use in digital systems.

The main aim of designing the bit serial adder is to perform one bit at a time, using the first bit operation results to influence the processing of subsequent bits. Here in this case the one bit serial adder is designed by using a D-flip flop and full adder. .

This circuit has two stages full adder stage for the addition of two bits that are entered serially and second stage is D-flip flop stage which temporarily stores the carry until the next stage is processed. The temporary storage of the carry in the D-flip flop depends on the clock pulse. Its design principle shows how the two inputs entered serially. These two inputs will be added by the full adder along with the carry which was temporarily stored by the flip-flop and gives us the sum output and carry output. This is a practical serial adder that is used to add a

stream of two bits addition. First it takes the Least Significant Bits (LSB) in addition. Its block diagram is as shown in the figure.

As shown in the above figure the inputs Xi and Yi are serially entered into the full adder along with the temporary carry from the D-flip flop i.e. Ci and gives the carry output Ci+1 and sum output Si.

Hence serial adder is simple and because of feedback looping bit delays are expected. It can be constructed with very low cost and it is the perfect adder at low speed operations.

Si = Ci Å Yi Å Xi

Ci + 1 = Yi . Ci + Xi . Ci + Xi . Yi = Ci . (Xi Å Yi) + Xi . Yi

The above equations represent the Sum and Carry outputs using Boolean equations.

The construction of 1-bit serial adder is as shown in the figure. As shown in the figure the inputs X and Y are serially entered through the full adder along with the carry input which was the feedback output of full adder. In this circuit, sum output is given by the XOR gate and the carry output is given by the AND gate followed by the OR gate. D- Flip flop used in this circuit acts as a temporary storage of carry.

This entire design process and simulation can be done by using the mentor graphics version 2005 software.

### D - FLIP FLOP

D- Flip flop is used in many applications. RS flip flop is the fundamental building block for the D- flip flop. It has only one data input. That is connected to the input S of RS flip flop where as D is inversely connected to the R input.. D- Flip flop is also having second input for holding the data which is known as Enable, simply represented as EN. The enable input is AND-ed with the D- Flip flop. D- Flip flop holds the data according to the clock pulse.

It is constructed by using AND gates and NOR gates as shown in the below figure. D and EN are the inputs and Q and Q' are outputs. The block diagram of the D-flip flop is as shown below.

D- Flip flop acts as temporary data storage in the 1- bit serial adder. Its storage capacity depends on the number of stages. The storage capacity of the D- flip flop in this serial adder is the total number bits (0 and 1) of digital data it can retain.

Its truth table is a shown below.

D |
EN |
Q |
QN |

0 |
Falling edge |
0 |
X |

0 |
Rising edge |
0 |
1 |

1 |
Falling edge |
Qprev |
X |

1 |
Rising edge |
1 |
0 |

Here i have taken only one input Q because of using only one input pin of the D-flip flop in serial adder.

The wave forms are attached in the results.

### XOR GATE USING NAND GATES

In PMOS holes flow very slowly when compared to the electrons in the NMOS technology. Hence NMOS is faster than PMOS transistor. In NOR gate PMOS transistors are connected in series and in NAND gate PMOS transistors are connected in parallel hence NAND gate is faster than the NOR gate. Now considering another case to make this one bit serial adder little bit faster compared to the normal one bit serial adder the XOR gate is constructed by using the NAND gates which works faster than the normal XOR gate. The reason for constructing this XOR gate is that in the core library we are using to design the entire circuit XOR gate internally contains an OR gate which usually reduces the performance of XOR gate. Its circuit diagram is as follows.

Its truth table is as shown below.

## X |
## Y |
## OUT |

0 |
0 |
0 |

0 |
1 |
1 |

1 |
0 |
1 |

1 |
1 |
0 |