Adaptive Algorithm For Noise Cancelling In Speech Signal Computer Science Essay

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Abstract- For long years the Signal processing field was dominated by dedicated Programmable Digital Signal Processors (PDSPs). In recent years FPGA systems are replacing PDSP systems due to their greater flexibility and higher bandwidth, resulting from their parallel architecture. This paper presents the applicability of a FPGA system for speech processing. Here adaptive filtering technique is used for noise cancellation in speech signal. Least Mean Squares (LMS ) , one of the widely used algorithm in many signal processing environment , is implemented for adaption of the filter coefficients. The cancellation system is first implemented in Matlab and tested for noise cancellation in speech signal. The simulation of VHDL design of adaptive filter is performed. Its implementation on SPARTAN - 3 FPGA board is done.

Keywords- Adaptive filter, Least Mean Squares Algorithm, noise cancellation, VHDL Design, FPGA implementation


In recent years , acoustic noises become more evident due to wide spread use of industrial equipments. An active noise cancellation (ANC) is a technique that effectively attenuates low frequencies unwanted noise where as passive methods are either ineffective or tends to be very expensive or bulky. An ANC system is based on a destructive interference of an anti-noise, which have equal amplitude and opposite phase replica of primary unwanted noise. Following the superposition principle, the result is cancellation of both noises.

Adaptive filter is widely used as Active noise canceller. ANC systems are distinguished by their different goals that lead to different architectures. If all ambient sound shall be reduced, a

feedback system with its simpler architecture may be used. If, as in our case, single sources of unwanted sound shall be compensated, a feedforward system is required. A feedforward system is characterised by two audio inputs per channel: one reference signal input for the sound to be removed, and one error input for the sound after the compensation . As in figure 1 , ANC system consist of an input sensor, ANC controller, cancelling source and error sensor. The input sensor is used to measure the unwanted noise at a location away from the error sensor and provide the input to ANC controller i.e. Adaptive filter. The error sensor measures the residual acoustic field that is used to adjust the adaptive filter coefficients.

Figure 1. Basic concept of ANC

An adaptive FIR feedforward system has to be designed for the selective cancellation of disturbing noise without affecting other sounds due to the fact that these filters are always stable and robust against parameter variations. (see fig 2) . The primary signal d(n) consists of the superposition of noise signal s(n) and the wanted signal n(n). The reference signal x(n) is noise signal measured at the noise source. The system output signal y(n) is an estimate of the noise signal with inverted sign. In the headphones this signal and the primary signal are superposed, so that the noise signal is cancelled. The error signal e(n) is the result of this superposition. If the adaptive filter does properly model the transmission path from the noise source to the error microphone, the contribution of the noise signal to the error signal is minimised. This goal is achieved by minimising the mean square of the error signal (MSE adaption) The widely used LMS algorithm is used for the FIR filtering and for the adaption of the filter coefficients.

Figure 2. Feedforward Adaptive Filter Structure

Mathematical treatment for FIR Adaptive Filter

In order to determine an optimal set of filter parameters w for the minimisation of the error signal, we consider the filter output y(n) of a filter of order M-1 for the sample index n.

y (n) = wT (n) u (n) (1)

where u(n) is the vector of the M most recent input samples at

sampling point n,

u(n) = [ u(n),u(n-1),…… u(n-M+1)] (2)

and w(n) is the tap-weight vector of filter coefficients.

w(n) = [w0(n), w1(n),……. wM-1(n)] (3)

The error signal is given by comparing this output with The primary signal d(n), we get estimation error

e (n) = d(n) - y(n)     (4)

Substituting y(n) with the right-hand side of eq. (1) yields

e (n) = d(n) - ŵ (n) u (n) (5)

and for the squared error we get

e 2(n) = d2(n) - 2 d(n)u T(n) w(n) + wT (n) u(n) uT(n) w(n) (5)

The method require the use of a gradient vector, whose value depends on two parameters R & P

VJ (n) = -2 P + 2R w (n)     (6)


R is the autocorrelation matrix of u(n), and P is the cross correlation matrix of d(n) and u(n).

The instantaneous estimates for R and P respectively

Rˆ (n) = u (n) u H (n)               (7)


                             Pˆ (n) = u (n) d* (n)  (8)

Minimising the expectation value of e2 in eq. (5) under the assumption of a stationary and zero-mean reference signal u(n) finally leads to the Wiener-Hopf equation

Wopt = R-1 P (9)

This is the Condition for Optimal FIR Parameters.

B. LMS Adaption Algorithm

The Wiener-Hopf equation (9) is not directly suitable for real-time embedded applications, because R and p are neither known in advance, nor are they time-invariant. In addition, the inversion of R is time-consuming for higher filter orders. The Widrow-Hoff least mean-squares (LMS) algorithm [15] provides a means of calculating wopt without the need of knowing R and P, and without performing a matrix inversion. In this algorithm the target function for the minimisation is the running average of the squared error signal (e2) instead of the expectation value E{e2}. In an iterative way the next FIR coefficient set w(M+1) is computed from the values at step n. A factor µ is introduced to control the step width of the iteration and thus the speed of convergence of the algorithm.

Stability bound on µ of LMS algorithm

0 < µ < (2/(M x Smax)) (10)

where, Smax is the max. value of Power Spectral Density of tap inputs and M is Filter length.

A new recursive relation for updating the tap weight vector is given by

w (n+1) = w (n) + μ ∆ e 2(n) (11)

with equation (4) we get

w (n+1) = w (n) + 2 μ u (n) e(n)  (12)

FPGA Implementation of ANC System

System Block Diagram

Figure 3 shows the block diagram of the ANC system. The system components are a FPGA board Spartan 3 FPGA XC3S400, connected to a stereo audio codec board Philips UCB 1400 , a condenser microphone AKG C3000B as reference microphone, an in-ear microphone Soundman OKM-II professional as error microphone, an Audio interface Motu 828 MKII, Sennheiser HD 600 headphones. The audio measurements were performed with a dummy head measurement system HEAD HMS II.4.

The in-ear microphone and the headphone were applied to the

dummy head as shown in figure 7. Measurements were made by recording the audio signal of the dummy head microphones, which are located at the end of the ear canal.

The noise signal x is recorded with the reference microphone,

which is connected via the Motu-interface to the left stereo input of the stereo audio codec board UCB 1400. Here it is digitized with fS = 48kHz sampling rate and routed with a serial protocol to the Spartan FPGA board.

The right stereo channel of the audio codec board is connected via the Motu-interface to the error microphone, an in-ear microphone, that records the result of the cancellation, i.e. the error signal e. This signal is utilised for the adaption of the FIR filter coefficients. The output of the adaptive filter y is fed to the headphone via the audio codec board and the Motu

Figure 3. Block diagram of the ANC system with measured group delays in the signal path. The secondary path is marked with thick lines


Our FPGA board offers only one interface to an audio codec

board, so only two audio signals could be processed simultaneously, hence the noise cancellation could only be performed for one ear.

VHDL Design

The VHDL model is structured as a processor element with a

data path and a control path. The data path represents a processing pipeline, and the control path handles the data transformations between the single stages of the pipeline.

Implementation of the Adaptive FIR Filter and LMS Algorithm

Fig. 5 shows the components of the adaptive filter. The constituent parts of the data path are the two serial MAC units for the adaption algorithm (MAC_LMS) and for the FIR algorithm (MAC_FIR), the RAM unit for storage of the current filter coefficients, and the audio samples. The control path functionality is implemented in the state machine FSM_LMS_FIR and its connecting signals.

Arithmetic is modeled with Q format number representation which provides for each pipeline stage an appropriate number of guard bits for representing the integer part and avoiding overflow effects.

The next sections describe the design of the FIR filter, the

adaption process and the finite state machine of the control path.

1.1) The FIR filter

The FIR filter design is based on the transposed direct form in

order to keep the maximum data path length short, since this is the limiting factor for the system clock frequency. Figure 5 shows, that for the direct form the maximum data path contains 1 multiplier and N adders, whereas the maximum data path for the transposed direct form contains only one multiplier and one adder regardless of the filter order.

Finally the filter is implemented as a sequential MAC unit

which performs N+1 accumulations of products during every sample period so that a resource sharing can be utilised: since the audio sample period fS provides a large amount of available clock cycles per audio sample, no parallel structure with N +1 multipliers and N adders is necessary.

Figure 4. FIR filter structures. The maximum data path length is indicated by the thick lines. Top: direct form. Bottom: direct form transposed

Figure 5. RT L Model of the adaptive filter

The updated input samples read from the filter RAM block (RAM_SAMP_FILT) are multiplied with their corresponding filter coefficient taken from the dual-ported RAM block DP_RAM_COEFF and stored in the accumulator. The filter output signal is fed to the saturation block SAT, which prevents the filter output from overflow and inverts the sign of the output signal to provide the phase shift for the compensation step.

1.2) LMS Algorithm for FIR Coefficient Adaption

The MAC_LMS entity stores the FIR coefficients to the dual port RAM DP_RAM_COEFF. The coefficient adjustment XEMUE is calculated by a product of the delayed input sample SAMP_LMS and the weighted error signal EN*MUE. A register is inserted to this path that splits the arithmetic chain for achieving a shorter signal delay so that a clock frequency of fCLK = 50MHz can be met.

The dual port RAM is chosen to support a parallel processing of the coefficient update and the MAC unit of the FIR filter. With two address inputs the reading address of the coefficients and the address for writing back the updated coefficients can be incremented within two interleaved clock periods.

1.3) The FSM of the Control Path

The finite state machine FSM_LMS_FIR in the upper left part of figure 4 controls the processing of the two parallel pipelined data paths. The state diagram of the FSM shown in figure 6 describes a sequence which is started with each new input sample pair EN (error signal) and XN (reference signal). In particular, the main controlled steps are the storage of a new sample of the reference signal XN, the calculation of the product of error signal EN and step size factor MUE, the alternating sequence of reading and writing the coefficients with parallel enabling the accumulator register REG_Y of the entity MAC_FIR. The last two states STOP and UPDATE provide the transfer of the accumulation result Y to the saturation module, which holds this value for one sample period and performs the adjustment of the RAM address counters for the next sequence.

Figure 6. State diagram of the FSM of the adaptive filter


The ANC system is first implemented in Matlab7.04. The evaluation of the measurement data was performed with Matlab.

Xilinx Simulator was used for the hardware simulation of the VHDL design of the adaptive FIR filter and the interface to the audio codec. VHDL synthesis and FPGA configuration was done with the Xilinx ISE development environment.

simulation and Results

The parameters of clean speech sample considered for testing of the algorithms were: duration 2 seconds, PCM 22.050 kHz, 8 bit mono sample recorded under laboratory conditions.

Figure 7 : Original speech signal

The filter order was fixed at 12 for all cases of noise cancellation in speech .The recorded sentence "A quick brown fox jumps over the lazy dog" was used as the clean speech. This sentence is conventionally used as a benchmark for speech processing. The above sentence contains all the alphabets of the English language. Hence the variability of effect of noise on speech with frequency of the signal is accounted. The original speech signal is shown in Fig. 7.

Noise was generated and added to the original speech signal. The SNR of the signal corrupted with noise was 7.776 dB. A linear combination of the generated noise and the original signal is used as the primary input for the filter. Fig. 8 shows the original speech corrupted by white noise.

Figure 8 : speech signal corrupted by white noise

The denoised speech signal using the is shown in Fig. 9. The output Signal to noise ratio of the signal denoised was 28.5101 dB.

Fig. 9 :Denoised signal

Figure 10 : Frequency Response of denoised signal

Table 1 shows the output signal to noise ratio of the denoised speech signal

Table 1. Output SNR

Sr. No

Signal Type

Output SNR in dB


The signal corrupted



The signal denoised



The measurements of the previous section proved, that the FPGA platform is well suited for the complex real time audio processing tasks in augmented reality audio systems. An adaptive noise cancellation process has successfully been implemented. Filter orders of 256 and above can be realized with the Spartan -3 FPGA XC3S400 board.

Measurements with real-life audio signals have been carried out to investigate the performance of the system. The limiting factors have been identified and will be overcome in the further



I have a great pleasure in submitting this Paper "FPGA Implementation of Adaptive Algorithm for Noise Cancelling in Speech signal", which was in the partial fulfillment of the requirements of the M.E. course in electronics engineering, Dr. BAMU, Aurangabad.

I take this opportunity to express profound gratitude to Prof. Mrs. S. S. Ardhapurkar (Project guide) for their valuable guidance and helpful attitude.

I would also like to thank all the teaching staff members of our stream and our college for their support.

I sincere thanks to all those who knowingly and unknowingly have contributed in their own way in completion of this seminar.