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A Binary lock is a digital implementation of a key that is used to control access to a device. This can be achieved by associating any number of bits to guarantee the access. In real life example such as the ATM or the door lock, the key consists of 10 bit binary input (0-9) which gives 210 different code combinations to choose from. The input of the lock code in these cases is entered in serial form bit by bit. In this project, a 4 Bit Binary lock system is implemented and tested. The lock consists of 4 data input switches that are connected to a comparator that is used to compare the 4 Binary inputs to the lock key stored in the device's memory. A D-flip flop was connected to the output of the comparator to indicate whether the lock is open or locked. The circuit includes a counter that feeds from the output signal of the comparator, so that the user can try three times only. After that, the "Trials Exceeded" and "Lock" signals turn on. The design also includes a reset switch that is used to reset the value of the counter to zero to provide the ability of resetting the device manually. The device was implemented using basic IC chips such as comparator, counter, D flip-flop and logic gates to construct the full design.
2.0 Circuit Implementation:
For the design of the 4 bit lock key, the team used six IC chips in addition to the LEDs and resistors. Table 1, shows the IC chips used in this circuit.
In this design, four bit equal comparator is used to compare the user's input to the switches to the key value stored in the device's memory. The comparator gives a high output voltage if they were equal. According to the equal comparator K-map (Appendix A), the equation of the circuit will be:
By obtaining this equation the comparator circuit can be built using OR, AND, Not or any other gates required. However, the IC chip used has additional inputs to activate the "less than", "equal" and "bigger than" modes (Appendix B).
Figure 1: Comparator pin code schematicFigure 1 shows the pin code for the comparator. The chip gives the output according to two factors. First factor is the activated mode. The designer chooses the mode by activating one of the pins 2, 3 or 4. The second factor is the inputs. This gate has two types of input "A" and "B" inputs. The gate compares the inputs and gives the output at the node related to the mode activated. The output is taken from the pins 5, 6 or 7 according to the mode chosen.
In the case of this design, the activated mode is the "Equal mode" at pin 3. Therefore, the output is taken from pin 6. The "A" inputs are connected to the memory where the correct sequence is saved, and the "B" inputs are connected to switches. If a user chooses the correct sequence, high voltage will be presented to pin 6, otherwise a low voltage will be presented to the same pin.
2.2 D - flip flop:
The D flip-flop is used in the design to distinguish the lock and open state for the lock. The output of the comparator is connected to the input D of the flip flop. When the output of the comparator is low, the output of the D flip-flop will follow input resulting in low voltage at the Q terminal. So, the complement output will be high. Table 2 shows the D flip-flop truth table.
Figure 2: D-flip flop pin code schematic Figure 2 shows the D flip-flop pin code for the IC chip used provided in the data sheet (Appendix C). The chip gives the outputs according to the truth table shown above (Table 2). The inputs are supplied to pins 1, 2 and 4 while the outputs are taken from the pins 5 and 6. The clock signal is supplied to pin 3.
In our design, D flip-flop was used where the clear and preset inputs are both set to high, so the output of the flip-flop will only depend on the D input. The output for the lock signal is taken from the complement of the flip flop output at pin 6, so when D is low, the output is high. The output of the open signal is taken from pin 5, in order to give a high signal only when the input D is high.
The counter is used in this design to count the number of the wrong entries for each user. According to the counter datasheet (Appendix D), the counter is built using 4 D flip-flop with a common clock input. Figure 3 shows the schematic diagram of the counter.
Figure 3: The schematic Block diagram of the 4 Bit synchronous counter
As shown in Table 4, In order for the counter to count the trial all inputs should be high. However, to hold the value of the output the inputs SR' and PE' should be high and at least one of the two other inputs should be low. To reset the counter the input SR' should be low. To load the data in at the inputs A, B, C and D the SR' input should be high and the PE' input should be low.
Table 4: Pin code for the IC chip used and its operating modes
Figure 4: Counter pin schematicIn the design the load mode is not used because the counter is only used for counting and does not require any additional inputs. The pins 3, 4, 5 and 6 are grounded in order to not have them floating. The comparator output is supplied to CET and PE' inputs through an inverter (I1), to insure they will always be high as long as the input of the inverter is low. An additional switch is supplied to an inverter (I2) and then to an AND gate with the output of (I1). This will ensure that the SR' signal will be low only if the switch was turned on or the comparator output is high. To hold the counter output after the third wrong input the counter outputs Q0 and Q1 are connected through a NAND gate to the CEP input of the counter. This will make the input low when the counter counts the third entry 0011.
2.4 NAND gate
The NAND gate is used to give low signal when its inputs are both high. The K-map and equation for the NAND gate is as following:
Figure 5: NAND gate chip pin schematicFigure 5 shows the pin code for the IC chip used provided in the data sheet (Appendix E). The input is supplied to pins 1 and 2 while the output is taken from pin 3. In our design NAND gate is used to send a low signal to the counter CEP input when the counter counts to three. This low signal will set the counter into the hold mode.
2.5 NOT gate
The not gate has only one input and its function is to invert this input. Therefore, its truth table is as following:
Figure 6: NOT gate chip pin schematic Figure 6 shows the pin code for the IC chip used provided in the data sheet (Appendix F). This IC chip has six inverters. The inputs are supplied to pins 1, 3, 5, 9, 11 or 13, while the output is taken from the pins 2, 4, 6, 8 10 or 12. In our design two inverters are used, one is to invert the output of the comparator before it goes to the CET and PE' inputs of the counter to ensure they will always be high as long as the correct entry is not applied. The other one is connected between an additional switch and an AND gate, to give the ability of resetting the device manually.
2.6 AND gate
The AND gate is used to give high signal when its inputs are both high. The K-map for the AND gate is as following:
Figure 7 shows the pin code for the IC chip used provided in the data sheet (Appendix G). The input is supplied to pins 1 and 2 while the output is taken from pin 3. In our design the AND gate is used to send a high signal to the trials exceeded output when the counter counts to three. This high signal indicated that the user inserted the wrong code three times in a row.
The first stage in this circuit is the comparator. The "A" inputs of the comparator is connected to the memory where the sequence is saved. When the user enters the correct sequence the output at pin 6 of the comparator will be high. This high voltage is supplied to the input of the input of the D flip-flop and the inverter (I2). The output of the inverter in this case is low which goes through an AND gate to the SR' signal to reset the counter. However, the output of the D flip-flop will not change until the user presses the pulse generator which represent the enter key. This pulse generator gives a pulse to the clock of the D flip-flop and the counter.
In the case of a wrong entry the output of the comparator at pin 6 will be low. After pressing the pulse generator the counter will count the try because all of its control inputs are supplied high voltage. After the third wrong entry the counter outputs Q0 and Q1 will both be 1. Connecting them to an AND gate will give a high voltage at the output of the AND gate which represents the trials exceeded signal. Also, the same outputs will be supplied through a NAND gate to the counter CEP input to supply a low voltage at that pin. This will let the counter holds this signal and never change it. Additional switch is available in order to be able to reset the counter manually if desired.
In conclusion, this project included the design and physical implementation of a 4 bit Binary lock key that can be used as a control for the access to a digital system such as ATM machines or as a simple lock for a door. One of the challenges faced in this design was the synchronization of the pulse timings in different IC chips. The first proposed solution was to attach a 555 timer that would synchronize the clocks together but it was found to be ineffective. A de-bounce switch was used to provide the pulse required to activate the clock signals in the D-flip flop and the Counter. Based on the counter designed function, a user is allowed to try up to 3 wrong inputs, after that the "Trials Exceeded" and "Lock" signals will switch on permanently. This signal can be used to activate an alarm or prevent the user from inserting another entry.