An Essay About Spread Spectrum Communications Essay

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INTRODUCTION

Spread spectrum is a technique whereby an already modulated signal is modulated a second time in such a way as to produce a waveform, which interferes in a barley noticeable way with any other signal operating in a same frequency band. Thus, a receiver tuned to receive a specific AM or FM broadcast would probably not notice a presence of a spread spectrum signal operating over the same frequency band. Similarly, the receiver of the spread spectrum would not notice the presence of the AM or FM signal. Thus, we say that interfering signals are transparent to spread spectrum signals and spread spectrum signals are transparent to interfering signals.

To provide the “transparency” described above the spread spectrum technique is to modulate an already modulated waveform, either using amplitude modulation or wideband frequency modulation, so as to produce a very wideband signal. For example, an ordinary AM signal utilizes a bandwidth of 10KHz. Consider that a spread spectrum signal is operating at the same carrier frequency as the AM signal and has the same power P, as the AM signal but a bandwidth of 1 MHz. Then, in the 10 KHz bandwidth of the AM signal, the power of the second signal is Ps x (104/106) = Ps/100. Since the AM signal has a power of Ps, the interfering spread spectrum signal provides noise, which is 20 dB below the AM signal. The widest application at this time is its use in military communications systems where spread spectrum serves two functions. The first is that it allows a transmitter to transmit a message to a receiver without the message being detected by a receiver for which it is not intended i.e. the transmitter is transparent to an unfriendly receiver. To achieve this transparency the spread spectrum modulation decreases the transmitted power spectral density so that it lies well below the thermal noise level of any unfriendly receiver. The second major application of spread spectrum is found, when, as a matter of fact, it turns out not to be possible to conceal the transmission. Police radars can employ spread spectrum to avoid detection by radar detector employed by drivers. In such a case the operator of an unfriendly receiver might attempt to begin transmitting an interfacing signal to block communication between transmitter and receiver. Here again spread spectrum act to reduce the effective power of the interference so that communication can process with minimal interference.

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In the commercial communication field, spread spectrum has many applications, a major application being the transmission of a spread spectrum signal on the same carrier frequency as an already existing microwave signal. By communicating in the manner additional signal can be transmitted over the same band thereby increasing number of user. In additional, spread spectrum is used in satellite communication and is being considered for use in local area networks.

The object of our project is to Design & Implement a “Digital Speech Security System” (DSSS) which can provide protection against externally generated interfering (jamming) signals with finite power. The jamming signal may consist of fairly powerful broadband noise or multitude waveform that is detected at the receiver for the purpose of disrupting communications. Protection against jamming waveforms is provided by purposely making the information - bearing signal occupy a bandwidth necessary to transmit it. This has the effect of making the transmitted signal assume a noise like appearance so as to blend into the background. The transmitted signal is thus enabled to propagate through the channel undetected by any one who may be listening.

The additional security to speech can be provided by inverting two bits at transmitter as well as at receiver station. Conventionally, speech can be protected from unauthorized interception or eavesdropping by analog techniques using scramblers. There are time, frequency and bandwidth scramblers in diplomatic use.

In a Digital Speech Security System (DSSS), the analog signal is converted into Pulse Code Modulated (PCM) digital signal from using an analog-to-digital converter. This digital signal is combined directly with the output from a pseudo-random noise (PN sequence) generator to obtain an encrypted speech before transmission. This technique is known as direct sequence spread spectrum technique. Such a system has property that for the interceptor, the received message appears like noise & thus prevents him from eavesdropping. However, the desired party can decipher the message with local replica of the pseudo-random noise (PN sequence) available with him.

Pulse code modulation

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Pulse code modulation (PCM) was developed by AT & T in 1937 at their Paris laboratories Alex H. PCM is the preferred method of communication within the public switched telephone network. Pulse code modulation is the only one of the digitally encoded modulation techniques shown in Figure 2.1 that is used for digital transmission.

With PCM, the pulses are of fixed length and fixed amplitude. PCM is a binary system where a pulse or lack of a pulse within a prescribed time slot represents either a logic 1 or logic 0 condition. PWM, PPM, and PAM are digital but seldom binary, as pulse does not represent a single binary digit (bit).

Figure 2.2 shows a simplified block diagram of a single- channel, simplex (one way only) PCM system. The bandpass filter limits the frequency of the input analog signal to the standard voice - band frequency range of 300 Hz to 3000Hz. The sample and hold circuit periodically samples the analog input signal and convert those samples to a multilevel PAM signal. The analog - to digital converter (ADC) converts the PAM samples to parallel PCM codes, which are converted to serial data in the parallel- to-serial converter then outputted onto the transmission line. The transmission line repeaters periodically regenerate the PCM codes.

In the receiver, the serial-to-parallel converter converts serial data from the transmission line to parallel PCM codes. The digital-to-analog converter (DAC) converts the parallel PCM code to multilevel PAM signals. The hold circuit and low pass filter convert the PAM signal back to its original analog form.

Figure 2.2 also shows several clocks and samples pulses. An integrated circuit that performs the PCM encoding and decoding function is called a codec (coder/decoder).

2.1 PCM Sampling:

The function of a sampling circuit in a PCM transmitter is to periodically sample the continually changing analog input signal and convert those samples to a series of pulses that can more easily be converted to binary PCM code. For ADC to accurately convert a signal to a binary code, the signal must be relatively constant. If not, before the ADC can complete the conversion, the input would change and the ADC would be continually attempting to follow the analog changes and may never stabilize on any PCM code.

There are two basic techniques used to perform the sample and hold function: natural and flat-top sampling. Natural sampling is shown in Figure 2.3. Natural sampling is when the tops of the sampled analog waveform retain their natural shape. In Figure 2.3(a), the FET analog switch simply grounds the input waveform when the sample pulse is high. When the sample pulse is low, however, the input signal is allowed to pass unaltered through the output amplifier to the input of the analog-to-digital converter. The waveform for a naturally sampled signal resembles a series of equally spaced pulses with rounded tops, as shown in Figure 2.3(b).

With natural sampling, the frequency spectrum of the sampled output is different from that of an ideal sample. The amplitude of the frequency components produced from narrow, finite-width pulses decreases for the higher harmonics in a (sin x)/x manner. This alters the information frequency spectrum requiring the use of frequency equalizers (compensation filters) before recovery by a low-pass filter.

The most common method used for sampling voice signals in PCM systems is flattop sampling, which is accomplished in a sample-and-hold circuit. The purpose of a sample-and-hold circuit is to periodically sample the continually changing analog input signal and convert those samples to a series of constants-amplitude PAM levels. Flat-top sampling alters the frequency spectrum and introduces an error called aperture error, which prevents the recovery circuit in the PCM receiver from exactly reproducing the original analog signal. The magnitude of error depends on how much the analog signal changes while the sample I being taken.

The schematic diagram of a sample-and-hold circuit. The FET acts as a simple analog switch. When turned ON, Q1 provides a low-impedance path to deposit the analog sample voltage across capacitor C1. The time that Q1 is ON is known as aperture or acquisition time. Essentially, C1 is the hold circuit. When Q1 is OFF, C1 dose not have a complete path to discharge through and, therefore, stores the sampled voltages. The storage time of the capacitor is called the A/D conversion time, because it is during this time that the ADC converts the sample voltage to a PCM code. The acquisition time should be very short to ensure that a minimum change occurs in the analog signal while it is being deposited across C1. If the input to the ADC is changing while it is performing the conversion, aperture distortion results. Thus, by having a short aperture time and keeping the input to the ADC respectively constant, the sample-and-hold circuit can reduce aperture distortion. Flat-top sampling introduces less aperture distortion than natural sampling and requires a slower analog-to-digital converter.

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Figure 2.4(b) shows the input analog signal, the sampling pulse, and the waveform developed across C1. It is important that the output impedance of voltage follower Z1 and the on resistance of Q1 be as small as possible. This ensures that the RC charging time constant of the capacitor is kept very short, allowing the capacitor to charge or discharge rapidly during the short acquisition time. The rapid drop in the capacitor voltage immediately following each sample pulse is due to the redistribution of the charge across C1. The interelectrode capacitance between the gate and drain of the FET is placed in series with C1 when the FET is off, thus acting as a capacitive voltage divider network. Also, note the gradual discharge across the capacitor during the conversion time. This is called droop and is caused by the capacitor discharging through its own leakage resistance and the input impedance of voltage follower Z2. Therefore, it is important that the input impedance of Z2 and the leakage resistance of C1 be as high as possible. Essentially, voltage followers Z1 and Z2 isolate the sample-and-hold circuit (Q1 and C1) from the input and output circuitry.

2.2 Sampling Rate:

The Nyquist sampling theorem establishes the minimum sampling rate (fs) that can be used for a given PCM system. For a sample to be reproduced accurately at the receiver, each cycle of the analog input signal (fa) must be sampled at least twice. Consequently, the minimum sampling rate is equal to twice the highest audio input frequency. If fs is less than two times fa , distortion will result. The distortion is called aliasing or foldover distortion. Mathematically, minimum Nyquist sample rate is fs ≥ 2fa

where fs = minimum Nyquist sample rate (Hertz)

fa = highest frequency to be sampled (Hertz)

Essentially, a sample-and-hold circuit is an AM modulator. The switch is a nonlinear device that has two inputs: the sampling pulse and the input analog signal. Consequently, nonlinear mixing (heterodyning) occurs between these two signals. Figure 2.5(a) shows the frequency-domain representation of the output spectrum from a sample-and-hold circuit. The output includes the two original inputs (the audio and the fundamental frequency of the sampling pulse), their sum and difference frequencies (fs ± fa), all the harmonics of fs and fa (2fs , 2fa ,3fs ,3fa , etc ), their associated cross products (2fs ± fa , 3fs ± fa , etc.).

Because the sampling pulse is a repetative waveform, it is made up of a series of harmonically related sine waves. Each of these sine waves

is amplitude modulated by the analog signal and produces sum and difference frequencies symmetrical around each of the harmonics of fs . Each sum and difference frequency generated is separated is special from its respective centre frequency by fa . As long as fs is atleast twice fa , none of the side frequencies from one harmonic will spill into the sidebands of another harmonic and aliasing does not occur. Figure 2.5(b) shows the results when an analog input frequency greater than fs /2 modulates fs . The side frequencies from one harmonic fold over into the sideband of another harmonic. The frequency that folds over is an alias of the input signal (hence, the names "aliasing” or “foldover distortion"). If an alias side frequency from the first harmonics folds over into the audio spectrum, it can be removed through filtering or any other techniques.

The input bandpass filter shown in Figure 2.2 is called an antialiasing or antifoldover filter. Its upper cutoff frequency is chosen such that no frequency greater than one-half of the sampling rate is allowed to enter the sample and hold circuit, thus eliminating the possibility of foldover distortion occurring.

With PCM, the analog input signal is sampled, then converted to a serial binary code. The binary code is transmitted to the receiver, where it is converted back to the original analog signal. The binary codes used for PCM are n-bits codes, where n may be any positive integer greater than 1. The codes currently used for PCM are sign-magnitude codes, where the most significant bit (MSB) is the sign bit and the remaining bits are used for magnitude. Table-2.1 shows an n-bit PCM code where n equals 3. The most significant bit is used to represent the sign of the sample (logic1=positive and logic 0=negative). The two remaining bits represent the magnitude. With two magnitude bits, there are four codes possible for positive numbers and four codes possible for negative numbers. Consequently, there is a total of eight possible codes (23=8).

2.3 Folded Binary Code:

The PCM code shown in Table 2.1 is called a folded binary code. Except for the sign bit, the codes on the bottom half of the table are a mirror image of the codes on the top half. (If the negative codes were folded over on the top of the positive codes, they would match perfectly.) Also, with folded binary there are two codes assigned to zero volts: 100(+0) and 000(-0). For this example, the magnitude of the minimum step size is 1V. Therefore, the maximum voltage that may be encoded with this scheme is +3V (111) or -3V (011). If the magnitude of a sample exceeds the highest quantization interval, overload distortion (also called peak limiting) occurs. Assigning PCM codes to absolute magnitudes is called quantizing. The magnitude of the minimum step size is called resolution, which is equal in magnitude to the voltage of the least significant bit (Vlsb or the magnitude of the minimum step size of the ADC). The resolution is the minimum voltage other than 0V that can be decoded by the DAC at the receiver. The smaller the magnitude of the minimum step size, the better (smaller) the resolution and the more accurately the quantization interval will resemble the analog sample.

In Table 2.1, each three-bit code has a range of input voltages that will be converted to that code. For example, any voltage between +0.5 and +1.5 will be converted to the code 101. Any voltage between +1.5 and +2.5 will be encoded as 110. Each code has a quantization range equal to + or - one-half the resolution except the codes for +0V and -0V. The 0-V codes each have an input range equal to only one-half the resolution, but because there are two 0-Vcodes, the range for 0V is also + or - one-half the resolution. Consequently, the maximum input voltage to the system is equal to the voltage of the highest magnitude code plus one-half of the voltage of the least significant bit.

Figure 2.6 shows an analog input signal, the sampling pulse, the corresponding PAM signal, and the PCM code. The analog signal is sampled three times. The first sample occurs at t1 when the analog voltage is exactly +2V. The PCM code that corresponds to sample 1 is 110. Sample 2 occurs at time t2 when the analog voltage is -1V. The corresponding PCM code is 001. To determine the PCM code for a particular sample, simply divide the voltage of the sample by the resolution, convert it to an n-bit binary code, and add the sign bit to it. For sample 1, the sign bit is 1, indicating a positive voltage. The magnitude code (10) corresponds to a binary 2. Two times 1V equals 2V, the magnitude of the sample.

  1. Linear transfer function;
  2. Quantization; (c) Qe

Sample 3 occurs at time t3. The voltage at this time is approximately +2.6V. The folded PCM code for +2.6V is 2.6 /1 = 2.6. There is no code for this magnitude. If successive approximation ADCs are used, the magnitude of the sample is rounded off to the nearest valid code (111 or +3V for this example). This results in an error when the code is converted back to analog by the DAC at the receiver end. This error is called quantization error (Qe). The quantization error is equivalent to the additive white noise (it alters the signal amplitude). Similar to noise, the quantization error may add or subtract from the actual signal. Consequently, quantization error is called quantization noise (Qn) and its maximum magnitude is one-half the voltage of the minimum step size (Vlsb /2). For this example, Qe = V/2 or 0.5V.

The input-versus-output transfer function for a linear analog-to-digital converter (sometimes called a linear quantizer). As the figure shows for a linear analog input signal (i.e., a ramp), the quantized signal is a staircase. Thus, as shown in Figure 2.7(c), the maximum quantization error is the same for any magnitude input signal.

the same analog input signal used in Figure2.8 being sampled at a faster rate. As the figure shows, reducing the time between samples (increasing the sample rate) produces a PAM signal that more closely resembles the original analog input signal. However, it should also be noted that increasing the sample rate does not reduce the quantization error of the samples.

2.4 Coding Efficiency:

Coding efficiency is a numerical indication of how a PCM code is utilized. Coding efficiency is the ratio of the minimum number of bits required to achieve a certain dynamic range to the actual number of PCM bits used. Mathematically, coding efficiency is

2.5 Signal to quantization noise ratio:

The three bit PCM coding scheme described in the preceding section is a linear code. That is, the magnitude between any two successive codes is the same. Consequently, the magnitude of their quantization error is also the same. The maximum quantization noise is the voltage of the least significant bit is divided by 2. Therefore, the worst possible signal voltage-to-quantization noise voltage ratio (SQR) occurs when the input signal is at its minimum amplitude (101 or 001). Mathematically, the worst case voltage SQR is

For a maximum amplitude input signal of 3 V (either 111 or 011), the maximum quantization noise is also the voltage of the least significant bit divided by 2. Therefore, the voltage SQR for a maximum input signal condition is

From the preceding example it can be seen that even though the magnitude of error remains constant throughout the entire PCM code, the percentage of error does not; it decreases as the magnitude or the input signal increases. As a result, the SQR is not constant.

The preceding expression for SQR is for voltage and presumes the maximum quantization error and a constant amplitude analog signal; therefore it is of little practical use and is shown only for comparison purposes. In reality and as shown in Figure 2.6, the difference between the PAM waveform and the analog input waveform varies in magnitude. Therefore, the signal to quantization noise ratio is not constant. Generally, the quantization error or distortion caused by digitizing an analog sample is expressed as an average signal power to average noise power ratio. For linear PCM codes (all quantization intervals have equal magnitudes), the signal power to quantization noise power ratio (also called signal to distortion ratio or signal to noise ratio) is determined as follows:

where,

R = resistance (ohm)

v = rms signal voltage (volts)

q = quantization interval (volts)

v2/R = average signal power (watts)

If the resistances are assumed to be equal,

2.6 Coding Methods:

There are several coding methods used to quantize PAM signals into 2n levels. These methods are classified according to whether the coding operation proceeds a level at a time, a digit at a time, or a word at a time.

LEVEL-AT-A-TIME CODING:

This type of coding compares the PAM signal to a ramp waveform while a binary counter is being advanced at a uniform rate. When the ramp waveform equals or exceeds the PAM sample, the counter contains the PCM code. This type of coding requires a very fast clock if the number of bits in the PCM code is large. Level-at-a-time coding also requires that 2n sequential decisions be made for each PCM code generated. Therefore, level-at-a-time coding is generally limited to low speed application. Nonuniform coding is achieved by using a nonlinear function as the reference ramp.

DIGIT-AT-A-TIME CODING:

This type of coding determines each digit of the PCM code sequentially. Digit-at-a-time coding is analogous to a balance where known reference weights are used to determine an unknown weight. Digit-at-a-time coders provide a compromise between speed and complexity. One common kind of Digit-at-a-time-coder, called a feedback coder, uses a successive approximation register (SAR). With this type of coder, the entire PCM code word is determined simultaneously.

WORD-A-TIME CODING:

 Word-at-a-time coders are flash encoders and are more complex; however, they are more suitable for high-speed applications. One common type of word-at-a-time coder uses multiple threshold circuits. Logic circuit sensed by a PAM input signal and produce the approximate PCM code. This method is again impractical for large values of n.

SPREAD SPECTRUM

3.1 Definition of Spread Spectrum:

A transmission technique in which a pseudo-noise code, independent of the information data, is employed as a modulation waveform to “spread” the signal energy over a bandwidth much greater than the signal information bandwidth. At the receiver the signal is “despread” using a synchronized replica of the pseudo-noise code.

3.2 Basic Principle of Spread Spectrum System:

The Principal types of Spread Spectrum are Direct Sequence (DS), and Frequency Hopping (FH). An over view of these systems is hereby given:

pseudo shift of the phase pseudo shift of the frequency

coherent demodulation noncoherent

Direct Sequence Spread Spectrum (DSSS)

A pseudo-noise sequence pnt generated at the modulator, is used in conjunction with an M-ary PSK modulation to shift the phase of the PSK signal pseudo randomly, at the chipping rate Rc (=1/Tc) a rate that is integer multiple of the symbol rate Rs (=1/Ts).

The transmitted bandwidth is determined by the chip rate and by the base band filtering. The implementation limits the maximum chip rate Rc (clock rate) and thus the maximum spreading. The PSK modulation scheme requires a coherent demodulation.

PN code length that is much longer than a data symbol, so that a different chip pattern is associated with each symbol.

Frequency Hopping Spread Spectrum

A Pseudo-noise sequence pnt generated at the modulator is used in conjuction with an M-ary FSK modulation to shift the carrier frequency of the FSK signal pseudurandomly, at the hopping rate Rh. The transmitted signal occupies a number of frequencies in time, each for a period of time Th (= 1/Rh), referred as dwell time. FHSS divides the available bandwidth into N channels and hops between these channels according to the PN sequence. At each frequency hop time the PN generator feeds the frequency synthesizer a frequency word FW (a sequence of n chips) which dictates one of 2n frequency position fhl . Transmitter and receiver follows the same frequency hop pattern.

The transmitted bandwidth is determined by the lowest and highest hop position by the bandwidth per hop position (∆fch). For a given hop, instantaneous occupied bandwidth is the conventional M-FSK, which is typically much smaller than Wss. So the FHSS signal is a narrowband signal, all transmission power is concentrated on one channel. Averaged over many hops, the FH/M-FSK spectrum occupies the entire spread spectrum bandwidth. Because the bandwidth of an FHSS system only depends on the tuning range, it can be hopped over a much wider bandwidth than an DSSS system.

Since the hops generally result in phase discontinuity (depending on the particular implementation) a noncoherent demodulation is done at receiver. With slow hopping there are multiple data symbol per hop and with fast hopping there are multiple hops per data symbol.

3.3 Basic principle of Direct Sequence Spread Spectrum

For BPSK modulation the building blocks of a DSSS system are:

Input:

  • Binary data dt with symbol rate Rs = 1/Ts (=bitrate Rb for BPSK)
  • Pseudo-noise code pnt with chip rate Rc = 1/Tc (an integer of Rs)

Spreading:

In the transmitter, the binary data dt (for BPSK, I and Q for QPSK) is

‘directly' multiplied with the PN sequence pnt , which is independent of the binary data, to produce the transmitted baseband signal txb:

txb = dt . pnt

The effect of multiplication of dt with a PN sequence is to spread the baseband bandwidth Rs of dt to a baseband bandwidth of Rc.

Despreading:

The spread spectrum signal cannot be detected by a conventional narrowband receiver. In the receiver, the baseband signal rxb is multiplied with the PN sequence pnr .

  • If pnr = pnt and synchronized to the PN sequence in the received data, than the recovered binary data is produced on dr. The effect of multiplication of the spread spectrum signal rxb with the PN sequence pnt used in the transmitter is to despread the bandwidth of rxb to Rs .
  • If pnr ≠ pnt , than there is no dispreading action. The signal dr has a spread spectrum. A receiver not knowing the PN sequence of the transmitter can not reproduce the transmitted data.

3.4 Performance in the presence of interference:

To simplify the presence of interference, the spread spectrum system is considered for baseband BPSK communication (without filtering).

The received signal rxb of the transmitted signal txb plus an additive inteferance i (noise, other users, jammer,......):

rxb = t xb + i = dt . pnt + i

To recover the original data dt the received signal rx0 is multiplied with a locally generated PN sequence pnr that is an exact replica of that used in the transmitter (that is pnr = pnt and synchronized) The multiplier output is therefore given by:

dr = rxb . pnt = dt . pnt . pnt + i . pnt

The data signal dt is multiplied twice by the PN sequence pnt , where as the unwanted inteferance i is multiplied only once.

Due to the property of the PN sequence:

pnt + pnt = +1 for all t

The multiplier output becomes:

dr = dt + i . pnt

The data signal dr is reproduced at the multiplier output in the receiver, except for the inteferance represented by the additive term i . pnt . Multiplication of the inteferance by the locally generated PN sequence, means that the spreading code will affect the inteferance just as it did with the information bearing signal at the transmitter. Noise and inteferance, being uncorrelated with the PN sequence, becomes noise-like, increase in bandwidth and decrease in power density after the multiplier.

After dispreading, the data component dt is narrow band (Rb) whereas the inteferance component is wideband (Rc). By applying the dr signal to a baseband (low-pass) filter with a band width just large enough to accommodate the recovery of the data signal, most of the inteferance component i is filtered out. The effect of inteferance is reduced by processing gain (Gp).

Narrowband inteferance:

The narrowband noise is spread by the multiplication with the PN sequence pnr of the receiver. The power density of the noise is reduced with respect to the despread data signal. Only 1/Gp of the original noise power is left in the information baseband (Rs). Spreading and dispreading enables a bandwidth trade for processing gain against narrow band interfering signals. Narrow band inteferance would disable conventional narrow band receivers.

The essence behind the inteferance rejection capability of a spread spectrum system: the useful signal (data) gets multiplied twice by the PN sequence, but the inteferance signal get multiplied only once.

Wideband interference:

Multiplication of the received signal with the PN sequence of the receiver gets a selective despread of the data signal (smaller bandwidth, higher power density). The inteferance signal is uncorrelated with the PN sequence and is spread.

Origin of wideband noise:

  • Multiple Spread Spectrum user: multiple access mechanism.
  • Gaussian Noise: There is no increase in SNR with spread spectrum: The large channel bandwidth (Rc instead of Rs) increase the received noise power with Gp:

Ninfo = N0 . BWinfo à Nss = N0 . BWss = Ninfo .Gp

The spread spectrum signal has a lower power density than the directly transmitted signal.

3.5 Mutiple Access:

Code division multiple access (CDMA) is a methode of multiplexing (wireless) users distinct (orthogonal) codes. All users can transmit at the same time, and each is allocated the entire available frequency spectrum for transmission. CDMA is also known as Spread-Spectrum multiple access (SSMA).

CDMA dose not require the bandwidth allocation of FDMA, nor the time synchronization of the individual users needed in TDMA. A CDMA user has full time and full bandwidth available, but the quality of the communication decreases with an increasing number of users (BER ).

In CDMA each user:

  • Has it's own PN code
  • Uses the same RF bandwidth
  • Transmits simultaneously (asynchronous or synchronous)

Correlation of the received baseband spread spectrum signal rxb with the PN sequence of user 1 only despreads the signal of user 1. The other user produces noise Nu for user 1.

3.6 Jamming:

The goal of a jammer is to disturb the communication of his adversary. The goals of the communicator are to develop a jam- resistant communication system under the following assumptions:

  •  Complete invulnerability is not possible
  •  The jammer has a prior knowledge of most system parameters, frequency bands, timing, traffic, ......
  •  The jammer has no a prior knowledge of the PN spreading code

Protection against jamming waveforms is provided by purposely making the information-beating signal occupy a bandwidth far in excess of the minimum bandwidth necessary to transmit it. This has the effect of making the transmitted signal assume a noise-like appearance so as to blend into background.

The transmitted signal is thus enabled to propagate though the channel undetected by anyone who may be listening. Spread spectrum is a method of “camouflaging” the information-bearing signal.

3.6 Evaluation of SS:

Positive:

  • Signal hiding (lower power density, noise-like), non interference with conventional systems and other SS systems.
  • Secure communication (privacy)
  • Code Division Multiple Access CDMA (multi-user)
  • Mitigation (rejection) of multipath, hold only the direct path
  • Protection to intentional interference (Jamming)
  • Rejection of unintentional interference (narrowband)
  • Low probability of detection and interception (LPI)
  • Avability of licence-free ISM (Industrial, Scientific and Medical) frequency-bands.

Negative:

  • No improve in performance in the presence of Gaussian noise
  • Increased bandwidth (frequency usage, wideband receiver)
  • Increased complexity and computational load.

PRACTICAL IMPLIMENTATION

4.1 Design:

In this project, the operation & construction of DSSS is described. The block diagram of the scheme is shown in figure. The system is divided into two sections:

  • Transmitter
  • Receiver

Transmitter section has two parts, Pulse Code modulator (ADC) & Encryptor.

Receiver section also consists of two parts Decryptor & Pulse Code Demodulator (DAC).

4.2 Principle:

The voice input given to microphone is amplified by audio power amplifier and fed to ADC. The ADC used in construction provides 8-bit equivalent of sampled speech in parallel form. This is converted into serial bit stream using a Multiplexer. Modulo-2 adder is used to obtain the enciphered speech by adding the (PCM) signal with the output of Pseudo-random number generator. The encrypted signal is transferred to the receiver through wire. In Receiver, this signal is decrypted by using Modulo-2 adder, by adding this signal with the same PN sequence that is used at transmitter. Then, the decrypted signal is fed to pulse code modulator which performs speech demodulation. Then this signal is amplified and fed to speaker.

4.6 WORKING:

Transmitter Section

In first stage to convert the voice signal into electrical signal, we use the condenser mic.Condenser mic is a passive transducer so it requires opposite supply which is given by 3.3K resistor and then to couple the signals, with next stage, we use capacitor of 5.6Kpf. This stage is a band pass filter used to band limit the signal so that we can decide the sampling rate to convert the signal into digital form. In this stage, we have using one of four OP-AMPS (LM 324). Hence, this is an active filter. Bandwidth of this filter is chosen 400Hz to 3.4 KHz. We have decided the values of component for this stage by the formula for the first of the filter

Fc = 1/(4лRC)

In the next stage, we are using secondary OP-AMP of this IC, just as an amplifier. The output of this stage is coupled to next OP-AMP, to boost the current capacitor. Hence, we configure this stage as Buffer Amplifier. The output of this stage is the input for sample and hold stage to sample the data (signal), we use IC 4066 which is a quartz analog switch and to hold the value of this sample, we use 1.5Kpf capacitor. To protect the capacitor from discharging during conversion period, we use OP-AMP in Buffer mode because it provides the highest input impedance, so, capacitor holds the sampled value during conversion time for proper conversion. Then, the output of this stage is feeded to Analog to Digital Converter IC ADC 0804 which converts analog signal into 8-bit digital signal. To protect the ADC from high voltage, we use a zener diode of 5Vs at its input stage because the input coming from previous stage may reach a value greater than 5V.

Here, we are operating the ADC at 640 KHz frequency which is the optimum frequency of this IC. At this frequency, IC provides the conversion time of 100 microseconds. The 640 KHz frequency is decided by the resistor and capacitor connected with pin 19 and pin 4 of IC. The scaling factor of IC is decided by the voltage at pin 9 so that we can change the gain of ADC by changing biasing at pin 9. Now, to provide the start pulse to start conversion, we generate a check by dividing standard 1 MHz clock by 4-bit counters .The output of this stage generate a clock of about 8 KHz. Since IC requires a low to high transition, the start conversion, we invert the clock by using simple HEX-INVERTER 7404.

Now, this parallel data is converted into serial stream by 4051 Multiplexer. Because of data at parallel input must remain unchanged during parallel to serial conversion, we hold a data in a Latch 74574. The output of pin 3 of IC4051 gives the serial data. Now, to spread the spectrum, we multiply the data by sequence of 1's or 0's by using IC 4077 which is EX-NOR IC. Now, to call the code for multiplication, we use a clock of 1MHz. For mixing the outputs of multiple channels use the IC 4071. To generate a standard clock, we use IC 4060 which is an oscillator plus divider IC, so we can select the required clock by selecting proper crystal and proper dividing value by this IC. Here, we are using 4 MHz crystal which is used to generate 1 MHz frequency with the help of IC CD 4060.

Receiver Section

In receiver stage, the encoded signals are multiplied with 4077. Here, also, the same code sequences are multiplied in the same way as a transmitter side. Now, to avoid false detection, we average the signal by using simple RC integrator and IC 4093 which is a Schmitt trigger NAND gate. To avoid any error during serial to parallel conversion, we delay the shifting clock of shift register by small amount of time so it samples the available data at right position. Now, the parallel data is taken from shift register 4015 which is latched in IC 74574 for proper conversion into analog signal. To convert digital data into analog data, we use DAC 0800 which is simple shift D to A converter. The output of DAC contains the harmonic distortion because of quantization error; we smooth the signals by using simple passive Low Pass Filter and then, fed the signal for power amplification to power amplifier IC LM 386. Before feeding the signal into this IC, we use a variable register so that we can use adjust the volume of the speaker. Because DAC require dual supply to work, we use two separate transformers to generate the supply.

COMPONENT LIST:

1. Integrated Circuits:

S. No.

IC No.

Specification

Pin Configuration

Qty.

1.

LM 324

Quad Op-Amp IC

14 Pin DIP

2

2.

CD 4066

Quad Analog Switch

14 Pin DIP

2

3.

ADC0804

8-bit A to D Converter

20 Pin DIP

2

4.

7404

Hex Inverter

14 Pin DIP

1

5.

74574

8-bit D-Latch

20 Pin DIP

3

6.

CD 4051

8-Channel Analog Multiplexer

16 Pin DIP

5

7.

CD 4060

14-Stage Counter/ Divider/Oscillator

16 Pin DIP

1

8.

CD 4520

Dual Binary Counter

16 Pin DIP

1

9.

CD 4077

Quad EX-NOR Gate

14 Pin DIP

2

10.

CD 4071

Quad 2 input OR Gate

14 Pin DIP

1

11.

CD 4093

Quad 2 input NAND Schmitt Trigger

14 Pin DIP

1

12.

CD 4015

Dual 4 bit static Shift Register

16 Pin DIP

1

13.

DAC 0800

8-bit D to A Converter

16 Pin DIP

1

14.

LM 386

Low Voltage Audio Power Amplifier

8 Pin DIP

1

15.

7805

5V fixed regulated IC

3 Pin Flat Pack.

2

2. Resistors:

S.No.

Resistance Value

Specification

Qty

1.

3. 3 KΩ

¼ Watt

2

2.

470 KΩ

¼ Watt

2

3.

10 KΩ

¼ Watt

20

4.

6. 8 KΩ

¼ Watt

2

5.

10 MΩ

¼ Watt

2

6.

37 KΩ

¼ Watt

2

7.

4.7KΩ

¼ Watt

2

3. Preset (Variable Resistor):

S.No

Resistance Value

Qty

1.

2 KΩ

2

2.

50 KΩ

2

3.

20 KΩ

2

4.

10 KΩ

1

4. Capacitors:

S.No

Capacitance Value

Specification

Qty

1.

5.6 nF

Ceramic Capacitor

2

2.

4.7 nF

Ceramic Capacitor

2

3.

1 μf, 63 V

Electrolytic Capacitor

5

4.

1.5 nF

Ceramic Capacitor

2

5.

150 pF

Ceramic Capacitor

2

6.

15 pF

Ceramic Capacitor

1

7.

0.01 μF

Ceramic Capacitor

3

8.

0.1 μF

Ceramic Capacitor

2

9.

220 μF,10 V

Electrolytic Capacitor

1

10.

1000 μF, 16 V

Electrolytic Capacitor

3

5. Diodes:

S.No

Diode Name

Specification

Qty

1.

IN 4007

PN Junction diode

6

2.

Zener Diode

Provides 5V Regulation

2

6. Oscillators:

S.No

Oscillator Name

Specification

Qty

1.

Crystal Oscillator

Operating at 4 MHz

1

7. Transformer:

S.No

Transformer Value

Specification

Qty

1.

9-0-9, 500mA

Step Down Transformer

3

8. Microphone:

S.No

Microphone Name

Specification

Qty

1.

Condenser Mic.

Directivity- Omnidirectional

S/N Ratio - about 40 dB

Distortion - Low (1%)

O/p Impedance - High (100Ω)

2

9. Speaker:

S.No

Speaker Name

Specification

Qty

1.

Loudspeaker

8Ω, 50 W(Max.), 10W(Normal)

1

10. Switches:

S.No.

Switch Name

Qty.

1.

Push to ON Switch

24

11. Connecting Wires:

We have used ribbon wires.

P.C.B. CONSTRUCTION

It is an important process in the fabrication of electronic equipment. The design of PCBs (Printed Circuit Boards) depends on circuit requirements like noise immunity, working frequency and voltage levels etc. High power PCBs require a special design strategy.

The fabrication process to the printed circuit board will determine to a large extent the price and reliability to the equipment. A common target aimed is the fabrication of small series of highly reliable professional quality PCBs with low investment cost. The target becomes especially important for custom tailored equipment in the area of industrial electronics.

The layout of a PCB has to incorporate all the information of the board before one can go on the artwork preparation. This means that a concept, that clearly defined all the details of the circuit and partly also of the final equipment is prerequisite before the actual lay out can start. The detailed circuit diagram is very important for the layout designer but he must also be familiar with the design concept and with the philosophy behind the equipment.

6.1 BOARD TYPES:

The two most popular PCB types are:

1. Single Sided Boards

The single sided PCBs are mostly used in entertainment electronics where manufacturing costs have to be kept at a minimum. However in industrial electronics cost factors cannot be neglected and single sided boards should be used wherever a particular circuit can be accommodated on such boards.

2. Double Sided Boards

Double-sided PCBs can be made with or without plated through holes. The production of boards with plated through holes is fairly expensive. Therefore plated through holes boards are only chosen where the circuit complexities and density does not leave any other choice.

6.2 CHRONOLOGY:

The following steps have been followed in carrying out the project.

  • Study the books on the relevant topic.
  • Understand the working of the circuit.
  • Prepare the circuit diagram.
  • Prepare the list of components along with their specification. Estimate the cost and procure them after carrying out market survey.
  • Plan and prepare PCB for mounting all the components.
  • Fix the components on the PCB and solder them.
  • Test the circuit for the desired performance.
  • Trace and rectify faults if any.
  • Give good finish to the unit.
  • Prepare the project report.

6.3 DESIGN SPECIFICATION:

(A) PCB DESIGNING

The main purpose of printed circuit is in the routing of electric currents and signal through a thin copper layer that is bounded firmly to and insulating base material some time called the substrate. This base is manufactured with an integral bounded layer of thin copper foil which has to be partly etched of other wise remove to arrive at a pre designed pattern to suite the circuit connections or whatever other application is noted.

The term printed circuit board is derived from the original method where by a printed pattern is used as the mask over wanted areas of copper. The PCB provides an ideal baseboard upon which to assemble and hold firmly most of the small components.

From the constructor's point of view, the main attraction of using PCB is its role as the mechanical support for small components. There is less need for complicate and time consuming metal work of chassis contraception except perhaps in providing the final enclosure. Most straight forward circuit designs can be easily covered in to printed wiring layer the thought required to carry out the inversion cab footed high light an possible error that would otherwise be missed in conventional point to point wiring. The finished project is usually neater and truly a work of art.

Actual size PCB layout for the circuit shown is drawn on the copper board. The board is then immersed in FeCl3 solution for 12 hours. In this process only the exposed copper portion that is etched out by the solution.

Now the petrol washes out the paint. Now the copper layout on PCB is rubbed with a smooth sand paper slowly and lightly such that only the oxide layers over the Cu is removed. Now the holes are drilled at the respective places according to component layout as shown in figure.

(B) LAYOUT DESIGN:

When designing the layout one should observe the minimum size (component body length and weight). Before starting to design the layout we need all the required components in hand so that an accurate assessment of space can be made. Other space consideration might also include from case of mounted components over the printed circuit board or to access path to present components.

It might be necessary to turn some components round to a different angular position so that terminals are closer to the connections of the components. The scale can be checked be positioning the components on the squared paper. If any connection crosses, then one can reroute to avoid such condition.

All common or earth lines should ideally be connected to a common line routed around the perimeter of the layout. This will act as the ground plane. If possible try to route the outer supply line to the ground plane. If possible try to route the other supply lines around the opposite edge of the layout to through the center. The first set is tearing the circuit to eliminate the crossover with out altering the circuit detail in any way.

Plan the layout looking at the topside to this board. First this should be translated inverse later for the etching pattern large areas rate recommended to maintain good copper adhesive it is important to bear in mind always that copper track width must be according to the recommended minimum dimensions and allowance must be made for increased width where termination holes are needed. From this aspect, it can become little tricky to negotiate the route to connect small transistors.

There are basically two ways of copper interconnections pattern in the under side to the board. The first is the removal of only the amount of copper necessary to isolate the junction to the components to each other resulting in the large areas of copper. The second is to make the interconnection pattern looking more like conventional point wiring by routing uniform width of copper from component to component.

(C) ETCHING PROCESS:

Etching process requires the use of chemicals acid resistant dishes and running water supply. Ferric chloride is mostly used solution but other etching materials such as ammonium per sulphate can be used. Nitric acid can be used but in general it is not used due to poisonous fumes.

The pattern prepared is glued to the copper surface of the board using a latex type of adhesive that can be cubed after use. The pattern is laid firmly on the copper using a very sharp knife to cut round the pattern carefully to remove the paper corresponding to the required copper pattern areas. Then apply the resist solution, which can be a kind of ink proportion for the purpose of maintaining smooth clean outlines as far as possible. While the board is drying, test all the components.

Before going to next stage, check the whole pattern and cross check against the circuit diagram. Check for any free metal on the copper. The etching bath should be in a glass or enamel disc. If using crystal of ferric- chloride these should be thoroughly dissolved in water to the proportional suggested. There should be 0.5 lt. of water for 125 gm of crystal.

Waste liquid should be thoroughly deflated and dried in water land. Never pour down the drain. To prevent particles of copper hindering further etching, agitate the solutions carefully by gently twisting or rocking the tray.

The board should not be left in the bath a moment longer than is needed to remove just the right amount of copper. Inspite of there being a resistive coating there is no protection against etching away through exposed copper edges. This leads to over etching. Have running water ready so that etched board can be removed properly and rinsed. This will halt etching immediately.

Drilling is one of those operations that calls for great care. For most purposes a 1mm drill is used. Drill all holes with this size first those that need to be larger can be easily drilled again with the appropriate larger size.

(D) COMPONENT ASSEMBLY: -

From the greatest variety of electronic components available, which runs into thousands of different types, it is often a perplexing task to know which is right for a given job.

There could be damage such as hairline crack on PCB. If there are, then they can be repaired by soldering a short link of bare copper wire over the affected part.

The most popular method of holding all the items is to bring the wires far apart after they have been inserted in the appropriate holes. This will hold the component in position ready for soldering.

Some components will be considerably larger .So it is best to start mounting the smallest first and progressing through to the largest. Before starting, be certain that no further drilling is likely to be necessary because access may be impossible later.

Next will probably be the resistor, small signal diodes or other similar size components. Some capacitors are also very small but it would be best to fit these after wards. When fitting each group of components mark off each one on the components as it is fitted and if we have to leave the job we know where to recommence.

Although transistors and integrated circuits are small items there are good reasons for leaving the soldering of these until the last step. The main point is that these components are very sensitive to heat and if subjected to prolonged application of the soldering iron, they could be internally damaged.

All the components before mounting are rubbed with sand paper so that oxide layer is removed from the tips. Now they are mounted according to the component layout.

(E) SOLDERING: -

Soldering is an alloying process whereby a small amount of soft metal is made to run between the two metals to be joined, thereby mixing or alloying them. Flux is to be applied to the tips and then the components are soldered. All solder alloys have low melting the metal to be joined. Following points must be remembered while soldering:

  • Components must not be loose.
  • Avoid formation of Solder Bridge.
  • Over heating of component or IC's may damage it permanently.

(F) PRECAUTIONS:

  • All connection leads should as small as possible to reduce unwanted inductive reactance.
  • The soldering iron being used for soldering of semiconductors should be of low voltage.
  • While soldering semiconductors, heat sinks should be used.
  • While soldering solder should not spread over the entire circuit, and solder tip should be sharp and smooth.
  • While mounting components values should be visible.
  • Semiconductors and other polarized components should be mounted with correct polarities.

LAYOUT

7.1 TRANSMITTER:

7.2 RECEIVER:

CONCLUSION

A Digital Speech Security System brings out the various operations involved in the process. Front panel test points provided can be used to show waveforms of clocks, PCM signals, encrypted speech, receives o/p waveform before and after filtering. Even though for demonstration purpose, a sinusoidal signal of 2V p-p is preferred, Speech signal from a microphone amplified can also be applied and the o/p can be maintained using loudspeaker. The module can be used as a demonstration model for communication engineering students.

FUTURE SCOPE:

This project can be enhanced for long distance or wireless communication for improving B.W. of by modulating the encrypted signal by either QPSV or BPSV.

This system can be made multi user by using CDMA (Code Division Multiple Access), where multiple signal occupy the BW are to be transmitted simultaneously without interfacing with one another. As each user has its own code which perform the direct sequence special spectrum modulation. This multiple access system has unique advantage over other multiple access system that the transition time of users dates symtrds do not have to coincide with those of other users. For accomplishing this unique feature of CDMA, we have to install a computer system loaded with switching software.

Bibliography

  • Taub Schilling - Principles of Communication Systems
  • Wayne Tomasi - Advance Electronics & Communication System
  • R.G.Gupta - Audio & Video Systems
  • K. R. Botkar - Integrated Circuits
  • Ramakant Gaikwad - Operational Amplifiers
  • Timothy Pratt - Satellite Communication
  • M. Morris Mano - Digital Logic & Computer Design
  • CMOS Datasheet - 40XX Series
  • CMOS Datasheet - 74XX Series

Web Sites

http://www.national.com

http://www.fairchildsemi.com

http://www.howstuffworks.com

http://www.google.com (google search engine)

http:// www.denayer.be