Vedic Mathematics For Digital Signal Processing Biology Essay

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In this paper VHDL implementation of multiplier using ancient Vedic mathematics is presented. The Urdhva Tiryabhyam sutra (method) was selected for implementation since it is applicable to all cases of multiplication. Multiplication using Urdhva Tiryabhyam sutra is performed by vertically and crosswise, vertically means straight above multiplication and crosswise means diagonal multiplication and taking their sum. The feature of this method is any multi-bit multiplication can be reduced down to single bit multiplication and addition. Single bit multiplication can be easily implemented using AND gate. This method requires high carry propagation that can be implemented using fast adders. The simulation results for 4 bit multiplication are illustrated. The results show that Urdhva Tiryabhyam sutra with less number of bits can be used to implement multiplier efficiently in signal processing algorithms.

Keywords: Signal Processing Algorithms, Vedic Multiplier, VHDL Implementation.

INTRODUCTION

Vedic Mathematics is an ancient mathematics which is based on 16-sutras and 16-sub sutras invented by Jagadguru Shankaracharya Bharati Krishna Teerthaji Maharaja (1884-1960) [1]. In Vedas there are only nine numbers and a zero. The basic number always remains one to nine and all extra numbers are the products of these numbers. Mainly multiplication in Vedic mathematics in carried out using three sutras Nikhilam Navatascaraman Dasatah, Ekadhikena Purvena and Urdhva Tiryagbhyam [1]. Nikhilam Navatascaraman Dasatah sutra is based on base and its deviation from the base. Ten and power of ten are called bases. Any number can be either less or more than the base. The difference between the number and base is known as deviation. Ekadhikena Purvena sutra means one more than the previous one. It is well suitable for finding the square of any number ending with five. Urdhva Tiryagbhyam sutra is suitable for all cases of multiplication. Multiplication using this sutra is performed by vertically and crosswise, vertically means straight above multiplication and crosswise means diagonal multiplication and taking their sum.

Digital multipliers are the core components for all digital signal processing algorithms. Hence the performance of these algorithms is highly dependant on the performance of the multiplier [2]. The most common multiplication algorithms used are Array multiplication and Booths algorithm. The computational time in case of Array multipliers are comparatively less since the partial results are calculated in parallel [3]. Multiplication using Booths algorithms takes comparable computational time [3]. These algorithms are used for multi-bit and exponential operations that require large partial results and carry registers [3].

This paper presents multiplication algorithm that may be useful in the efficient implementation of signal processing algorithms. The framework of this multiplication algorithm is based on Urdhva Tiryabhyam sutra of Vedic mathematics. The feature of this method is any multi-bit multiplication can be reduced down to single bit multiplication and addition. Single bit multiplication can be easily implemented using AND gate. This method requires high carry propagation that can be implemented using fast adders.

This paper is organized as follows. In section 2 the Urdhva Tiryabhyam sutra of Vedic mathematics is explained with examples. Section 3 deals with the hardware architecture of the Urdhva Tiryabhyam sutra and results obtained are presented in section 4. Concluding remarks are presented in section 5.

URDHVA TIRYABHYAM SUTRA

Urdhva Tiryagbhyam sutra is suitable for all cases of multiplication. Multiplication using this sutra is performed by vertically and crosswise, vertically means straight above multiplication and crosswise means diagonal multiplication and taking their sum [1]. The feature of this method is any multi-bit multiplication can be reduced down to single bit multiplication and addition. Single bit multiplication can be easily implemented using AND gate. This method requires high carry propagation that can be implemented using fast adders. The multiplication is illustrated using following examples.

Example 1: Multiplication of 42 and 13

Step 1: Starting at the left multiply two left hands most significant digits vertically and set down results underneath as the left hand most significant part of the answer.

4 2

1 3

4 ((4 * 1) = 4)

Step 2: Next multiple crosswise and add these partial results. Set down the result of addition as illustrate below.

4 2

1 3

4 4 (((4 * 3) + (1* 2)) = 14)

1

Step 3: Multiply two right hands least significant digits vertically and set down results underneath as the right hand least significant part of the answer.

4 2

1 3

4 4 6 ((2 * 3) = 6)

1

Step 4: Finally add the digits vertically as illustrated

4 2

1 3

4 4 6

1

5 4 6

Result of multiplication 42 * 13 = 546.

Example 2: Multiplication of 147 and 168

Step 1: Starting at the left multiply two left hands most significant digits vertically and set down results underneath as the left hand most significant part of the answer.

1 4 7

1 6 8

1 ((1 * 1) = 1)

Step 2: Next multiple crosswise and add these partial results. Set down the result of addition as illustrate below.

1 4 7

1 6 8

1 0 (((1 * 6) + (1 * 4)) = 10)

1

Step 3: Multiply crosswise most significant digit of the first number to the least significant digit of the second number as well as multiply vertically the middle numbers and add the partial results of the multiplication. Set down the result as illustrated below.

1 4 7

1 6 8

1 0 9

1 3 (((1 * 8) + (1 * 7) + (4 * 6)) = 39)

Step 4: Next multiple crosswise the least significant digits and add these partial results. Set down the result of addition as illustrate below.

1 4 7

1 6 8

1 0 9 4

1 3 7 (((4 * 8) + (6 * 7)) = 74)

Step 5: Multiply two right hands least significant digits vertically and set down results underneath as the right hand least significant part of the answer.

1 4 7

1 6 8

1 0 9 4 6

1 3 7 5 ((7 * 8) = 56)

Step 6: Finally add the digits vertically as illustrated.

1 4 7

1 6 8

1 0 9 4 6

1 3 7 5

1

2 4 6 9 6

Result of multiplication 147 * 168 = 24696.

Thus the above method is equally applicable for binary multiplication. Thus consider the multiplication of two 4-bit binary numbers A3A2A1A0 and B3B2B1B0. The result of multiplication is more then 4-bit, we represent it as S7S6S5S4S3S2S1S0. Using above method of multiplication the result obtained is represented using following equations.

S0 = A0B0 (1)

C1S1 = A1B0 + A0 B1 (2)

C2S2 = A0B2 + A1B1 + A2B0 + C1 (3)

C3S3 = A3B0 + A2B1 + A1B2 + A0B3 + C2 (4)

C4S4 = A3B1 + A1B3 + A2B2 + C3 (5)

C5S5 = A3B2 + A2B3 + C4 (6)

C6S6 = A3B3 + C5 (7)

S7 = C6 (8)

The method for 4-bit binary multiplication is illustrated below with example.

Example 3: Multiply 1101 to 1001

Step 1:

1 1 0 1

1 0 0 1

1

Step 2:

1 1 0 1

1 0 0 1

1 1

Step 3:

1 1 0 1

1 0 0 1

1 1 0

Step 4:

1 1 0 1

1 0 0 1

1 1 0 0

1

Step 5:

1 1 0 1

1 0 0 1

1 1 0 0 1

1

Step 6:

1 1 0 1

1 0 0 1

1 1 0 0 1 0

1

Step 7:

1 1 0 1

1 0 0 1

1 1 0 0 1 0 1

1

Step 8:

1 1 0 1

1 0 0 1

1 1 0 0 1 0 1

1

1 1 1 0 1 0 1

Result of multiplication in binary

1101 * 1001 = 1110101.

HARDWARE ARCHITECTURE

The hardware architecture for the implementation of 4-bit binary multiplication using Urdhva Tiryagbhyam sutra is shown in figure 1. The hardware design consists of three components array of AND gates, partial result calculation through vertical and crosswise multiplication and addition and finally addition using 8-bit fast adder. The calculation of results is done using equations 1 to 8. In the first block the bitwise multiplication is done using array of AND gates. In the next block the bitwise products calculated are added as per the sutra to obtained partial results as expressed in the following equations.

P0 = A0B0 (9)

P'1P1 = A1B0 + A0 B1 (10)

P'2P2 = A0B2 + A1B1 + A2B0 (11)

P''3P'3 P3 = A3B0 + A2B1 + A1B2 + A0B3 (12)

P'4P4 = A3B1 + A1B3 + A2B2 (13)

P'5P5 = A3B2 + A2B3 (14)

P6 = A3B3 (15)

The results of addition in equation 10, 11, 13 and 14 are two bits while in case of equation 12 results are three bits. Finally in the last block these partial results are added using 8-bit fast adders to obtained final result. The final result is calculated using following equations.

R0 = P0 (16)

R1 = P1 (17)

R2 = P2 + P'1 (18)

R3 = P3 + P'2 (19)

R4 = P4 + P'3 (20)

R5 = P5 + P'4 + P''3 (21)

R6 = P + P'5 (22)

R7 = Final carry (23)

A3 - A0 B3 - B0

Array of AND Gates

Partial Result Generator

P''3 P'5 - P'1 P6 - P0

8-Bit Fast Adder

R7 - R0 Final Result

Figure 1: Hardware Architecture of 4-Bit Binary Multiplication

RESULTS

The hardware architecture of the 4-bit binary multiplier using Urdhva Tiryagbhyam sutra is similar to the array multiplier. The work presented in this paper was implemented using VHDL and logic simulation was done in Modelsim simulator and synthesis was done using Xilinx project navigator. The design was synthesized for Spartan3 and Vertex2P devices [4]. The obtained results are presented in table 1 and waveforms for 4-bit binary multiplication for 1010 * 1010 and 1100 * to 1100 are shown in figure 2.

Devices

Logic Delay ns

Route Delay ns

Total Delay ns

Spartan3

8.812

6.647

15.459

Vertex2P

5.425

3.402

8.825

Table 1: Results of 4-bit binary multiplication

Figure 2: Waveforms obtained for 4-bit multiplication

CONCLUSION

The Urdhva Tiryabhyam sutra of Vedic mathematics was implementation using VHDL. This sutra is applicable to all cases of multiplication. The feature of this method is any multi-bit multiplication can be reduced down to single bit multiplication and addition. Single bit multiplication can be easily implemented using AND gate. This method requires high carry propagation that can be implemented using fast adders for lesser number of bits. As the number of bits increases, the number of adders' increases that requires high carry propagation. The results show that Urdhva Tiryabhyam sutra with less number of bits can be used to implement multiplier efficiently in signal processing algorithms.

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