Tsv Based On Chip Spiral Inductor Biology Essay

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This paper presents a novel design and characterization of the spiral inductor based on TSV/3D integration technology. An equivalent lumped model is proposed where this model is based on physics and it takes into consideration TSV nonlinearities and skin effects. A highly accurate closed form expression for our proposed TSV-based spiral inductor equivalent inductance is presented. This closed form is the first in literature. Moreover, this form is verified against large number of EM simulations for different setups and showed excellent agreement with less than 5% error. Also, analytical equation to calculate the maximum quality factor is derived. According to the simulation results, the TSV-based spiral inductor presents better quality factor than planar on-chip spiral inductor (120% improvement) and 3D Via-based spiral inductor (76% improvement) for identical inductance. Moreover, the self-resonance frequency of the proposed TSV-based 3D spiral inductor is 38% higher than the conventional 2D spiral inductor and 3% higher than the 3D via-based inductor. In addition, the proposed inductor occupies only 15% and 60% of the area of the conventional 2D planar spiral inductor and 3D via-based spiral respectively, with the same inductance and higher quality factor. This small area of the proposed inductor leads to significantly reducing the cost of the radio frequency system on chip (RF-SoC).

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Index Terms- Three-Dimensional ICs, Through Silicon Via, TSV, Spiral Inductor, Quality factor (Q), Self-Resonance Frequency.

INTRODUCTION

Inductors are considered important elements in analog, RF, and microwave circuits such as low-noise amplifiers, power amplifiers, filters, oscillators, impedance matching networks, and DC-DC converters .

The poor characteristics of the integrated on-chip inductors due to lossy characteristics of the substrate and thin metal layers, besides its large die area which causes some limitations on routing are limiting factors in realizing RF-SOC circuits .

The benchmarks for the spiral inductor are the quality factor and the self resonance frequency, -. These benchmarks are summarized in .

In most applications, quality factor significantly determines the performances of the circuits. For example, the phase noise of an LC oscillator is inversely proportional to the oscillator quality factor . Therefore, it is important to obtain high quality factor inductance.

Besides the quality factor, the self-resonance frequency is an important factor in inductors, where if the operation frequency exceeds the self-resonance frequency, the impedance of the inductor becomes capacitive. Therefore, the maximum operating frequency should be less than the self-resonance frequency. Hence, increasing the self-resonance frequency is necessary to increase the bandwidth.

Chip area is also an important design issue as it relates directly to the cost.

2D planar and 3D multi-level (via-based) spiral inductor has been reported, -, but they have very small inductance values while consuming large areas (there is a trade of between large Q-factor inductor and area), so spiral inductor with high Q-factor is still a challenge .

Three dimensional integrated circuit (3D-IC) is now considered as a new paradigm in IC design enabling to overcome the actual limitations of 2D-ICs represented in interconnect bottleneck, improve performance, and enable heterogeneous stacking of different layers like RF, analog, digital, and MEMS into a single 3D-IC or even enable stacking of multi-core processors (). Today, many 3D stacking technologies are existing, but through silicon via (TSV) is one of the key points and is considered an excellent candidate for 3D integration for different device layers connection.

Therefore, TSV-based 3D integration, which can be demonstrated in , is a promising solution to improve the quality factor and spiral self-resonance frequency over planar 2D spiral () and 3D via-based spiral (), where it reduces parasitics and loses which are the main causes for the quality factor degradation.

Comparing to 2D spiral, for the same footprint, the resistance in case of 3D TSV-based spiral is lower than the one in case of 2D planar spiral inductor and therefore the quality factor is better. This is due to the fact that direction of current is different for both cases and the effective cross section is constrained by the metal layer thickness which is fixed by standard CMOS process technology in case of 2D planar spiral inductor (The proof can be demonstrated in ).

Table

BENCHMARKS FOR THE SPIRAL INDUCTOR

Benchmark

Description

The quality factor (Q)

The quality factor is defined as a ratio of the net energy stored by magnetic field and the average power dissipation in one cycle, and calculated as:

,

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the Q is decreasing at certain frequency as the capacitive effects are dominating the behavior of the spiral, also the substrate loss at high frequencies can degrade the quality factor.Where, the parasitic resistance consumes the stored energy and the parasitic capacitance reduces the inductivity.

The self resonance frequency (SRF)

Due to the extra parasitic capacitances, a spiral inductor has a SRFwhen the average electric and magnetic energies are equal. Therefore, its factor will vanish to zero at (SRF). The SRFcan be calculated as:

,

where are the equivalent inductance and capacitance, respectively. Obviously, the larger the parasitic capacitance, the lower the .

Comparing to 3D via-based spiral which uses the multiple metal layers to achieve the required inductances in a small area, 3D TSV-based spiral provides less area consumption and less parasitics resistance as the 3D via structure still must use the thinner lower metal layers. Noting that, the fundamental difference between TSVs and vias is the semi-conducting material surrounding them. Since the TSVs are surrounded by silicon, if you turn it laterally they look like  MOS capacitors.

This work introduces the TSV interconnect paradigm as a new architecture for the spiral inductor. Only few investigations have been done for this approach-. Our contributions as compared to previous related publications are briefly summarized in . Numerical comparisons for the common parts will be reported in another section.

The methodology used in the modeling of the spiral can be summarized in the following steps ():

Propose a physics-based lumped element model for the TSV-based spiral inductor.

Simulate the structure of the TSV-based spiral inductor using EM simulation.

Use the results of EM simulator to optimize the physics-based lumped-element values under a number of different setups (TSVs dimensions, TSV electrical and physical properties and substrate parameters).

Use curve-fitting techniques, to develop closed-form expressions for the inductance.

Validate the inductance values set using the closed-form expressions of step (d) against EM simulation.

This paper is organized as follow. In Section II, the basic concepts of the spiral inductor will be reviewed, the proposed architecture for the TSV-based spiral inductor is introduced, and simulation results are discussed. Closed form expression for our proposed TSV-based spiral inductor equivalent inductance is also given. Moreover, the analytical equations for the maximum quality factor are derived to be compared to the simulation-based one. In Section III, verification of the closed form equations are performed. Moreover, comparison with conventional on-chip and multi-level ground-plane (via-based) spiral inductors are presented. Conclusions are given in Section IV.

Core3

Core2

Core1

Digital

Analog

RF

(a)

(b)

Fig. In the 3D design, a 2D chip is divided into a number of different blocks, and each one is placed on a separate layer of silicon where each layer is stacked on top of each other: (a) multi-core processors stacking, (b) Heterogeneous stacking (digital, analog, RF).

Die1

Die2

TSV

Fig. TSV-Based 3D-IC. TSV is used to carry electrical signals vertically through semiconductor die.

dout

din

s

w

Fig. The typical layout for the 2D spiral inductor. The 2D planar spiral inductor can be defined by the design parameters, which are the outer/inner diameter dout/din, the metal width w, the spacing between the wiring metal s, and the number of turns n.

Metal5

Metal3

Fig. The typical layout for the 3D via-based spiral. It consists of series-connected spiral inductors in different metal layers (stacked inductors). The wires wind from the top metal layer to downward the bottom one. The metal thickness increase upward. They can generate the same inductance in less are as compared with 2D planar spiral inductors.

Table

CURRENT DIRECTION IN CASE OF 2D PLANAR SPIRAL INDUCTOR AND 3D TSV-BASED SPIRAL INDUCTOR

2D conductor

3D conductor

Current direction

Y

X

Z

The resistance

(1)

(2)

In CMOS process <, so, .

(The metal thickness is the most significant determinant of the resistive losses and limitations in Q).

So, from (1),(2)

Table

THE CONTRIBUTIONS OF THIS WORK AS COMPARED TO PREVIOUS RELATED PUBLICATIONS

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This essay has been submitted by a student. This is not an example of the work written by our professional essay writers.

Examples of our work

Issues covered in the study

This work

Novelty of the method

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Full-Wave simulation

ü

ü

ü

Lumped element model

ü

ü

û

Taking skin effectand nonlinearitiesinto account for the Lumped element model

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û

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Closed-form expressions for the inductance

ü

û

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Analytical formula for the maximum quality factor

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TSV-BASED SPIRAL ARCHITECTURE AND ANALYSIS

In this section, we will introduce the TSV-Based spiral inductor architecture, propose an equivalent lumped element model, discuss the EM simulation results, and deduce closed form expressions for the inductance and the maximum quality factor.

The Proposed TSV-Based Spiral Inductor: Architecture and Analysis

As stated earlier, in this work we proposed a new architecture for the spiral inductor based on TSV. shows the concept of the winding of the TSV-based inductor, where each turn is modeled as vertical TSV. The spiral inductor parameters and their typical range are defined in , where we use a wide range of inductors, with TSV diameter varying from 5-100 mm, TSV Length ) varying from 50-300 mm, metal track width varying from 50-100 mm, metal track lengthvarying from 20-100 mm, metal track thickness varying from 1-5 mm, space between two metal tracks varying from 10-100 mm, and number of turns varying from 1-3. Also, from , it is noticed that the N-turns 3D spiral inductor consists of 2N TSVs.

Various TSV-based spiral inductors are designed and simulated using EM simulator, Ansoft HFSSTM . The simulated inductance, resistance, quality factor, and self-resonance frequency (SRF) at different number of turns are shown in and , where we obtained peak quality factor ranging from 8 to 21 for inductance ranging from 1.2 to 3.5 nH.

Physics and circuit theory basics

Full Wave EM

Simulator

Optimization

(curve fitting techniques)

TSV-spiral proposed

equivalent lumped model

Closed form expression for the inductance

Spiral Structure

Verification (1): compare the

S-matrix for multiple testcases

Error

< 5%

SPICE-compatible model

No

Yes

Verification (2): compare the S-Matrix for new random testcases

Error

< 5%

Yes

Our model and forms are accurate.

Define design parameters in

Fig. Flow graph illustrations of TSV-based modeling methodology. Where, we propose a physics-based lumped element model for the TSV-based spiral inductor, then simulate the structure of the TSV-based spiral inductor using EM simulation, after that use the results of EM simulator to optimize the physics-based lumped-element values under a number of different setups, use curve fitting techniques, to develop closed-form expressions for the inductance, and finally validate the inductance values set using the closed-form expressions against EM simulation.

The simulation results can be discussed in the following points:

While increasing the number of turns of the TSV-based 3D inductor, more and more metal-to-metal and metal-to-substrate capacitances are generated. Thus, the equivalent capacitances become larger. Hence, the self-resonance frequency decreases while the number of turns increases .i.e. smaller inductor area results in higher SRF.

Moreover, it is noticed that TSV-based spiral inductor is proportional to the area of the loop (, and the number of turns (). We will get analytical proof for this in Section II.C.

A smaller spacing improves the interwinding magnetic coupling and reduces the area consumed by the spiral. However, a large spacing is only desired to reduce the interwinding capacitance.

For the spiral inductor a small inductance typically combines with a high Q, and vice versa, a large inductance combines with a low Q.

Increasing the metal lines width reduces the series resistance, but increases the parasitic capacitance to substrate, which degrades both Q and SRF.

TSV

Port2

Port1

(a)

(b)

Fig. Schematic of two turns TSV-based spiral inductor (a) 3D view (b) top view.

Table

TSV-based spiral inductor typical values

Design Parameters

Typical range

Typical Design value

Number of turns (N)

1-3

3

TSV diameter ()

5-100 mm

5 mm

TSV length ()

50-300 mm

300 mm

Metal track width ()

5-100 mm

5 mm

Metal track length ()

20-100 mm

20 mm

Metal track thickness ()

1-5 mm

1 mm

Space between two metal tracks ()

10-100 mm

10 mm

(a)

(b)

(c)

Fig. EM simulation variations of (a) L, (b) R, (c) Q of 3D TSV-based spiral inductor with 1 to 3 turns versus frequency (1 to 10 GHz) at typical values given in Table III.

Table

GEOMETRIC VARIANTS FOR THE TSV-BASED SPIRAL INDUCTOR AND THE ASSOCIATED ESTIMATED SELF-INDUCTANCE, RESISTANCE, AND QUALITY FACTOR VALUES

N

L(nH)

R(Ω)

Qmax/ F(GHz)

SRF(GHz)

1

1.2

1.26

21.2/5.2

18.1

2

2.3

2

12.1/2.7

16.5

3

3.5

2.9

8.12/1.8

15.1

Proposed Lumped Element Model for the TSV-Based Spiral Inductor and Derivation of Qmax

To allow SPICE simulations (time-domain simulation), a lumped element model for the TSV-Based spiral inductor is proposed (), where the interpretation of each element is demonstrated in . Those elements account for :

Substrate losses: where the capacitive coupling allows conduction current to flow not only in the TSV but also through the substrate.

Metal losses: due to the cupper resistance.

The model parameters of a particular spiral inductor could be estimated by a fitting procedure on the data provided by the EM simulations. The fitting procedure was performed by minimizing the least square error between the circuit element and EM data using curve-fitting software.

The capability of this model to describe the behavior of spiral inductors is investigated, where the inductance and quality factor obtained by the circuit model are compared with the data provided by EM-simulations for various testcases (). The comparison shows a good agreement and confirms that the physical model can indeed predict the overall inductor behavior.

The extracted values of the equivalent circuit models are reported in .

From the obtained values and for simplicity, we will neglect Rdep, Cdep, Cox, R1, L1, and the model can be simplified to the model shown in . This simplified model will help us to obtain closed form expressions for the maximum quality factor.

In circuit applications, spiral inductors could be used in two possible configurations,, ():

1) one-port or single-ended: when one of the two ports is shorted.

2) two-port: when neither of the two ports is shorted and is not symmetrically driven.

The quality factor for single-ended lumped model can be calculated as follow:

using (1), the quality factor Q for the simplified model () can be written as :

(5)

By noticing that is much smaller than , the quality factor is approximated by:

The derivation of Q w.r.t and equating it by zero to get the frequency at the maximum Q results in:

Substituting (7) into (6) results in:

(8)

The values obtained from equation (8) and the values obtained from the simulations () at N=1, 2, 3 are correlated and their values are shown below in .

Port1 1

Port2 2

Fig. The proposed equivalent lumped model for TSV-Based spiral inductor.

Table

THE PROPOSED MODEL LUMPED ELEMENTS AND ITS PHYSICAL INTERPRETATION

Circuit element

Physical meaning

Inductance and ohmic losses of the spiral.

Skin effect of the spiral.

Capacitance of the oxide.

Silicon substrate depletion region capacitance and resistance.

Silicon substrate capacitance and resistance.

Capacitance between two metal tracks of the spiral.

Table

EXTRACTED VALUES FOR R, L, AND C of THE TSV-BASED SPIRAL INDUCTOR PROPOSED MODEL AT (N=1, F=1GHz) AND OTHER PARAMETERS SHOWN IN

N

1

105

200

2

2.1

202

40m

22

2.3k

200

300

403

3

3.3

300

60m

34

3.5k

320

505

612

(a)

(b)

(c)

Fig. A comparison of the EM simulations against the proposed lumped element model simulations for (a) N=1, (b) N=2, (c) N=3.

Y11

Y11+Y12

Y11+Y12

-Y12

Y11+Y12

-Y12

(a)

(b)

Port1 1

Port2 2

Fig. Simplified model of the spiral inductor. This simplified model will help us to obtain closed form expressions for the maximum quality factor.

Fig. Simplified equivalent model representation (a) 2 ports model (b) 1 port model.

Table

The values obtained from equation (7) AND THE values obtained from the simulations () at N=1, 2, 3.

N

Analytical

Value

Simulated

Value

1

21

21.2

2

11.8

12.1

3

8

8.12

N

Analytical

Value

(GHz)

Simulated

Value

(GHz)

1

5.4

5.2

2

2.8

2.7

3

1.85

1.8

Closed Form Expressions for the Inductance

In this section, we will drive an analytical proof for that L is proportional to N not N2 as this was proven by simulations in section II.A. The calculation of inductance in spiral structures is formulated based on the self-inductance, which is fixed by the geometry of each line segment in the coil, and by the mutual components, which are determined by the geometry, the spatial separation, as well as by the relationship between the currents carried by those lines. Parallel currents travelling in the same direction contribute positive mutual components of inductance, whereas parallel currents travelling in opposite directions contribute negative mutual components of inductance- (see ).

The overall inductance of a spiral can be obtained by summing the self-inductances of individual segments and positive and negative mutual inductance between all possible wire segment pairs. For instance, an N turn spiral has:

Lself α 4N, number of self-inductance terms,

Lm+ α 2N(N-1), number of positive mutual inductance terms,

Lm- α 2N2, number of negative mutual inductance terms.

From the above discussion, the following equation can be obtained:

Leq = Lself + Lm+ - Lm- =4 β1N+2 β 2N (N-1) -2 β 2N2

=4 β1N-2β2N=2(2β1-β2)N (9)

where β1, β2 are the self and mutual inductance, respectively

Equation (9) confirms EM simulations results (refer to ).

Using 3D EM simulations along with curve fitting techniques, the closed form equation for our proposed TSV-based spiral inductor equivalent inductance is given by:

From the above equation, the inductance is a function of number of turns, metal track length, TSV diameter, TSV length, and spacing between tracks. This formula is scalable over wide range of spiral dimension (refer to ). From , -,we can notice the following to increase the inductance:

Decrease the distance between the conductor segments that carry currents in the same direction {(seg3, seg7), (seg5, seg1), (seg6, seg2)} to increase positive mutual inductance i.e. decrease (. In other words, the direction of current for the first loop is the same as the second one. Therefore, it is important to make them near each other.

Increase the distance between the conductor segments that carry currents in the opposite direction {(seg3, seg1), (seg5, seg7), (seg6, seg4)} to decrease negative mutual inductance i.e. increase (.

Increase number of turns (N) to increase number of positive mutual inductance terms, which implicitly increase the inductance.

I1

.

(b)

(a)

X

I1

X

I2

X

I2

L1=Lself+M12

L1=Lself-M12

Fig. (a) Parallel currents travelling in same directions contribute positive mutual components of inductance (even mode), (b) parallel currents travelling in opposite directions contribute negative mutual components of inductance (odd mode).

TSV

Port2

Port1

Seg3

Seg1

Seg2

Seg4

Seg5

Seg6

Seg7

Fig. The conductor segments numbering for the TSV based spiral inductor.

TSV-BASED SPIRAL VERIFICATION

In this section, we will validate our lumped model, closed form formula against EM simulations, and provide numerical comparison with related work.

Validation against EM Simulation

The approach which was applied to validate the proposed lumped model and closed form equations presented above (see Section II.B, Section II.C), is to simulate new random physical parameters test-cases using EM simulator and compare them with the lumped model and closed form equation. For all those new random physical parameters, the S-parameters of the EM simulations are correlated with the S-parameter of the lumped element model whose inductance values are found using the closed form expressions. The percent error between simulation and closed-form expressions of TSV-based spiral inductor, inductance () are shown in , where the maximum error is less than 5%.

Table

PERCENT ERROR BETWEEN SIMULATION AND CLOSED-FORM

EXPRESSIONS OF TSV-BASED SPIRAL INDUCTOR INDUCTANCE ()

(um)

(um)

(um)

(um)

50

100

200

5

10

10

2.1

2.4

3.3

100

50

1.9

4.2

2.6

10

10

10

2.7

4.2

2

100

50

3.9

1.4

3.2

15

10

10

1.5

1.5

3

100

50

3.2

4.8

2.7

20

10

10

3

3.1

4.2

100

50

1.5

2

4.3

25

10

10

1.5

1.5

3.1

100

50

3.2

4.8

2.7

30

10

10

3

3.1

4.2

100

50

1.5

2

4.1

35

10

10

1.5

1.5

2

100

50

3.2

4.8

2.7

40

10

10

2.7

3.3

4.2

100

50

1.5

2

4.3

Comparison with Related Work

From the comparison with related work, it is clear that the proposed TSV-based spiral is offering large quality factor and high self-resonance frequency, where the obtained Q from the proposed TSV-Based inductor is higher than the values obtained from identical inductance conventional planar and 3D via-based (stacked) spiral inductors, as reported in .

Table

COMPARSION BETWEEN PLANAR SPIRAL INDUCTOR, VIA-BASED SPIRAL INDUCTOR, AND PROPOSED TSV-BASED SPIRAL INDUCTOR FOR THE SAME INDUCTANCE (0.88 nH, 2.5 nH) AND FREQUENCY (1GHz)

Parameters

Conventional

Planar

Spiral inductor

3D Via-based

Spiral inductor

This work:

Proposed

3D TSV-based Spiral inductor

L(nH)

0.88

0.88

0.88

0.88

R(Ω)

0.92

1.1

0.73

0.527

Q

6

5

7.5

13.2

Area

-

-

(50mm)2

(25mm)2

SRF

-

-

-

10.5 GHz

Parameters

Conventional

Planar

Spiral inductor

3D Via-based

Spiral inductor

This work:

Proposed

3D TSV-based Spiral inductor

L(nH)

2.5

2.5

2.5

R(Ω)

-

-

0.827

Q

6

6.8

11.8

Area

(220mm)2

(80mm)2

(30mm)2

SRF

11.8GHz

15.8GHz

16.3 GHz

<Note> "-"means it is not mentioned.

CONCLUSIONS

In this paper, a proposed architecture based on TSV/3D integration for spiral inductor is demonstrated and characterized. Moreover, closed form expression for the inductance is obtained and analytical equation to calculate the maximum quality factor is derived. Simulation results indicate that our formulas are feasible. Moreover, simulations show that our model presents better quality factor than planar spiral inductor (120% improvement) and 3D Via-based spiral inductor (76% improvement) for identical inductance. Our inductors have Q's in the 8-21 range. Moreover, the self-resonance frequency of the proposed TSV-based 3D spiral inductor is 38% higher than the conventional 2D spiral inductor and 3% higher than the 3D via-based inductor. It also provides lower area for the same inductance, where the proposed inductor occupies only 15% and 60% of the area of the conventional 2D planar spiral inductor and 3D via-based spiral respectively, with higher quality factor. These good characteristics of the proposed inductor indicate that TSV/3D integration is a promising solution for RF-SoC.