Scaling the thickness of the oxide in a Metal-Oxide-Semiconductor device is one demanding need in order to verify Moore's law. Investigation of the quality and the parameters of the gate oxide can be obtained by Capacitance -Voltage measurements. Moreover, parasitic factors like the different types of resistances should be taken into account. Van der Pauw method and Cross Bridge Kelvin Resistor structure are helpful in this effort.
This lab report consists of two parts. In the fist part, a metal oxide semiconductor (MOS) structure was investigated, by measuring the silicon oxide (SiO2) thickness, the refractive index and the capacitance voltage behaviour. Using ellipsometry technique the properties of interest (thickness and refractive index) were measured. Ellipsometry is a non-contact optical technique which measures the change in the polarisation state of light from a surface . Electrical measurement equipment was used for the capacitance voltage investigation of the MOS structure. In the second part, the Van der Pauw structure was used to measure sheet resistivity and the Kelvin structure to measure the contact resistance. In order to do that the IV characteristics of each device were measured.
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Aims and objectives
1. Investigate C-V characteristics of a MOS capacitor
2. Gain experience with different procedures and instruments.
3. Understand the different structure and methods that are been used.
4. Calculate varied parameters of the device.
Capacitance voltage behaviour of a MOS capacitor (p-type substrate)
The ellipsometry technique was obtained in order to measure the thickness and the refractive index of the silicon oxide (SiO2) layer of the MOS (metal-oxide-semiconductor) capacitor. The ellipsometer in the EMTERC clean room was used and the material of the sample was the same as the one in the MOS structure. In our effort to take into account the inhomogeneity of the sample, we took 4 measurements across the sample in order to calculate the average of each parameter that was measured. Our initial goal was a minimum of 5 measurements, but due to problems with deflections of the incident light we took only 4. Then, using the electrical testing station that was available in room H00.45, CV (Capacitance Voltage) measurements at 1 MHz of the MOS capacitor structure were taken. A voltage was applied to the gate while the body was grounded. We set the start voltage at 5 V with a voltage step of -0.5 and the end voltage at -25 V. The extracted data from these measurements are the frequency, the applied voltage, the capacitance and the power dissipation. In our sample the Al top contacts were dots and had two different sizes (1.5mm and 1mm). Five CV measurements were taken for each size.
Sheet resistivity and contact resistance
In Figure I there are the chosen devices for the Van der Pauw and Kelvin structure that we used to measure the sheet and contact resistance respectively.
Figure I. The layout of the chosen devices.
The metal contacts are 100 microns square. To make a measurement, a current is caused to flow along one edge of the sample (for instance, I12) and the voltage across the opposite edge (in this case, V34) is measured. Then we rotate the lead positions by 900 and repeat the measurement. Totally four measurements should be taken in order to estimate the sheet resistance. Similarly, for the Kelvin structure IV characteristics of the device are measured. However in that case different current-voltage, like I23 and V14 should be considered for the calculation of contact resistance.
Results and Discussion
The thickness, the refractive index measurements and the mean of them are listed below.
From the CV measurements we can obtain the CV characteristics of the MOS capacitor. In Figure 1 can be seen the voltage-capacitance behaviour of our samples. The C-V characteristic of a MOS capacitor with a p-type substrate (Figure 1&2&3) is a curve with three different regimes. In the first regime, negative gate voltage (VG<VFB) is been applied and the majority carriers of the semiconductor- in our case holes- accumulate in the surface of Si02-Si. And as can be seen from Figure 1 the accumulation capacitance is almost the same for the two various samples. When positive voltage (VG>VFB) is applied holes are been depleted at the surface. If higher voltage is applied (VG>>VFB) and its large enough, it can cause an inversion to the p-type substrate. The substrate will behave like an n-type substrate not due to doping but due to inversion of the original p-type substrate which was caused by the applied gate voltage.  The measurements of the SiO2 A5 (1.5mm) sample (Figure 1 graph B or Figure 2) and SiO2 D5 (1mm) sample (Figure 1 graph F or Figure 3) are being used for the calculations in this report. All samples seems to have the same CV behaviour, the choice of the one that we use for our calculations is arbitrary.
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The intersection between the graph and the y axis will give the value of the accumulation capacitance Cacc, when the MOS structure is in the accumulation regime.
Cacc = 4.31x10-10
A: area,, d is equal to either 1mm or 1.5 mm respectively to the sample
er: is the relative permittivity of silicon oxide which we calculated
Figure 1.The voltage-capacitance graph of our samples.
Figure 2.The voltage-capacitance graph of the SiO2 A5 (1.5mm) sample.
Figure 3.The voltage-capacitance graph of the SiO2 D5 (1mm) sample.
Then we calculated the thickness of the oxide layer.
In comparison with the measured value (<tox>=144.575nm) the difference is really minor. The observed difference is due to the fact that different relative permittivity (Îµ r) of the SiO2 were taken into account. However, the calculated thickness is exactly the same for our two chosen samples, because the relative permittivity of SiO2 was calculated for each one separately.
The capacitance per unit area is
Substrate doping concentration is
, where is the slope from the curve 1/C2 vs. VG
Then we calculated the capacitance at flatband voltage, CFB, using the following equation and from the C-V curve (Figure 2&3) we found the flatband voltage VFB.
Another way to define VFB is from the graph 1/(C/Cox) 2 vs. V, Figure 4&5.
Figure 4.Plot of 1/(C/Cox) 2 vs. V of the SiO2 A5 (1.5mm) sample.
VFB=V at the lower knee of the curve. VFB= -16.6 Volts
Figure5.Plot of 1/(C/Cox) 2 vs. V of the SiO2 D5 (1mm) sample
VFB=V at the lower knee of the curve. VFB= -15.1 Volts
The difference in the value of VFB using the two ways is because of the use of the graphs to determine it. In the second way of determination it is also the subjective factor. In this graph the capacitance is 1/(C/Cox) 2, while in the first case is the measured capacitance.
The different charges at the semiconductor-oxide (Si-SiO2) interface have a great impact on the MOS structure. There are four possible types of these charges, as shown in Figure 4, the mobile ionic charge (Qm), the oxide trapped charge (Qot), the fixed oxide charge (Qf) and the interface trapped charge (Qit). During the growth of the SiO2, metal ions (as Na+, Li+, K+, H+) can be build-in and introduce positive unwilling charges (Qm). Consequently these charges cause negative charges in the Si surface. Heavy metals or negative ions can also contribute to this charge. Extremely clean materials and proper care procedures should be provided in order to eliminate this type of charges. Moreover, positive or negative charges can be trapped in the oxide (Qot) usually due to x-ray radiation exposure, avalanche injection or other mechanisms. Low temperature (<500OC) treatments can reduce this type of charges. Interface trapped charge (Qit) can be either positive or negative and they originate in structural defects, oxidation-induced defects, metal impurities or other defects caused by radiation or similar bond breaking processes (e.g. hot electrons) . Last but not least, the fixed oxide charge (Qf) is being introduced during the thermal oxidation. During oxidation, Si reacts with the oxygen and when oxidation is finished, some ionic Si is left near the interface. These results in a sheet of positive charges (Qf) near the interface. Hence, its origin is related to the oxidation process and depends on crystal orientation, cooling conditions and on the final oxidation temperature. The higher the oxidation temperature, the lower is Qf. , 
The fixed charge (QF) is a positive charge at the interface that includes the various oxide and interface charges. For the calculation of it we use the theoretical expression for the flatband voltage
Figure 4.Charges and their location for thermally oxidized silicon. The picture is from the paper: Effect of Mobile Ionic-Charge on CMOS based Ion-Sensitive Field-Effect Transistors (ISFETs) 
Also for the threshold voltage of the capacitor we used the equation
The charge in the depletion region is negative for an nMOS structure. Thus, we expect the threshold voltage to be negative. However, in a pMOS structure the threshold voltage can be either negative or positive.
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Below is a table with all the values that were obtained and calculated for the chosen samples.
SiO2 A5 (1.5mm)
SiO2 D5 (1mm)
Relative permittivity of silicon oxide
Thickness of oxide (measured)
Thickness of oxide (calculated)
Capacitance per unit area
2.439 x 10-8F/cm
2.515 x 10-8F/cm
Substrate doping concentration
1.305 x 1016cm-2
1.377 x 1016cm-2
3.55 x 10-10F
1.8 x 10-10F
(from C-V curve)
(from 1/(C/Cox)2 -V curve)
7.92 x 10-7 C/cm2
7.99 x 10-7 C/cm2
It can be observed from the above results that for smaller contact dots the capacitance per unit area and the substrate doping concentration is slightly higher which is expected to be due to the difference of the value of the relative permittivity of SiO2 and the different area. In addition, the accumulation capacitance is different and that has as a result a different flatband capacitance.
The hysteresis of the threshold voltage is mainly due to Qm charges which are usually mobile in the oxide. When there is an applied field this type of charges are drifted at the Si-SiO2 interface. Furthermore, a positive fixed charge at the Si-SiO2 interface shifts the flatband voltage by an amount. Moreover, the work function difference can have as a result a shifted curve. Also there are various impurities in the material which can lead to a hysteresis of the threshold voltage. Intentionally implanted particles can create that hysteresis in order to produce a memory device.
Dry and wet oxidations are two types of thermal oxidation which are being used to produce thin layers of oxides. The chemical reactions are introduced below for each case and the main difference of the procedure is that instead of oxygen, water is used.
Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Si + O2 Â® SiO2 DRY OXIDATION
Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Si + 2H2O Â® SiO2 + 2H2 WET OXIDATION
Furthermore, although wet oxidation has a higher growth rate even on low temperatures and it is possible to grow thicker oxide, the oxide film quality is not satisfactory. Therefore thin oxides such as screen oxide, pad oxide, and especially gate oxide normally use the dry oxidation process. Dry oxidation also results in a higher density oxide than that achieved by wet oxide and so it has a higher breakdown voltage (5 to 10 MV/cm). 
For the measurement of the sheet resistance we used the first device of the Figure I, VdP nW.
Figure II.The IV characteristic of our measurements.
The slope is the resistance (R=V/I).
Using the average of the measured IV characteristics of the device and the following equation, the sheet resistance was found R= 137.8 Ohms/square
Resistivity depends on the length and the cross section area of the material. That is why it is better the contacts to have a square shape like ours.
There are different resistances that have to be considered in our sheet resistivity measurement. As shown in Figure III (a), there is a sheet resistance Rs, a spreading resistance Rsp, a probe resistance Rp and at the interface between the probe tip and the semiconductor there is a probe contact resistance Rcp. The four-point probe method has the benefit that can eliminate the probe resistance, the probe contact resistance and the spreading resistance. The equivalent circuit for the measurement of semiconductor sheet resistance by using the four-point probe method is shown in Figure III (c). The four probes are equally spaced. The current flows between the outer two probes and the voltage is measured between the inner two probes. All the resistances-apart from the sheet resistance- can be neglected for the two inner probes because the voltage is measured with a high impedance voltmeter, which draws very little current. Thus the voltage drop across these resistances is insignificantly small. The reading voltage from the voltmeter will be approximately equal to the voltage drop across the semiconductor sheet resistance. The ratio of the voltage to the current will give the sheet resistance. 
Figure III. Four-point probe measurement of semiconductor sheet resistance. The picture is from the presentation of K.X. Chen, J .K. Kim, F. Mont, and E.F. Schubert.
In addition, Van der Pauw technique has the advantage that allows measurements of samples of arbitrary shape. However, there are four conditions that should be met in order the measuring resistivity to be valid.
All the contacts should be ohmic and from the same material.
The thickness of the sample must be uniform and less than the width and length of the sample.
Contacts areas should be infinitely small.
Contacts must be all in the perimeter, preferably in the corners of the sample.
Using the four terminal Kelvin test structure (Figure IV) and the Van der Pauw method we can measure the contact resistance by eliminating the contribution of bulk or sheet resistance.
Figure IV. Conventional four terminal Kelvin structure. The picture is from the paper: Cross-Bridge Kelvin Resistor structures for reliable measurement of low contact resistances and contact interface characterization 
By forcing current I, the Kelvin potential (V2-V1) between the taps is measured. The contact resistance is simply:
Totally, four measurements were taken for the various rotations and IV combinations. The average of them was used to calculate the contact resistance. Rc= 2.4 Ohms
Figure V.The IV characteristic of our measurements.
The slope is the resistance (R=V/I).
The fact that our plot is not linear is due to errors in measurement. Probe tips should be in good contact with the wafer before proceeding with the measurement. However the errors have the same spread, thus a linear fit is the correct assumption.
The structure of this experiment is a conventional Cross Bridge Kelvin Resistor (CBKR) structure (Figure IV). The disadvantage of this structure is that is very sensitive to lateral crowding current around the contact when the contact window is smaller than the diffusion tap. This current accounts for the additional resistance that induces a voltage drop at the contact periphery. This effect becomes crucial for the relatively high sheet resistance values of diffusion areas.  This problem can be alleviated with the use of a three dimensional model of Kelvin structure.
Capacitance-voltage (CV) measurements are commonly used in studying gate-oxide quality in detail. In this experiment, initially using ellipsometry technique the silicon oxide thickness and refractive index was measured. After, CV characteristics of MOS capacitor structures and calculations of various parameters of the devices took place. Our CV graphs have the typical capacitance-voltage behaviour with a slightly more hysteresis due to the charges within the oxide. Moreover, the calculated silicon oxide thickness was similar with the measured one, verifying our method. For the different sized Al top contacts a difference in the accumulation and flatband capacitance was observed. The size of the contact is proportional to the accumulation capacitance. In order to determine the quality of the oxide the substrate doping concentration, the fixed charge and the threshold voltage were also calculated.
Four-probe method was used for the measurement of the sheet resistivity. Van der Pauw technique eliminates the parasitic resistances and from the IV measurements the sheet resistivity can be calculated as the ratio of the voltage and the current, multiply with a correction factor due to imperfectly symmetry of the sample. The contact resistance was also calculated using the IV characteristics of a four terminal Kelvin structure. According to our results the contact resistance between the probe tip and the surface was quite small (2.4 Ohms), while the sheet resistivity of the device is higher (137.8 Ohms/square). The Rc can be controlled and minimised during the fabrication and the measurement, but we cannot control Rs because it is the resistivity of the device itself and can only be eliminated during the fabrication procedure.