# The Switching States Of Five Level Inverter Biology Essay

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The case study 2 has been taken from. A new cascaded H-Bridge multilevel inverter topology has been proposed in this paper using resonant inverter circuit. A resonant circuit is a combination of an inductor and a capacitor. These are inserted in series to the load in the corresponding circuit. The values of inductor and capacitor are chosen according to the circuit requirement. The values should fulfill the requirement so that resonant frequency in the circuit is equal to the switching frequency of the inverter. The values can be calculated using the mathematical expression [22] given as under

finv = fr = 1ââ€ž ( 2Ã°Å“â€¹âË†Å¡LC )

Where

finv is the inverter frequency, fr is the resonant frequency, L is the inductance and C is the capacitance used in the circuit. The circuit layout is shown in the figure below

The figure above illustrates the cascaded multilevel inverter topology proposed in [22]. There are eight switches and two dc sources used to generate five levels multilevel inverter. The two H-Bridge cells have been connected in series to each other. The resonant circuit used in layout has been demonstrated in the figure. The advantage of using the resonance phenomena is to obtain low voltage (dv/dt) or current stress (di/dt) on the semiconductor switches used in the circuit. If the voltage or current stress will be high, than the output waveform of the inverter can generate unwanted electrical signals which will affect the performance of the electronic devices [28]. The unwanted signals in the circuit results in the generation of electromagnetic interference. This signal can transmit to the other electronic systems through space by conduction along cable or it could be transmitted by radiation [28]. The situation could be more critical if the inverter will operate at higher switching frequency with large number of switching devices. The resonant circuit can be applied to several multilevel inverter configurations depending on the location of inductor and capacitor and switches. The above topology of cascaded multilevel inverter adopts the merits of a general topology of cascaded H-Bridge layout. The proposed topology in [28] has significantly reduced the di/dt switching frequencies less than 25 kilohertz and hence this factor has reduced the electromagnetic interference. The proposed topology in this paper has allowed the cascaded H-Bridge inverter to be used in sensitive applications such as in medical and communication fields where electromagnetic compatibility is given a special importance [28].

## 2.9 Proposed Topology

The proposed topology of multilevel inverter presented in this thesis consists of the combination of circuits used in case study 1 and 2. The new multilevel inverter topology proposed in [27] and the critical review of Cascaded H-Bridge multilevel inverter with a new feature of resonant circuit used in [22] has been considered for designing multilevel inverter. By the help of the above two papers and several others, the proposed multilevel inverter topology is shown below in the figure

The figure above illustrates the proposed multilevel inverter topology used in this thesis. This topology is extracted from [27] and [22]. The circuit consists of SN number of switches. The basic H-bridge cell in the circuit will produce three levels i-e +Vdc, 0 and ââ‚¬"Vdc. Inorder to increase the number of output voltage levels, one dc source will be added along with two switches in the circuit. The circuit can further be extended to N number of switches for producing a nice staircase waveform. The resonant circuit in the circuit will help to reduce switching stress. This circuit with inductor and capacitor could be excluded from the schematic if we have a large number of steps in the output waveform. The maximum number of steps will allow using the inverter without resonant circuit. With the increase in number of steps, the circuit will be close enough to sine wave and the harmonics contents will be reduced. The further description of circuit along with the switching pattern, output waveform results is given in the chapter 3.

## 2.10 Summary

Multilevel inverters are gaining a lot of attention these days. The different topologies of multilevel inverters can be used to generate staircase waveform. Voltage source multilevel inverters use one or more voltage sources to produce multilevel steps. The cascaded H-Bridge multilevel is the most effective inverter with good output waveform. H-Bridge inverters do not use clamping diodes and voltage balancing capacitors whilst they produce the same type of waveform as of diode clamped and capacitor clamped inverters. The comparison in between different inverter topologies proves cascaded H-Bridge inverter to be the best with fewer disadvantages as they have no voltage balancing issues. A new version of cascaded H-Bridge multilevel inverter reduces the use of switches helping in less voltage and current stress. In addition to this, resonant circuit can also be added for improving resonance phenomenon. The major application of proposed new topology cascaded H-Bridge multilevel inverter includes its use in medical and telecommunication fields.

## Chapter 3 Design Methodology

## 3.1 Chapter Overview

In the following chapter, a five level multilevel inverter has been designed initially using new proposed topology. All the switching states and output waveform are described in sections 3.2.1 and 3.2.2 respectively. In the next section 3.3, the circuit schematic, switching states and output waveform of a seven level multilevel inverter has been illustrates. The sections 3.4, 3.4.1 and 3.4.2 explain layout, switching pattern and output waveform of a nine level multilevel inverter designed using new topology. Finally, in last section 3.5, the maximum number of levels achieved in this project i-e thirteen has been illustrated. The switching pattern and output waveform of thirteen level inverter is shown in sections 3.5.1 and 3.5.2. A brief summary of this chapter is given in section 3.6. All the simulation results, output parameters and waveform obtained using PSpice software is shown in chapter 4.

## 3.2 Five level multilevel inverter

A basic three level multilevel inverter was illustrated in the previous chapter. The circuit diagram, switching states, and output waveform was also shown. By using the proposed new topology, the number of switches and dc voltage sources can be added in the circuit for obtaining more levels. A five level multilevel inverter using proposed topology described in section 2.9 is shown below

The figure above illustrates a five level multilevel inverter. The circuit consists of six switches and two dc voltage sources. The H-Bride cell in the circuit consists of four switches i-e S1, S2, S3 and S4. These four switches will generate three levels. In the same fashion, S5 and S6 connected in parallel to each other with another dc voltage source will generate two more levels. Finally a five level staircase waveform will produce at the output voltage VL.

## 3.2.1 Switching states of five level inverter

The six switches used in circuit layout of five level multilevel inverter turns ON and OFF at different pattern or states to generate desired output voltage levels at VL. The switching states along with output levels is shown below in the table

The table above provides information about the switching states of a five level multilevel inverter. The state 1 means that the circuit is in ON mode while state 0 means that the circuit is in OFF mode. The states are explained below

For voltage level VL = 2Vdc, S2, S3 and S6 will be 1 while S1, S4 and S5 will remain 0

For voltage level VL = Vdc, S2, S3 and S5 will be 1 while S1, S4 and S6 will remain in 0 state

For voltage level VL = 0, S1 and S2 will be 1 while S3, S4, S5 and S6 will remain 0

For voltage level VL = -Vdc, S1, S4 and S5 will be 1 while S2, S3, and S6 will operate at 0

For voltage level VL = -2Vdc, S1, S4 and S6 will be 1 while S2, S3 and S5 will operate at 0

## 3.2.2 Output waveform of five level inverter

The output staircase waveform obtained using the schematic above is a five level waveform. The five levels 2Vdc, Vdc, 0, -Vdc and -2Vdc are shown in the figure below

The above figure illustrates the waveform of five level inverter. The levels obtained are generated using 2 dc sources. In the circuit layout, one dc voltage source is generating three level inverter with the help of four switches. The remaining two switches, with the help of another dc voltage source are producing two more levels. Thus, these voltage sources are adding up in series. If the dc voltage of single source is 10 volt, then the two dc sources will produce 20 volts output level waveform with positive and negative cycle.

## 3.3 Seven level multilevel inverter

A seven level multilevel inverter uses eight switches and three dc voltage sources to produce seven output levels. An H-Bridge is connected in the circuit which generates three levels +Vdc, 0, -Vdc. The switches S5 and S6 are connected in parallel to each other use second dc voltage source and produce two more levels 2Vdc and -2Vdc. In the same fashion, the switches S7 and S8 use third dc voltage source to produce two more levels 3Vdc and -3Vdc. The circuit layout is shown below

The figure above illustrates seven level inverter schematic producing output voltages at VL. The positive voltage levels are obtained when the current flows from positive to negative side to the load while negative voltage levels are obtained when the current flows in negative to positive direction. The simulation results, Fourier analysis and output waveform obtained is shown in chapter 4. The eight switches are turned ON and OFF simultaneously to generate staircase levels. The switching pattern of switches is mentioned in next section.

## 3.3.1 Switching states of seven level inverter

The switching states of seven level inverter are shown in the table below. The state 1 represents the switch in ON condition while state 0 represents switches in OFF condition. The pattern of eight switches along output voltage levels VL is given below in the table

The table above illustrates the switching pattern of the inverter designed using proposed topology. The states are explained as below

For obtaining voltage level VL = 3Vdc, S3, S4, S6 and S8 will be 1 while S1, S2, S5 and S7 will remain 0

For achieving voltage level VL = 2Vdc, S3, S4, S6 and S7 will be 1 while S1, S2, S5 and S8 will remain 0

For voltage level VL = Vdc, S3, S4 and S5 will be 1 while S1, S2, S6, S7 and S8 will remain 0

For obtaining voltage level VL = 0, S1 and S3 will be 1 while S2, S4, S5, S6, S7 and S8 will remain 0

For voltage level VL = -Vdc, S1, S2 and S5 will be 1 while S3, S4, S6, S7 and S8 will remain 0

For achieving voltage level VL = -2Vdc, S1, S2 and S5 will be 1 while S3, S4, S6, S7 and S8 will remain 0

For obtaining voltage level VL = -3Vdc, S1, S2, S6 and S8 will be 1 while S3, S4, S5 and S7 will remain 0

## 3.3.2 Output waveform of seven level inverter

The output waveform of seven level multilevel inverter obtained using new schematic is shown in the figure below. The seven levels of inverter comprises of 3Vdc, 2Vdc, Vdc, 0, -Vdc, -2Vdc and -3Vdc. These seven levels are obtained using 3dc voltage sources. Each source produces two levels and one new source adds up two more levels. The waveform is shown below

The figure above illustrates seven level staircase waveform. The above wave has been generated for 20 ms and it will keep on going forever with the same pattern. Further results including Fourier analysis and simulation are shown in the next chapter.

## 3.4 Nine level multilevel inverter

A nine level multilevel inverter generates nine different output voltage levels. For generating nine levels, ten switches are connected in parallel and series combination. There are four dc voltage sources which are used for this purpose. The output levels obtained are 4Vdc, 3Vdc, 2Vdc, Vdc, 0, -Vdc, -2Vdc, -3Vdc and -4Vdc. The circuit schematic of this inverter is shown below in the figure

The figure above illustrates a nine level multilevel inverter. The output waveform obtained at VL is in the form of staircase. One dc voltage source with the help of two switches adds up positive and negative cycle at the output wave. The switching pattern used in the schematic of nine level inverter is described in the next section.

## 3.4.1 Switching states of nine level inverter

The switching pattern used to generate output waveform of the above schematic is shown in the table below. The term 1 refers to ON state while 0 means that the switch is in OFF mode.

The table above illustrates the switching states at different output voltage levels. These states are explained below

For voltage level VL = 4Vdc, S2, S3, S6, S8 and S10 will be 1 while S1, S4, S5, S7 and S9 will remain 0

For achieving voltage level VL = 3Vdc, S2, S3, S6, S8, and S9 will be 1 while S1, S4, S5, S7 and S10 will remain 0

For voltage level VL = 2Vdc, S2, S3, S6 and S7 will be 1 while S1, S4, S5, S8, S9 and S10 will remain 0

For obtaining voltage level VL = Vdc, S2, S3 and S5 will be 1 while S1, S4, S6, S7, S8, S9 and S10 will remain 0

For voltage level VL = 0, S1 and S2 will be 1 while S3, S4, S5, S6, S7, S8, S9 and S10 will remain 0

For obtaining voltage level VL = -Vdc, S1, S4 and S5 will be 1 while S2, S3, S6, S7, S8, S9 and S10 will remain 0

For voltage level VL = -2Vdc, S1, S4, S6 and S7 will be 1 while S2, S3, S5, S8, S9 and S10 will remain 0

For achieving voltage level VL = -3Vdc, S1, S4, S6, S8 and S9 will be 1 while S2, S3, S5, S7 and S10 will remain 0

For voltage level VL = -4Vdc, S1, S4, S6, S8 and S10 will be 1 while S2, S3, S5, S7 and S9 will remain 0

## 3.4.2 Output waveform of nine level inverter

The output staircase waveform of nine level multilevel inverter obtained as a result of above switching pattern is shown below

## 3.5 Thirteen level multilevel inverter

A Thirteen level multilevel inverter produces thirteen output voltage levels. Inorder to produce thirteen levels, fourteen switches are used in parallel and series combination. The switches are numbered from S1 to S14. For generating thirteen levels, six dc voltage sources are used in the circuit. The H-Bridge in design will generate three levels i-e +Vdc, 0 and -Vdc. For further levels, two switches and one dc voltage source will add up in the circuit. the circuit layout is shown below

The figure above illustrates the circuit schematic for a thirteen level inverter. The output of the circuit can be obtained from VL with one leg connected in between S1 and S3 while other leg is connected in between S2 and S4. The switches used in the circuit could be MOSFETââ‚¬â„¢s or IGBTââ‚¬â„¢s. The switching pattern used is shown in next section.

## 3.5.1 Switching states of thirteen level inverter

The switching states of thirteen level inverter along with their output voltage levels generated at VL are shown below in the table.

The table above illustrates the switching pattern of a thirteen level multilevel inverter. The fourteen switches used in the circuit turns ON and OFF at different states to produce staircase. The switching state 1 shows that the circuit is in ON mode while 0 states that the circuit is in OFF mode. The states are explained as below

For obtaining voltage level VL = 6Vdc, S3, S4, S6, S8, S10, S12 and S14 will be 1 while S1, S2, S5, S7, S9, S11 and S13 will remain 0

For achieving voltage level VL = 5Vdc, S3, S4, S6, S8, S10, S12 and S13 will be 1 while S1, S2, S5, S7, S9, S11 and S14 will remain 0

For voltage level VL = 4Vdc, S3, S4, S6, S8, S10 and S11 will be 1 while S1, S2, S5, S7, S9, S12, S13 and S14 will remain 0

For achieving voltage level VL = 3Vdc, S3, S4, S6, S8, and S9 will be 1 while S1, S2, S5, S7, S10, S11, S12, S13 and S14 will remain 0

For voltage level VL = 2Vdc, S3, S4, S6 and S7 will be 1 while S1, S2, S5, S8, S9, S10, S11, S12, S13 and S14 will remain 0

For obtaining voltage level VL = Vdc, S3, S4 and S5 will be 1 while S1, S2, S6, S7, S8, S9, S10, S11, S12, S13 and S14 will remain 0

For voltage level VL = 0, S1 and S3 will be 1 while S2, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13 and S14 will remain 0

For obtaining voltage level VL = -Vdc, S1, S2 and S5 will be 1 while S3, S4, S6, S7, S8, S9, S10, S11, S12, S13 and S14 will remain 0

For voltage level VL = -2Vdc, S1, S2, S6 and S7 will be 1 while S3, S4, S5, S8, S9, S10, S11, S12, S13 and S14 will remain 0

For achieving voltage level VL = -3Vdc, S1, S2, S6, S8, and S9 will be 1 while S3, S4, S5, S7, S10, S11, S12, S13 and S14 will remain 0

For voltage level VL = -4Vdc, S1, S2, S6, S8, S10 and S11 will be 1 while S3, S4, S5, S7, S9, S12, S13 and S14 will remain 0

For achieving voltage level VL = -5Vdc, S1, S2, S6, S8, S10, S12 and S13 will be 1 while S3, S4, S5, S7, S9, S11 and S14 will remain 0

For obtaining voltage level VL = -6Vdc, S1, S2, S6, S8, S10, S12 and S14 will be 1 while S3, S4, S5, S7, S9, S11 and S13 will remain 0

## 3.5.2 Output waveform of thirteen level inverter

The thirteen levels obtained using the proposed schematic comprises of 6Vdc, 5Vdc, 4Vdc, 3Vdc, 2Vdc, Vdc, 0, -Vdc, -2Vdc, -3Vdc, -4Vdc, -5Vdc and -6Vdc. The output waveform of thirteen level multilevel inverter using proposed schematic is shown below in the figure

The figure above illustrates thirteen level inverter staircase waveform designed using proposed switching pattern. Further calculations, Fourier analysis and results are shown in next chapter.

## 3.6 Summary

Cascaded multilevel inverter has been designed by many authors for utility applications. Such a type of inverters uses multiple dc voltage sources and doesnââ‚¬â„¢t require clamping diodes or capacitors. This inverter can generate almost sinusoidal waveform and can eliminate transformers of multipulse inverters. In other words, cascaded type of multilevel inverter is more efficient and suitable as compared to multipulse and pulse width modulation inverters [8]. A new topology of cascaded multilevel inverter has been illustrated and described briefly in this chapter. The levels five, seven, nine and thirteen are generated and results are shown along with their switching pattern to describe the working of the circuit. Maximum thirteen levels are obtained in this project. More number of levels can also be obtained using the same technique and expending circuits to further levels. For a thirteen level inverter, the use of filter circuit can be neglected as the output waveform is close enough to sinusoidal waveform. Simulation results using PSpice is shown in the next chapter.