The Second Order Sigma Delta Adc Biology Essay

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To be able to compare the performance of the bandpass sigma-delta ADC with the lowpass one, the design of the first order bandpass sigma-delta ADC is not enough. Therefore the second order version of it is also designed as shown below.

The number of feedback loops, determines the order of the converter. Hence the addition of another feedback loop to the original 1st order converter yields a second order bandpass sigma-delta ADC. The simulink version of the second order ADC is shown on the next page.

3.7 Derivation of the quantization noise ei - ei-1

To be able to derive the quantization noise, the discrete-time equivalent circuit of the sigma-delta modulator after sampling, needs to be designed.

Some changes are made in order to facilitate this derivation for example; the 1-bit DAC has been replaced by a line while the comparator has been replaced by a summer with added noise, ei.

Due to the delay, the ith step will be

is the difference between two consecutive errors. This difference becomes a high pass filter.

Frequency response of ei [E(f)]

Let ui = ei - ei-1

Frequency response of ui [U(f)]

The whole idea behind deriving the quantization noise is to demonstrate the concept of noise shaping.

3.8 Comparison of the quantization noise spectra of different converters

Figure 22 shows the quantization noise spectrum of a typical Nyquist type converter. Figure 23 shows the effects of oversampling. fS/2 is much greater than 2fC and the quantization noise is spread over a wider spectrum. The total quantization noise is still the same but the quantization noise in the bandwidth of interest is greatly reduced. Figure 24 illustrates the noise shaping of the oversampled sigma delta modulator. Again the total quantization noise of the converter is the same as in Figure 22, but the in-band quantization noise is greatly reduced.

3.9 Noise shaping concept in SIMULINK

In order to confirm the noise shaping of the sigma-delta ADC, the following circuit is implemented in simulink.

The settings of the following blocks are changed while default settings are applied to the rest.

Sine Wave

Frequency = 1*2*pi

Sample Time = 1/8

Matlab Function (1-bit DAC)

y = -1+2*u;

3.10 Derivation of the formula "SNR = 6.02N + 1.76 dB"

The theoretical quantization noise of an N-bit A/D converter is firstly derived. Once the rms quantization noise voltage is known, the theoretical signal to noise ratio is computed.

Quantization Noise Model

An ideal converter makes a maximum error of ± 1/2 LSB as shown in the transfer function of an ideal N-bit ADC (Figure 26)

The quantization error for any ac signal which spans more than a few LSBs can be approximated by an uncorrelated sawtooth waveform having a peak to peak amplitude of q, the weight of an LSB. Another way to view this approximation is that the actual quantization error is equally probable to occur at any point within the range ±½ q. Although this analysis is not precise, it is accurate enough for most applications.

The quantization error as a function of time is shown in more detail in Figure 27.

Again a simple sawtooth waveform provides a sufficiently accurate model for analysis. The equation of the sawtooth error is given by

e(t) = st, -q/2s < t < +q/2s

The mean square value of e(t) can be written as

Performing the simple integration and simplifying,

The root mean square quantization error is therefore

Rms quantization noise = =

The sawtooth error waveform produces harmonics which extends well past the Nyquist bandwidth of dc to fs/2. However all these higher order harmonics must fold (alias) back into the nyquist bandwidth and sum together to produce an rms noise equal to.

Bennett points out that the quantization noise is approximately Gaussian and spread more or less uniformly over the Nyquist bandwidth dc to fs/2. The underlying assumption here is that the quantization noise is uncorrelated to the input signal. Under certain conditions where the sampling clock and the signal are harmonically related, the quantization noise becomes correlated, and the energy is concentrated in the harmonics of the signal. However the rms value remains approximately . The theoretical signal to noise ratio can now be calculated assuming a full scale input sine wave.

Input full scale sine wave = v(t) =

The rms value of the input signal is therefore

Rms value of full scale input =

The rms signal to noise ratio for an ideal N-bit converter is therefore

SNR = 20 log10

SNR = 20 log10 = 20 log10 2N + 20 log10

SNR = 6.02N + 1.76 dB, over the dc to fs/2 bandwidth

Bennett's paper shows that although the actual spectrum of the quantization noise is quite complex to analyze, the simplified analysis which leads to the equation of "SNR = 6.02N + 1.76 dB" is accurate enough for most purposes. However it is important to emphasize again that the rms quantization noise is measure over the full Nyquist bandwidth, dc to fs/2.

3.11 Effective number of bits

The ENOB is a measure of the quality of a digitized signal. The resolution of a digital-to-analog or analog-to-digital converter (DAC or ADC) is commonly specified by the number of bits used to represent the analog value, in principle giving 2N signal levels for an N-bit signal. However, all real signals contain a certain amount of noise. If the converter is able to represent signal levels below the system noise floor, the lower bits of the digitized signal only represent system noise and do not contain useful information. ENOB specifies the number of bits in the digitized signal above the noise floor. [1]

The 6.02 term in the divisor converts decibels (a log10 representation) to bits (a log2 representation).

The 1.76 term comes from quantization error in an ideal ADC.

CHAPTER 4: RESULTS AND DISCUSSIONS

4.1 Results for sinusoid

The input to the first order lowpass sigma-delta ADC in the first case is a sinusoid of frequency one hertz and amplitude one. According to the Nyquist Sampling Criterion, the input signal must be sampled at least twice the input frequency of it, that is at least two hertz. But sigma-delta ADC uses the principle of oversampling to convert the analog input signal into digital form. Thus the frequency to be used in the sigma-delta ADC must be a multiple of the Nyquist frequency, that is

Input signal frequency = 1 Hz

Nyquist frequency = 2 * input signal frequency = 2*1 = 2 Hz

Oversampling frequency = K * Nyquist frequency = K*2 = (2K) Hz

Where K can be 4,5,6,7,8,9……………….

In this case the first value K=4 is used for the oversampling frequency to be eight hertz (2*4). The sinusoid passes through a number of stages before being filtered out from the digital filter. The output is a digital representation of the analog input. It is noticed that there is delay between the analog waveform and its digital counterpart. This is due to the delay accumulated when the sinusoid has passed through different components of the sigma-delta ADC. To be able to determine the error between the input and output signals, one has to be superimposed on the other so that they look nearly similar to each other. This is done through the 'Transport Delay' block which is placed on the analog path. This enables the analog signal to be delayed by some milliseconds and appeared to map exactly on the digital waveform.

The error calculated in the time domain is the difference between the delayed analog waveform and the digital one. Then the error signal, along with the delayed sinusoid is used to calculate the SNR as shown in the model of sigma-delta from simulink. For the first case (k=4), an SNR of 18.2 dB is obtained. The same steps are repeated for different values of K and the results are tabulated as shown below.

4.1.1 Processing of results obtained for sinusoid

The increase in SNR after K is doubled, is calculated by the difference between two successive readings of the SNR. This is done so as to find out by how much SNR varies as the sampling frequency is doubled. For the case of the sinusoid, the change in SNR varies from 8-10 dB.

For each reading the ENOB is calculated from the equation

From the values of ENOB, it is deduced that in order to achieve a 7-bit resolution, the 1-bit sigma-delta ADC with an oversampling ratio of 32 can be used instead of designing a conventional Nyquist 7-bit ADC which is very complex and consumes more power.

Using values of K and SNR, a semi-log graph is plotted in matlab to view how the SNR varies upon increasing the sampling frequency and thus settings in frequency could be made so as to obtain a better SNR. This kind of plot is used because one of the variables being plotted covers a large range of values (K) while the other has only a restricted range (SNR) - the advantage being that it can bring out features in the data that would not easily be seen if both variables had been plotted linearly.

The Figure 28 depicts the relationship between quantization noise and OSR for a first order sigma-delta modulator. The graph illustrates that as the OSR (K) increases, the noise decreases (SNR increases). The rate at which the SNR increases due to increase in OSR, is as follows. Two points are taken as follows:

(10, 29) and (20, 38)

As OSR doubles from 10 to 20, the SNR increases by (38-29) = 9 dB. Hence it is deduced that the SNR for a first order lowpass sigma-delta increases by nine decibels per octave. An octave is either the halving or doubling in frequency (in this case, octave means doubling).

Another observation made in the case of the sinusoid is the quantization level associated with the digital waveform after filtering. The waveform in Figure 29 shows the digital representation (blue) of the analog input (red) of frequency 1 Hz sampled at 16 hertz (oversampling ratio = 8). The SNR obtained for this simulation is around 27 decibels which corresponds to an ENOB of about 4 bits. In other words, the performance of the sigma delta ADC with an OSR of 8 is equivalent to that of a standard 4-bit ADC. An n-bit ADC normally has 2n levels; therefore a 4-bit ADC will have 24 levels (16 levels). Effectively the digital representation in the sigma-delta also has 16 levels, thus confirming the correct value of the SNR.

The initial transient response is neglected because the digital filter takes many clock cycles to settle. The counting of the levels is started after the waveform reaches steady state as indicated by the arrows. The 16 arrows represent the 16 different levels of the digital signal.

4.2 Results for Lowpass signal

In the second case the input to the sigma delta ADC is a narrowband lowpass signal with cut off frequency at ten hertz. The nyquist frequency is 20 hertz, and thus the oversampling frequencies are multiples of 20, starting with 80 hertz which denotes an oversampling ratio of four. The same procedures done for the sinusoid, are repeated for the narrowband lowpass signal and the following results are obtained as shown below.

4.2.1 Processing of results for lowpass signal

The semi-log graph of SNR against K for the low pass signal is also plotted and shown below.

From the two graphs plotted, it is deduced that the SNR variation with increasing oversampling ratios, is nearly the same for the case of the sinusoid and the low-pass signal.

4.3 Results for bandpass signals

The third case involves the simulation of a bandpass signal of bandwidth 50 Hz modulated at a carrier frequency of 1 KHz. The bandpass input is applied to both the first and second order bandpass sigma-delta ADC, and the results are tabulated below.

4.3.1 Processing of results for bandpass signal

The results obtained from the 1st order bandpass sigma-delta ADC are not good enough since the changes in SNR are random. At some instant the SNR increases and at other times, it decreases. No observation or deduction could be made and therefore these results are ignored.

Meanwhile the performance of the 2nd order one is better with the increase in SNR for each doubling of the sampling frequency as shown in the graph below.

From the graph, it is seen that at OSR = 32, the value of the SNR is a bit higher, which has led to the graph being deviated slightly from its expected straight line. If the line of best fit is considered, it will have the same relationship between SNR and OSR as obtained in the case of the first order lowpass sigma-delta ADC.

It is deduced that the quantization noise shaping of the second order bandpass sigma-delta modulator is equal to that of the first order lowpass sigma-delta modulator. In other words, bandpass sigma-delta converters require double the order of lowpass sigma-delta converters to obtain the same performance.

4.4 Waveforms at different levels of the sigma-delta modulator

The analog versions of the first order lowpass modulator's signal diagrams for the sinusoid look like this.

Note that in this example the clock rate, which here is also the sample rate, is 16 times higher than the frequency of the input signal. Conventional converters require a sample rate of more than twice the highest input frequency. Delta sigma converters require much more in order to produce a sufficient number of bitstream pulses.

Now that the clock rate is 64 times higher, it is obvious that the more bitstream pulses are produced the better is the approximation of the input signal by the average bitstream.

The bitstream can be regarded either as a digital or an analogue signal. The bitstream is a one-bit serial signal with a bit rate much higher than the data rate e.g. of the ADC. Its major property is that its average level represents the average input signal level. A digital "high" represents the highest and a "low" represents the lowest possible output value.

The average (low pass filtered) bitstream never exactly represents the input signal. It is always superimposed by some kind of noise as shown in Figure 34.

One way to reduce this noise is to further increase the clock rate. Due to the sampling theorem the sampling rate must be higher than twice the maximum input frequency. Any further increase is called "oversampling rate".

The Figure 34 shows the quantization noise introduced by the ADC (red), the green sinusoid represents the original sinusoid while the blue waveform is the digital representation of the analog input. The difference between the green waveform and blue waveform gives the quantization noise (red).

4.5 Noise Shaping

The output of the sigma-delta modulator in section 3.9 is analyzed in the frequency domain. A set of matlab codes is used to find the Fourier transform of the output.

The figure above clearly shows that most of the noise in the low frequency band has moved into the high frequency region, therefore the digital filter can filter out maximum noise. As a result, the SNR of the ADC will be highly improved.

4.6 Fan-fold paper model

In the bandpass sigma-delta ADC, fan-fold paper model is also demonstrated when sampling the bandpass signal which is centered at a high frequency, F0. The sampling frequency, FS to be used, depends on the bandwidth of the signal FB, not on the highest frequency (F0 + FB/2). After passing through the converter, the signal energy of the bandpass on F0 will fold down to the frequency band between 0 and FS/2 as if it was a baseband signal.

As seen in both figures above, after sampling, all of the signal energy on sheet 5 will fold down onto sheet 1 as if it is a baseband between 0 and FS/2.

4.6.1 Fan-fold paper model illustrated in matlab

In this project, the bandpass signal of bandwidth 50 Hz is centered around F0 = 1 KHz, that is the signal is in the band 975 Hz to 1025. Using a sampling frequency FS of 400 Hz, the bandpass signal has fold back into the range 0 to 200 Hz (FS/2). The Figures 38 and 39 confirm the fan-fold paper model.

From Figure 39, it is seen that the oversampling frequency has translated the spectrum of the bandpass signal down to baseband. The presence of a dc offset at Frequency = 0 Hz, is also noted. Thus by programming the digital bandpass filter, this dc offset is eliminated.

CHAPTER 5: CONCLUSIONS AND RECOMMENDATIONS

5.1 Work achieved and main results

It was shown that a sigma delta converter grossly oversamples the input signal and shapes the noise spectrum such that the modulator appears to be a high pass filter for the noise and a low pass filter for the input signal.

For every doubling of the oversampling ratio, the SNR improves by 9 dB, or equivalently, the resolution improves by 1.5 bits.

There is a strong relationship between the output-data rate and the converter's resolution. If the sample rate is kept constant, lower data rates provide high effective resolution, or ENOB, at the output of the converter. Whereas if data rate is kept constant, higher sample rates provides the same performance (high resolution).

Normally if a 4-bit ADC has to be designed using conventional nyquist rate converters such as flash converters, the complexity of the circuit is much higher compared to the sigma-delta ADC. The same 4-bit ADC has been achieved through the 1-bit sigma-delta ADC using an oversampling ratio of eight, which has a less complex circuit.

In the 4-bit flash ADC, the use of the 16 comparators in addition to decoders, resistors and NOR gates, covers a larger surface area compared to the 1-bit sigma-delta ADC. Moreover, the power consumption will be greater due to the superior number of components used.

5.2 Practical considerations and limitations

For the case of the sinusoid, the values of the SNR for oversampling ratios over 64, could not be correctly obtained since the original and the reconstructed waveform are nearly the same. The error remains constant for the specified OSR above. Thus results for values of K, of 128 and above are not considered so as not to deteriorate the performance of the sigma-delta ADCs, which will result in their characteristics not being justified.

For the lowpass signal, the SNRs for K=4 up to K=32, are determined quite easily but for K=64, the settings of the digital filter is adjusted in order to get a satisfactory value of the SNR, but for K >= 128, the same problem is encountered as in the case of the sinusoid.

For the bandpass sigma-delta ADC, the four settings of the digital bandpass filter (Fstop1, Fpass1, Fpass2 and Fstop2) are changed each time the sampling frequency is increased. Fpass1 and Fpass2 are easily set since they are centered in the region from zero up to Fs/2 whereas Fstop1 and Fstop2 are continuously adjusted until the correct digital output is obtained from the simulation. Again the number of simulations for multiple oversampling frequencies are limited to OSR=64.

The transient responses in the cases of sinusoid and lowpass signal are taken into consideration for the calculation of SNR while that of the bandpass signal are ignored (SNR determined after digital signal reaches steady state).

5.3 Advantages and disadvantages of sigma-delta ADCs

The penalty paid for the high resolution achievable with sigma-delta technology has always been speed - the hardware has to operate at the oversampled rate, much larger than the maximum signal bandwidth, thus demanding great complexity of the digital circuitry. Because of this limitation, these converters have traditionally been relegated to high-resolution, very-low frequency applications.

The digital filtering stage results in long latency between the start of the sampling cycle, and the first valid digital output. Similarly, there is a significant lag thereafter between digital outputs and their corresponding sampling instants. This characteristic has prevented the use of these converters in multiplexed systems - it takes many clock cycles for the digital filter to settle after switching from one channel to the next.

By having thus outlined the key limitations of these devices, we've established the framework within which they are suitable, and may now proceed to itemize their numerous advantages when compared with alternate technologies:

Most of the circuitry in sigma-delta converters is digital. This implies that performance will not drift significantly with time and temperature. Also, incorporation of the converter into a single-chip package with additional circuitry, such as a D/A converter or DSP is feasible. Finally, the cost of implementation is low and will continue to decrease.

They do not require an external sample & hold circuit; due to the high input sampling rate and low precision of the A/D conversion, the devices are inherently self-sampling and tracking

The background noise level, which determines the SNR, is independent of the input signal level.

Since there is a digital filtering stage after the A/D converter section, noise injected during the conversion process can be controlled very effectively. In fact, the filter may be tailored to minimize noise with very specific characteristics. (Noriega, 1996)

5.4 Further work

In this project, it has been seen how the lowpass sigma-delta ADC depends on oversampling rates to provide better signal-to-noise ratio while for the bandpass one, the amount of noise also depends on the order of the modulator in addition to the oversampling rate. Furthermore the behavior of the SNR upon the increase of order of the lowpass sigma-delta converter can be studied.

It has also been deduced that the bandpass sigma-delta converter require double the order of the lowpass one to achieve the same performance, but still the need of designing higher orders of bandpass converters is required in order to confirm this deduction.

For higher values of oversampling ratios (e.g. K = 128 and above), a new better method of finding the SNR needs to be devised.

A final improvement to this project can be the derivation of an approximate formula to calculate the SNR of the sigma-delta using parameters such as data rate, sample rate and order of the modulator. For example to achieve a good performance (SNR), there can be limitations on frequencies (i.e. higher frequencies cannot be used), thus the order of the modulator can be increased to compensate for the limited frequency thereby obtaining the same SNR. On the other hand the same can be applied if there are few components to implement the circuit i.e. the order of modulator is restricted to a certain value. Thus, a source with high frequencies is used to match the same performance as in the earlier case. To summarize this point, there is a trade-off between oversampling ratio and order of the modulator to design a sigma-delta ADC with a specified performance. The optimum use of the larger available resources is advised.

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