The Proposed Adc Design Biology Essay

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Recent trends in mixed-signal design for wireless application require high speed and power-efficient ADCs. Flash ADC architecture is an optimum choice for speed but dissipates power exponentially with increase in resolution. The present work on 5-bit 1.5 GS/s ADC explores new architectural strategy of circuit design in optimizing the power using reduced comparator architecture. The proposed circuit using only 5 comparators when operated with 2.5 V supply, dissipates less (83mW) power and silicon area as compared to existing architectures. The proposed ADC offers an ENOB of 4.60 bits, SNR of 27.2dB, SFDR of 36.21dB, INL and DNL of 0.32LSB and 0.43LSB respectively when simulated using 500nm CMOS MOSIS (AMIS) C5X design kit.

Keywords- Analog to Digital Converter, Low Power, High Speed Comparator, Resolution, Multiplexer.

Introduction

The development of CMOS technology has in general helped to increase the speed of electronic circuits [1]. Communication systems like cognitive, software defined radio in general and upcoming wireless communication standards using impulse radio, UWB like 802.15.4 WPN or 802.15.6 WBAN in particular requires high speed and low resolution (4-5 bits) ADCs [2,3]. Conventionally, a flash-type converter is often chosen when the sample rate is high, since it can perform a conversion in a single clock cycle. However, this comes at the expense of an exponential dependence of area and power on the resolution, as well as offset variations of the parallel paths, which requires pre-amplifiers or extra calibrations [4].

This paper presents the design and simulation of 5-bit 1.5GS/s high speed-low power ADC. The proposed ADC design uses only 5 comparator and 4 multiplexers as compared to 32 comparators used in 5 bit flash ADC. While multiplexer is used for passing reference voltages, the comparator not only generates the digital output code but also acts as a sample and hold circuit. The comparator used in the proposed work is a high speed latch based comparator and the ADC output is obtained in a single clock cycle. With such architecture, there is a saving in power and area. Section II discusses the proposed ADC design while section III presents the result. Conclusions are discussed in Section IV.

Proposed ADC Design

The proposed ADC design uses only 5 comparators and 4 multiplexers to generate 5 digital bits. The architecture although uses the concept of comparison with half values as done in successive approximation register ADC, it doesn't require any DAC and separate register unit. Moreover due to the parallel architecture in the design, the output is generated in one clock cycle for n-bit conversion.

To generate the most significant bit (B5), the analog input signal (Vin) is compared with the reference voltage (V) and depending upon their magnitude either 1 or 0 is transferred as bit B5. The former is transferred when input voltage is higher and latter is transferred when it is less. The output of comparator also acts as select line for 2x1multiplexer and either analog input signal (Vin) or difference (Vin1) of analog input signal (Vin) and reference voltage (V) is passed from this multiplexer. The output of this multiplexer is then compared with half of the reference voltage (V/2) in the next comparator and its output forms the next digital bit (B4) of ADC.

This process is repeated again and the output of the last comparator is applied as select line for the next multiplexer. However this time V/4 and 3V/4 are applied as inputs to this multiplexer. The output of this multiplexer is then applied as one of the inputs to the next comparator with analog input signal (Vin1) being the other one. The output of this comparator forms the next digital bit (B3) of ADC and is also applied simultaneously to 4x1 multiplexer as one of the select line, the other being the bit B4. The output of this multiplexer and analog input signal (Vin1) is applied as inputs to the next comparator and the output of this comparator acts as next digital bit (B2) of ADC. This output is also applied as one of the select line inputs to the last 8x1 multiplexer, other being the output bits B3 and B2. The output of this multiplexer is then finally applied as one of the input to final comparator, the other being analog input signal (Vin1). The output of this comparator forms the final digital output bit (B1) of ADC.

The fractions of reference voltages (V/2) for 2x1 multiplexer, (V/8, 3V/8, 5V/8 and 7V/8) for 4x1 multiplexer and (V/16, 3V/16, 5V/16, 7V/16, 9V/16, 11V/16, 13V/16 and 15V/16) for 8x1 multiplexer are generated by a resistive ladder network. The block diagram of the proposed ADC design is presented in Fig. 1.

Fig.1 Block Diagram of Proposed ADC

Fig. 2 shows the circuit diagram of 2x1 multiplexer. It consists of two pairs of CMOS transmission gates for passing the reference voltages. The choice of employing transmission gates in preference to pass transistors is because of its effect on dynamic range.

Fig. 2 Circuit Diagram of 2x1 Multiplexer

Table I present the aspect ratio of transistor:

Table I. Aspect Ratio of 2x1 multiplexer

Transistors

Aspect Ratio

(µm/µm)

M1,M2,M3,M4

2.5/.5

M5

2.5/.5

M6

1.25/.5

Using three 2x1 multiplexers, a 4x1 multiplexer is realized. In the design two 2x1 multiplexers are connected in parallel and the output of these multiplexers are passed as an input to another 2x1 multiplexer. Depending upon the two select signals any one of the four inputs acts as output of 4x1 multiplexer.

In the same fashion (as done in 4x1 multiplexer), a 8x1 multiplexer is realized using two 4x1 multiplexers and one 2x1 multiplexer. The two 4x1 multiplexer are connected in parallel and the output of these two multiplexer is passed as an input to 2x1 multiplexer. Depending upon the three select line signals any of the eight inputs acts as output of 8x1 multiplexer.

Fig. 3 shows the circuit diagram of high speed comparator which compares the analog input voltage (Vin) with reference voltage (V) and generates digital output as either '1' or '0'. The proposed comparator consists of the following stages:

Pre-amplifier

Latch

Differential stage

Output driver

Firstly the signal which is to be compared is applied to the positive terminal of comparator while the reference signal is applied to its negative terminal. The difference of these signals is amplified by a differential amplifier with inherent DC offset. With high bandwidth and slew rate, high speed is obtained in the present work. Moreover the latch stage (also known as positive feedback stage) is so designed that the response time in 'ns' is achieved in the present case. By exploiting the response characteristics of pre-amplifier (negative exponential response) and latch (positive exponential response), a steep rise (less propagation time) in the output is obtained. For cancelling the DC offset, a self biased differential stage is used. Finally the output drive stage (push-pull driver in the present case) is used for providing the complete swing.

Fig. 3 Schematic of High Speed Comparator

Table II shows the aspect ratio of comparator & Table III presents the simulation results of comparator.

Transistors/Source

Aspect Ratio (µm/µm)

M1,M2

50/0.5

M3,M4,M5,M6,M7,M8

5/0.5

M9

0.5/0.5

M10,M11,M12,M21

5.5/0.5

M13,M14,M15,M16,M17,M18,M19,M20,M21

11/0.5

Current Source

50 µATable II. Aspect Ratio of Comparator

Table III. Measured Parameters

Parameter Name

Measured Value

Propagation Delay

8ns(with load capacitor of 5pF)

Power Dissipation

1.286 mW (Avg. power)

3.43 mW(Max. power)

Resolution

12 mV

The subtractor block of Fig. 1 is designed using a two stage operational amplifier. Fig. 4 presents the schematic of two stage op-amp working as subtractor. The first stage consisting of differential transconductance stage converts voltage to current (V→I) while the other stage being a current mirror load for transforming these differential currents into voltages (I→V). The second stage comprised of common-source MOS transistors which convert first stage voltage to current (V→I) and a current sink load which converts the current to output voltages (I→V).

Fig. 4 Schematic of two stage op-amp as Subtractor

Table IV shows the aspect ratio of two stage op-amp as Subtractor.

Table IV. Aspect Ratio of Subtractor

Transistors/Device/Source

Aspect Ratio(µm/µm)

M1,M2

10/.5

M3,M4

5/.5

M5,M8

2.25/.5

M6

50/.5

M7

7/.5

C1

3pF

Current Source

50µA

Results

This section presents the simulation results of proposed ADC. The simulation of proposed ADC is done on Tanner Tools using 500nm CMOS MOSIS (AMIS) C5X design kit.

Fig. 5 shows the transient analysis of comparator where one of the inputs is a sinusoidal signal with 30 MHz and the other input is a constant DC signal of 0.5V.

Fig. 5 Transient Response of High Speed Comparator

As seen from the waveform, the output of comparator is either logic 1 or 0.

Fig. 6 presents the output transient waveform of proposed ADC. The analysis is carried out by using single ended power supply of 2.5 V. The input voltage is given as a ramp input of 0 to 2.5 V (full scale range). The functional simulation of ADC shows all the digital codes from 0 to 31.

Fig. 6 Transient Waveform of 5-bit ADC

The proposed ADC has also been characterized for static and dynamic performance. The output value of each code is compared with the infinite resolution characteristic and a measure of the difference of each code is calculated. The difference gives INL as 0.32 LSB and DNL as 0.43 LSB. Fig. 7 & Fig. 8 present the INL and DNL for proposed ADC.

Fig. 7 INL plot

Fig. 8 DNL plot

The output of the proposed ADC is reconstructed using an ideal DAC for calculating different dynamic parameters like signal- to noise ratio (SNR), signal to noise and distortion ratio (SINAD) etc. Fig. 9 presents the FFT plot for calculation of different dynamic parameters. The calculated value of spurious free dynamic range (SFDR) comes out to be 36.21 dB, SNR as 27.2 dB and SINAD as 24.10 dB at frequency of 150 MHz.

Fig. 9 FFT plot for SNR, SINAD & SFDR

Conclusion

In this paper a 5-bit, 1.5 GS/s ADC using reduced comparator architecture has been presented. The proposed architecture results in saving of power and exploits some of the properties of SAR ADC while generating the n bit output in 1 clock cycle. The performance summary of proposed ADC presented in Table V shows its superiority in terms of power dissipation even though it is at a higher technology node. The proposed ADC design using preamplifier-latch based architecture not only runs at higher speed, but also has low power dissipation. This makes it highly suitable in wireless applications which currently use flash ADC architecture resulting in exponential power dissipation with increase in resolution.

Table V. ADC Performance Summary & Comparison

Author Name & Year

Blazquez 2005

[5]

Varzaghani

2009

[6]

Lin

2010

[7]

This Paper

Tech. (nm)

180

130

130

500

Supply Voltage (V)

1.8

1.2

1.2

2.5

Power

86mW

300mW

120mW

83mW

Sampling Rate

1.2 GS/s

4.8 GS/s

3.2 GS/s

1.5 GS/s

Resolution

4-bit

5-bit

5-bit

5-bit

INL(LSB)

-

0.65

0.39

0.32

DNL(LSB)

-

0.55

0.24

0.43

SNR

-

-

-

27.2 dB

SNDR

-

30.4

-

24.10 dB

SFDR

-

-

-

36.21dB

ENOB(bit)

-

4.76

4.54

4.60

- not mentioned in the paper

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