The Number Of Inputs And Outputs Biology Essay

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Combinational logic simply describes digital circuits constructed from a number of standard logic gates. Theses circuits are 'static' in that they do not require clock inputs. You can think of a combinational digital circuit as a 'Black Box', that is a box (which contains the circuit) with a number of inputs and a number. See the diagram below:

It is important to realise that the number of inputs and outputs is determined by the design problem only. For example a 3 to 8 line decoder will require three inputs and will have eight outputs, on the other hand a BCD to seven segment decoder will have four inputs and seven outputs (these devices will be studied later in the course).

When a digital circuit has been designed and tested (the black box has been filled in) you can use that design as a building block to develop more complex circuits. This process can continue almost indefinitely allowing you to produce complex digital circuits. This process is Top Down Design. It is simply a way to take a very complex design problem and divide it into smaller manageable problems.

DIGITAL ELECTRONIC DEVICES

Logic Families

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Historically logic devices have been developed since the introduction of the electronic switch, whether implemented from valves, discrete transistors or large-scale integrated circuits.

Many logic families were produced providing building blocks for digital designs; these include:

Resistor Transistor Logic (RTL)

Diode Transistor Logic (DTL)

Transistor Transistor Logic (TTL)

Emitter Coupled Logic (ECL)

Complementary Metal Oxide Silicon (CMOS)

You will find that most digital circuits today are implemented in either TTL or CMOS.

These two families provide the digital design engineer with a range of devices that satisfy almost any digital design criteria.

TRANSISTOR-TRANSISTOR LOGIC (TTL)

The TTL family was introduced in the 1960s and is still widely used today. The digits '74' as the first two numbers of the IC identify TTL devices. With developments in semiconductor technology, more TTL sub-families were introduced, to provide various combinations of :-

Better power consumption,

Faster operation or

A combination/compromise between the two.

You should remember that the general numbering system for all TTL devices: -

Starts with the two digits 74,

Followed by one or more letters, which denote the subfamily,

Followed by the device number itself.

The descriptor letters, and the corresponding TTL family, are listed in table 1.1

Descriptor

Family

Example

No Letter

Standard TTL

7400

L

Low Power

74L00

LS

Low Power Schottky

74LS00

ALS

Advanced Low Power Schottky

74ALS00

AS

Advanced Schottky

74AS00

F

Fast (Fairchild Advanced Schottky)

74F00

Table 1.1

NOTE: 54XX - Military TTL version of the 74 series. It's main different is the extended operating temperature range up to 120oC

Example of TTL gate - NAND gate circuit diagram

D2

+VCC

R1 R2 R4

4kï- 1.6kï- 130ï-

D4 Q3

Y

Q2 D1

D3 output (x)

Q1 Q4

R3

1kï-

Figure 1.1: Basic TTL NAND (74xxx)

Q1 = multiple emitter transistor (can have 8 inputs)

Q3Q4 = Totem pole configuration

D1 = Level shifter diode is to guarantee Q3 turns OFF when Q4 is ON

R1~R4 = biasing resistors to ensure transistor work as fast electronics switches (not as amplifier)

TTL Electrical Characteristics

All TTL devices operate from a single 5Volt power supply, in which: -

a high level is a logic 1

a low level is a logic 0.

You should remember that logic devices are constructed from transistors that are analogue devices and, as such, they will produce slightly varying output characteristics.

The consequence of this is that we cannot specify a single voltage to represent a logic 1 or logic 0. In fact, you will find that manufacturers specify: -

a range of voltages that represent a logic 1,

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a range of voltages to represent a logic 0 and

an undefined, (invalid), range of voltages, which represent neither a logic1 or a logic 0.

You will see later that, one advantage of this invalid range is that it gives the device some degree of noise immunity.

Typical example of logic level voltage ranges for TTL:

Input specification: Output specification:

VIL : 0V - 0.8V VOL : 0V - 0.4V

VIH : 2V - 5V VOH : 2.4V - 5V

Undefined or Floating Voltage:

Input : 0.81V - 1.99V

Output: 0.41V - 2.39V

The table 1.2 on the next page is one example of the total manufacturer's specifications for a TTL device.

According to table 1.2,

Logic 1 at input = 5 - 2 = 3V

Logic 0 at input = 0.8 - 0 = 0.8V

Logic 1 at output = 5 - VOH(min)

Logic 0 at output = VOL(max) - 0

Recommended Operating Conditions

Symbol

Parameter

5400

7400

Units

Min

Typ

Max

Min

Typ

Max

VCC

Supply Voltage

4.5

5

5.5

4.75

5

5.25

V

VIH

High Level Input Voltage

2

2

V

VIL

Low Level Input Voltage

0.8

0.8

V

IOH

High Level Output Current

-0.4

-0.4

mA

IOL

Low Level Output Current

16

16

mA

TA

Free Air Operating Temperature

-55

125

0

70

ï‚°C

Electrical Characteristics over recommended operating free air temperature

Symbol

Parameter

Conditions

Min

Typ

Max

Units

VI

Input Clamp Voltage

VCC = Min II = -12mA

-1.5

V

VOH

High Level Output Voltage

VCC = Min, IOH = Max

VIH = Max

V

VOL

Low Level Output Voltage

VCC = Min, IOL = Max

VIH = Min

V

II

Input Current @ Max Input Voltage

VCC = Max, VI = 5.5V

mA

IIH

High Level Input Current

VCC = Max, VI = 2.4V

IIL

Low Level Input Current

VCC = Max, VI = 0.4V

mA

IOS

Short Circuit Output Current

VCC = Max

54

-20

-55

mA

74

-18

-55

ICCH

Supply Current With Outputs High

VCC = Max

4

8

mA

ICCL

Supply Current With Outputs Low

VCC = Max

12

22

mA

Switching Characteristics at VCC = 5V and TA = 25ËšC

Parameter

Conditions

CL = 15 pF

RL = 400ï-

Units

Min

Typ

Max

tPLH Propagation Delay Time Low to High Level Output

12

22

ns

tPHL Propagation Delay Time High to Low Level Output

7

15

ns

Table 1.2

Table 1.2 is an extract from a manufacturers data sheet for the 7400, which is a quad 2-input NAND gate. Each parameter is given for the 54 series and the 74 series. We will consider each parameter in turn for the 74 devices:

VCC is the supply voltage. As stated previously this in nominally 5V but you can see that the allowable range is from 4.75V to 5.25V.

VIH is the voltage range at the input that represents a logical 1 (high). You should be able to understand the notation: V = Voltage, I = Input and H = High (logic 1). You can see that the minimum value for a logic 1 at the input is 2V (the maximum would be the supply voltage).

VIL is voltage at the input that represents a logical 0. In this case any value below 0.8V represents a logical 0.

IOH is the current sunk into the output (hence the negative value) when the output is high. In this case the maximum current is -0.4mA.

IOL is current supplied by the output when the output is at a logical 0 (low). The value in this case is 16mA.

TA is the range of temperatures over which the device is guarantied to operate within it's specification. This device will operate from 0 to 70ï‚°C.

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VI is the input clamp voltage. This is the allowable voltage to which an input may be connected to clamp it to logic zero. In this case the value is -1.5V.

VOH is the range of output voltages that represent a logical 1 (high). From Table 1.2 you should be able to see that minimum value is 2.4V but is typically 3.4V.

VOL is the range of output voltages that represent a logical 0 (low). In this case the maximum value is 0.4V but is typically 0.2V.

II is the input current when the maximum input voltage is applied to the input. In this case the value has a maximum value of 1mA.

IIH is the high level input current when the input voltage is set to 2.4V in this case.

IIL is the low level input current when the input voltage is set to 0.4V in this case.

ICCH & ICCL are the values of the supply currents when the outputs are high and low respectively.

tPLH is the time taken for the output of a gate to go from low to high (0 to 1) as a result of an input change.

tPHL is the time taken for the output of a gate to go from high to low (1 to 0) as a result of an input change.

The specification of a device is used to assess its suitability for a particular application.

In other words, you must interpret the specification in order to understand the implications of each parameter.

POWER and GROUND

All ICs need to be powered up before use, i.e., they have to be connected to the power and ground points. The DC power aupply pin of a TTL chip is labelled as VCC and as for a CMOS chip it is labelled as VDD. Many newer CMOS ICs which are designed to be compatible with TTL chips also uses VCC as their power pin.

74XX 5V +/- 0.25V

54XX 5V +/- 0.5V

CMOS 3V to 18V (+5V dc is often used since CMOS ICs re usually used in the

same circuit as TTL ICs)

NOISE MARGIN

Stray electrical and magnetic fields can induce voltages on a circuit line. These unwanted signals are called noise which can produce unreliable operation in the circuit.

Logic circuits are designed to tolerate this noise to a certain level. This refers to as the noise margin or noise immunity of the logic circuit.

Logic 1

VOH(min) Logic 1

VNH VIH(min)

Floating Floating

Range VIL(max) Range

VNL Logic 0

Logic 0 VOL(max)

Noise margin for logic 1 = VOH(min) - VIH(min)

Noise margin for logic 0 = VIL(max) - VOL(max)

Consider the case where a gate supplies at least 2.4 V for a logical 1 and a following gate can recognize down to 2.0V as a logical 1, then there is a 0.4 V difference in levels.

This safety margin is called the noise margin of the IC.

2.4V (Minimum for Logical 1)

Noise Margin

2.4V - 2.0V = 0.4V

As shown in table 1.2, 0.4 V of noise can be riding on a 1-level output, and the following IC will still recognize the signal as a 1.

Figure 1.1

Some other points for you to note are: -

VIL, low level input voltage, is listed as 0.8 V maximum. The highest volt­age that an IC will accept as a logical 0 is 0.8 V.

A logic 0 level input can range from 0 to 0.8 V.

VOL, low-level output voltage, is listed as 0.4 V maximum.

A logical 0 output can range from 0 to 0.4V.

If the highest logic 0 level that an IC will supply is 0.4 V, but a following IC can recognize up to 0.8 V as a logic 0, then once again there is a noise margin of 0.4 V, as shown in figure 1.3, on the next page.

0.4V (Maximum for Logical 0)

Noise Margin

0.8V - 0.4V = 0.4V

0.8V maximum logic 0 level

Figure 1.3

Question

Calculate the noise margin of a 5400 TTL device.

Solution:

Table 1.2 above shows that :-

VOH = 2.5 V minimum,

VIL = 0.8 V maxi­mum,

VOL = 0.5 V maximum,

VIH = 2.0 V minimum.

Therefore, high level noise margin = VOH - VIH = 2.5V - 2.0V = 0.5V

And low level noise margin = VIL - VOL = 0.8V - 0.5V = 0.3V

FANOUT

Fanout is also called the loading factor. It is a measure of the ability of a logic gate output to drive a number of inputs of other logic gates of the same type.

All gates have fanout limitations because their inputs require to drive current. CMOS gates have a high fanout advantage over TTL.

Examples: Fan-out Ratio

1 LS --- > 5 TTL

1 TTL --- > 10 TTL

20 LS

1 CMOS --- > 50 CMOS

IOL, which is the low-level output current, is listed as a maximum of 16mA in table 1.2. This current is flowing into the gate. Hence the gate is said to be "sinking" current.

The Manufacturer guarantees that the 7400 can "sink" 16mA, without the zero level output voltage rising above 0.4V.

IIL, the low-level input current, is listed as a maximum of -1.6mA, this current is flowing out of the gate, (hence the minus sign).

Figure 1.4, on the next page, shows a 7400 NAND gate sinking current from ten similar devices, each with a low-level input current of -1.6mA.

This total input current of 1.6mA is said to be "one standard TTL load".

Fan-out is a measure of the number of loads that a gate can drive.

Therefore, you can calculate the fan-out of a gate using :-

IOL

IOH

Fan-out L =

Fan-out H =

;

IIL

IIH

1.6mA

1.6mA

1.6mA

1.6mA

1.6mA

1.6mA

1.6mA

1.6mA

1.6mA

16mA

Figure 1.2

For a NAND gate driving other standard loads:

Fan-outL =

IOL

IIL

=

16mA

1.6mA

=

10 standard loads

You can see that this means that each of the standard TTL gates can drive ten other standard gates.

Table 1.3 below shows the input and output currents for NAND gates from each subfamily.

In this table, IOL is a measure of the drive capability of each subfamily.

TTL

L

LS

ALS

S

AS

F

Units

IOH

-400

-200

-400

-400

-1000

-2000

-1000

A

IOL

16

3.6

8

8

20

20

20

mA

IIH

40

10

20

20

50

20

20

A

IIL

-1.6

-0.18

-0.36

-0.2

-2

-0.5

-0.6

A

Table 1.3

Question

How many 74ALS00 gates can a 74L00 drives?

Solution

From Table 1.3,

IOL for a 74L00 is 3.6mA and

IIL for a 74ALS00 is -0.2mA.

Hence:

Fan-out =

IOL

IIL

=

3.6mA

0.2mA

=

18

________________________________________________________________________

If you inspect the data for the 7400 from Table1.3, noting the values for IOH and IOL you should be able to see that the gate can :-

source 0.4mA, when the output is high and

sink a current of 16mA, when the output is low.

TTL Switching Characteristics

As we have mentioned previously, logic devices are constructed from transistors, which are analogue devices and thus cannot be perfect.

One important characteristic is that changes on the input take a finite time to propagate through to the output, resulting in a propagation delay, specified by two parameters:

tPLH : The time taken for the output of a gate to go from low to high (0 to 1) as a result of an input change.

tPHL : The time taken for the output of a gate to go from high to low (1 to 0) as a result of an input change.

Propagation delay: the amount of time starting from when the input to a logic gate becomes stable and valid, to the time that the output of that logic gate is stable and valid.

Propagation Delay =

tPLH + tPHL

2

TTL

L

LS

ALS

S

AS

F

Units

tPLH

22

60

15

11

7

4.5

5

ns

tPHL

15

60

15

8

8

4

4.3

ns

Table 1.4

The propagation delays for the 7400 TTL subfamilies are shown in table 1.4.

1.5v

1.5v

1.5v

tPHL

tPLH

Input

Output

3.0V

Figure 1.6

You can see from figure 1.6 that :-

The propagation delay effectively set the maximum operating speed of the device.

When the propagation delay becomes a significant part of the period of the applied signal, then the output levels become distorted. Therefore to prevent this, as a rough guide you should limit the frequency of the applied waveform, so that its period is more than twice the maximum propagation delay of the gate,

The various TTL subfamilies are effectively a compromise between power consumption and speed.

Table 1.5 shows a comparison of speed and power consumption for the subfamilies.

Speed

Power Consumption

Fastest

AS

Low

L

F

ALS

S

LS

ALS

F

LS

AS

TTL

TTL

Slowest

L

High

S

Table 1.5

Maximum or Typical Power Consumption =

VCC

ICCH + ICCL

2

CMOS

CMOS stands for Complementary Metal-Oxide Semiconductor field effect transistor.

Complementary means that a P-channel transistor and an N-channel transistor work together in a totem-pole arrangement as shown in Figure 1.9. Metal-Oxide refers to the silicon dioxide layer between the gate and channel.

The gate, channel, and silicon dioxide insulator form a small capacitor. This capacitive input determines many of the characteristics of CMOS ICs.

In Figure 1.9 you can see that when A is HIGH, the N-channel on the bottom is en­hanced, and the output Y is connected to ground through a completed chan­nel. Therefore the P-channel MOS on the top is turned off.

When A is LOW the P-channel is enhanced and the N-channel is turned off. Y is connected to VDD through the P-channel. Therefore these two transistors produce an inverter.

The supply voltages for CMOS ICs are often called VDD, for drain voltage, and VSS, for source voltage. Sometimes supply voltages are called VCC, for col­lector voltage and ground as they were in TTL. VDD varies for each subfamily. VSS is usually 0 V.

VDD

Y = A

Drain

P-Channel MOS Transistor

N-Channel MOS Transistor

Source

Channel

Gate

A

Silicon Dioxide Layer

Figure 1.9

The early series of CMOS devices (the CD4000B series) had three advantages over TTL:

Wide operating voltage range (3 - 15 volts).

Low power consumption.

High noise immunity (1 volt noise margin).

High density of logic functions on a chip.

As with all things in life, there are also disadvantages:

Long propagation delays (100ns).

Low current drive capability (approximately 1 LS-TTL load).

Sensitive to Electro-Static Discharge (ESD).

Some advances were made to partially alleviate some of the disadvantages with the introduction of the HE4000B series. These retained the advantages of the previous devices whilst doubling the drive capability and decreasing the propagation delay. Other families are now available which are pin compatible to TTL devices, these are denoted with the letter C, for example the 74C00 is a CMOS version of the TTL 7400

Descriptor

Family

Example

No letter

Standard CMOS

4001 or 14001

C

CMOS, pin-compatible with TTL

74C02

HC

High speed CMOS, pin-compatible with TTL

74HC02

HCT

High speed CMOS, pin and electrically compatible with TTL

74HCT02

Pin compatibility - CMOS chip's inputs and outputs have the corresponding pin number as that of the TTL chip.

Electrical compatibility - CMOS chip can be connected directly to the TTL chip without any interfacing circuitry in between.

CMOS Characteristics

You should recall that one of the major advantages of the CMOS device is the very low power consumption. Table 1.6 comparative power consumption of CMOS devices against TTL devices.

74AC

74HC

4000

74ALS

74LS

74F

74AS

74

74S

Static

2.5 nW

2.5 nW

1 nW

1.2 mW

2 mW

5.5 mW

8.5 mW

10 mW

19 mW

100KHz

75 W

0.1 mW

1.2 mW

2 mW

5.5 mW

8.5 mW

10 mW

19 mW

Table 1.6

Table 1.7 shows the comparative propagation delay between TTL and CMOS devices. You should be able to see that ALL TTL devices have much smaller propagation delays and as such can be operated at much higher frequencies.

74AS

74AC

74F

74S

74ALS

74HC

74LS

74

4000

HE

HC

Delay (ns)

1.5

3

3

3

4

8

9.5

10

40

95

Max Clk (MHz)

160

150

125

100

60

55

33

25

12

4

Table 1.7

Fan-out

Due to the very low input currents to CMOS gates, the fan-out to similar devices is almost limitless.

However, when interfacing CMOS gates to TTL, (or other) logic families, the fan-out is effectively limited to one TTL load.

Question

How could you overcome this apparent limitation?

Solution

If you wish to drive more than one TTL device from a CMOS output, you should buffer it first.

________________________________________________________________________

COMMON DEVICES

In this section you will study a number of combinational devices and look at design methods, which you will use to design combinational logic circuits of your own.

Buffers and Drivers

Previously, you have studied a number of TTL and CMOS families.

Question

What do you think is one of the major restrictions when interconnecting logic devices?

Solution

One of the major restrictions was seen to be that the output of one device was only capable of driving a restricted number of inputs.

By carefully selecting a device for your design, you could avoid problems, however this is the case only when you have total control over the complete design.

In many cases you will be presented with a number of outputs, (from a "black box"), which will have limited drive capability.

In these cases you would apply the signal to a Buffer or Driver thus giving you control over the selection of devices to use within your design.

Therefore, when interconnecting a number of separate designs (or black boxes) it is good practice to buffer the in-coming and out-going signals

A number of devices are available for such applications. One example is the 74LS244, which is an Octal TRI-STATE Buffer/Line Driver/Line Receiver.

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

VCC 2G 1Y1 2A4 1Y2 2A3 1Y3 2A2 1Y4 2A1

1G 1A1 2Y4 1A2 2Y3 1A3 2Y2 1A4 2Y1 GND

Figure 1.11

As you can see in figure 1.11:-

this device can be thought of as two halves, each buffering 4 inputs, (or bits)

each four-bit section is controlled by an enable signal on pins 1 and 19.

Question

Can you work out what these control signals do?

Solution

Enable the four bits allowing the input to "pass" through to the output.

Place the device in TRI-STATE. This places the device into a high impedance state, which effectively disconnects the device from the circuit.

____________________________________________________________________

The two control signals may be connected together to make the 74LS244 behave as an 8-bit buffer (with TRI-STATE control).

The notation is typical of that used by manufacturers but is by no means universal.

You will find that manufactures data sheets will use various notations, after you have studied a number of these sheets, you will learn to "pick up" the notation used without too much effort.

The notation used here is as follow:

*G is the TRI-STATE control signal, * is either 1 or 2 meaning side 1 or 2.

1A* is the input to side 1 of the device, where * is 1, 2, 3 or 4 meaning input 1, 2, 3 or 4.

2A* is the input to side 2 of the device, where * is 1, 2, 3 or 4 meaning input 1, 2, 3 or 4.

1Y* is the outputs of side 1 of the device, is 1, 2, 3 or 4 meaning input 1, 2, 3 or 4.

2Y* is the outputs of side 2 of the device, is 1, 2, 3 or 4 meaning input 1, 2, 3 or 4.

Inputs

Outputs

G

A

Y

L

L

L

L

H

H

H

X

Z

L = Low Logic Level

H = High Logic Level

X = Don't Care

Z = High Impedance

There are many Buffer/Driver components available in a variety of technologies, (both TTL and CMOS), it is left to you to look at manufacturers data sheets.

All logic families provide a large number of devices. These range from simple gates up to complex multi-bit ALUs (Arithmetic Logic Units).

If a device exists to implement the function you require, all well and good!

However, sooner or later, you will come across a situation when a specific device does not exist. In this case, you will have no option other than to design it yourself, from "standard" logic gates.

The fact that a device may exist should not detract from your overall goal:

To be able to design combinational logic circuits to meet any specification!

We will now look at the design involved in some common logic functions, and the type of chips on which they are implemented, i.e. SSI, (Small Scale Integrated), MSI, (Medium Scale Integrated), LSI, (Large Scale Integrated) and VLSI , (Very Large Scale Integrated) chips.

You will find that the basic definitions of these are :-

SSI - small-scale integrated circuits have up to 10 devices on the chip.

Typical examples of these are logic gates.

MSI - medium-scale integrated circuits have between 10 and 100 devices on the chip.

Typical examples of these are some of the combinational logic circuits, such as multiplexers, demultiplexers, and code convertors, which we will be considering later in this section.

LSI - large scale integrated circuits have between 100 and 10,000 devices on the chip.

Typical examples of these are RAM and ROM chips

VLSI - very large scale integrated circuits have over 10,000 devices on the chip.

Typical examples of these are microprocessors and single chip microcomputers.

EXERCISES:

1. Refer to the simplified specifications for the SN54AS02, SN74AS02 IC in Figure below.

ALS and AS Circuits

SN54AS02, SN74AS02

QUADRUPLE 2-INPUT POSITIVE-NOR GATES

Absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, Vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V

Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V

Operating free-air temperature range : SN54AS02 . . . . . . . . . . . . . . .. . . . . . . . . . . . -550C to 1250C

SN74AS02 . . . . . . . . . . . . .. . . . . . . . . . . . . . . . .00C to 700C

Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . -650C to 1500C

Recommended operating conditions

Parameter

SN54AS02

SN74AS02

Unit

MIN TYP MAX

MIN TYP MAX

VCC

4.5 5 5.5

4.5 5 5.5

V

VIH

2

2

V

VIL

0.8

0.8

V

IOH

-2

-2

mA

IOL

20

20

mA

VOH

3

3

V

VOL

0.35 0.5

0.35 0.5

V

IIH

20

20

A

IIL

-0.5

-0.5

mA

ICCH

3.7 5.9

3.7 5.9

mA

ICCL

12.5 20.1

12.5 20.1

mA

TPHL

1 5

1 4.5

ns

TPLH

1 5

1 4.5

ns

Note : All typical values are at Vcc = 5V, TA = 250C

Based on the specifications above, find

(a) the fanout of the gate and hence determine the actual fanout.

(b) the typical and maximum power consumption of the IC.

2. Propagation delays of logic device are normally labeled as tphl and tplh parameter.

Explain these parameters with the aid of proper timing diagram. If tphl and tplh of a device are 50ns and 80ns respectively what is the propagation delay of this device?