Selectable Voltage Controlled Oscillator Biology Essay

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The speed of operation in digital electronics industry, in both military and consumer products are ever increasing. Pulse generators are the heartbeat of all digital communications and digital logic. The frequency of the pulse generator determines the speed of which the digital circuitry operates, the higher the frequency, the faster digital circuitry can operate. The phase noise of a pulse generator will determine the reliability of the operation of the circuit. A system called Phase Lock Loop (PLL) helps improve the phase noise by comparing the phase of the pulse generated by the VCO with a referencing (more stable) phase with the difference filtered and fed back to the input of the VCO [1]. There are four major module for a PLL system; phase frequency detector (PFD), loop filter, voltage controlled oscillator (VCO), and frequency divider. Figure 1.1.1 illustrates the block diagram of a typical PLL system.

Fig 1.1.1 PLL Block diagram

The VCO generates the operating frequency, which is then divided into lower frequency by the divider (but with the same phase). The phase of the divided frequency is then sensed by the PFD where it is compared to a referencing phase. The loop filter then filters out other carrier frequency components and harmonics, then produces a control voltage to regulate the output frequency of the VCO. The heart of a PLL system is its VCO, it not only determine the operating frequency, but also its reliability and performance.

This thesis focuses on developing both ring VCO and LC tank VCO structures in conjunction with a variable frequency divider to produce a highest possible oscillation, and lowest possible phase noise in order to be used in a PLL system.


This chapter discusses the theories and basic operation of the structure of a Voltage Controlled Oscillator (VCO) and frequency divider used in PLL systems. Two VCO structures were selected to be considered in developing an on-chip high frequency VCO in a 90nm VLSI process. The goal of this research is to find a better VCO and Frequency Divider to be used in a Phase Lock Loop High Frequency Synthesizer. Development of a high frequency divider using 90nm VLSI process is also entailed in this research.

Ring VCO

In today industry, ring VCO structure is preferred in more cost effective applications due to its simplicity and low cost of construction. The ring oscillator is popular in the use of generating an on-chip signal, and it is also often used as a test structure for the fabrication process evaluation [1]. Ring oscillator structure is a cascade of an odd number of CMOS inverters, with the output of the last inverter connected to the input of the first inverter [1]. The operation of ring oscillators depends on the gate delay of the CMOS inverters. Gate delay of CMOS inverters is the time it takes to charge and discharge the capacitance of the MOSFETs due to its physical properties [2]. When placing an odd number of inverter circuits, the gate delay of each inverter adds up to a total delay of which the reciprocal is the operating frequency of the oscillator. Equation 1.1.1 describes the relationship of the ring oscillator [1].

Fosc = 1/2Npi = 1/(N(piR + piF)) (1.1.1)


The LC tank VCO structure is popular in applications that require low phase noise such as in high speed microprocessors which rely on precise arrival time of a clock signal. The main determining factor of the output frequency of the LC VCO is the size of its LC tank. Comparing the oscillation of the LC tank to a marble in a bowl, the smaller the bowl, the faster the marble will roll back and forth in the bowl, where T is the time it takes to complete one cycle. Similar to our LC tank, the smaller the inductance and capacitance, the less time it takes for the electrical energy to transfer from magnetic energy (in the inductor coil), to electro-potential energy (in the capacitor plates). Thus, the smaller the LC tank, the faster the output frequency will be. The LC tank voltage controlled oscillator can also be compared to a tank containing a certain amount of energy that powers the oscillation. The word "tank" refers to the combination of capacitors and inductors that are active components, storing the electrical potential energy in the oscillator circuit. In an ideal situation, there is no "leak in the tank" where the active components have no impedance and no energy loss during oscillation, which is not so in a real world situation. The governing relationship of the LC tank oscillation is observed to be

f = 1/(2*pi*sqrt(LC)). (1.2.1)

Equation 1.2.1 explains the relationship of oscillation frequency f as a function of inductance L and capacitance C. In the real world situation, inductors and capacitors have impedance as a function of frequency. In order to counter the impedances of the active components, a form of negative resistance is required. Figure 1.2.1 illustrates the LC tank with negative resistance.

Figure 1.2.1 LC tank with negative resistance

The negative resistance can be a form of an amplifier using transistors. The experiment conducted with Cadence software is to determine the best possible circuit arrangement to produce the highest oscillating frequency with lowest phase noise possible.

Frequency Divider

The performance and functionality of a frequency divider is vital to the overall performance of PLL systems. The noise produce from the frequency divider will add to the overall noise of the PLL system. This research uses a digital frequency divider for its simplicity and efficiency. The digital frequency structure used in this research operates on a principle of a D-flip-flop, which is also known as delay flip-flop [5].

Fig D-Flip-Flop

When the clock input of the D flip flop sees a positive edge trigger, the output Q becomes the state of the input D [5] as illustrated in figure and figure

Fig D-Flip-Flop Logic

When biasing the output Q' to D, the D-flip-flop behaves as a half divider for the incoming clock signal as shown in figure

Fig D-Flip-Flop Logic as half frequency divider

This frequency divider concept is simple and efficient; therefore, it is selected in this Thesis to be used with an LC VCO for the high frequency PLL in 90nm VLSI process.

As we can see that for a relatively lower frequency PLL such as 200MHz, a half divider frequency divider circuit is sufficient to sync the phase of the output frequency to a crystal oscillator, which operates in the Mega Hertz range [7]. However, for a much higher frequency PLL such as 40GHz, in order to carry out the same objective, many half divider circuits would be required. This leads to creating a problem with power consumption, chip size, and production cause. Therefore,

Variable Frequency Divider

The idea of a variable frequency divider is to be a solution to a high frequency PLL that operates above the Giga Hertz range.

Thesis Organization


Previous Work

The ring VCO structure analyzed in this thesis is based on two low-power wide tuning range VCOs in 90nm CMOS process.

Ring VCO Structure

The structure of the ring VCO used in this research is based on CMOS inverters with PMOS to NMOS ratio of roughly around 2 to 1. The gate delay of the inverter circuits is within 10 to 15 Nano-second ranges.


The strategy for improving the ring VCO structure is based upon the basic property of inverter size in 90nm process.


Design Aspects


As mention earlier, for the oscillation to occur in an LC circuit, there must be an exchange of energy between a capacitor and an inductor. A compensation for the loss of energy is also necessary. Referring to figure 1.2.1 and from Kirchhoff's voltage and current law, we can derive the relationship:


Which is the second order differential equation describing the current in the LC tank as a function of time. And from equation 1.2.1, we can derive the equation for LC tank frequency assuming an ideal capacitor to be:


With the same assumption that the gm of each MOSFETs must be:


The coefficient gm is determined by the size of the MOSFET due to its internal capacitances.

Waveform and Duty Cycle

The purpose of designing a good LC VCO is mainly to satisfy the need for a reliable and efficient clock signal, or a function generator, for a digital logic or any wireless communication applications. Therefore, a time-domain analysis has broken into three sub categories, which are; output frequency, duty cycle, and the shape of the waveform of the output signal. The output frequency of the design will determine what the circuit can be utilized according to the application of the LC VCO. The duty cycle of the output waveform is important to be considered, since the falling or rising edge of the signal will be the trigger for most digital logic applications (i.e. D-Flip-Flops). It will also be important in most analog applications because the duty cycle of the clock signal will determine an ON or OFF time of the transistor. The shape of the output waveform is important for analog applications, since bizarre waveforms can cause errors and misbehavior of the active components such as capacitors or transistors. Bizarre waveforms will also cause noise in analog circuits, and some possible errors in digital computations. For above reasons, all three analyses are very important to be considered in designing a voltage-controlled oscillator.

Phase Noise

The main determining factor of the phase noise is the "Q" factor of the LC tank. The "Q" factor of the LC tank is the quality factor of which indicates how well the energy is stored in the LC network in terms of the rate of energy loss. In an ideal situation, the "Q" factor is assumed to be very low or zero, which we know that it is not so in the reality. Consider a generic oscillator, where vo(t) is the out put voltage, and fo is the oscillation frequency:

vo(t) = [A + a(t)] cos[2πfot + Ф(t)] (

Where a(t) is the zero-mean amplitude noise, and Ф(t) contains all of the phase and frequency that departure from the nominal oscillation frequency fo and phase of 2πfot. A is the mean amplitude of the oscillator output. Phasedisturbance Ф(t) includes random zero-mean phase noise, initial phase, and integrated effects of frequency offset and drift [7].

Tuning Rang

Tuning Linearity

Power Consumption

3.2 LC Oscillators

LC Oscillator Circuit

From what we know about the conditions in which the oscillation will occur, the oscillator circuit is now ready to be design.

Fig 3.2.1 LC Oscillator Circuit

The circuit in figure 3.2.1 was the first LC Oscillator circuit to be tested. The circuit contains four stages; LC tank having two inductors and one capacitor, current mirror, sense amplifier, and an inverter. The current mirror is connected to both of the source terminals of the two transistors to provide a current source for the oscillation. The sense amplifier is connected to both output terminals of the LC tank to amplify the oscillation signal from the tank. An inverter is connected to the output of the sense amplifier to bring the output signal to 0V and 1.2V. The first oscillation of the circuit produced an output frequency of 200MHz (period of 5ns) using an ideal capacitor and inductor model with capacitance of 1pf, and inductance of 100nH. The circuit was then tested with different values of capacitance and inductance to vary the output frequency. To test the steady state response of the oscillation, a relatively long simulation of over 125ns on the oscillating frequency of 9.3GHz was conducted, and the result is illustrated and shows that it is stable.

Figure 3.2.2 Response of the Oscillator circuit with output frequency of 9.3GHz

LC Voltage Controlled Oscillator Circuit

The tuning voltage is to control the capacitance of the varactor in order to vary the frequency. The circuit shown in figure is an improvement of the LC Oscillator Circuit in the previous section. It uses an inverter circuit as an amplifier for the output voltage. This is possible due to an appropriate ratio between the NMOS and PMOS transistor width of the inverter circuit. In this circuit the ratio between NMOS and PMOS (N/P) of 50. The LC network of the circuit determines the frequency of oscillation. The amplitude and the waveform of the oscillation are controlled by the ratio of PMOS and NMOS transistor size of the inverter connected to the LC tank. The detail on dimensions and sizes are recorded in Appendix A. The circuit produces a frequency ranging from 12GHz to 23.1GHz.

Fig LC Voltage Controlled Oscillator Circuit

LC Voltage Controlled Oscillator Circuit Output

As illustrated in Figure, the shape of the waveform of the output oscillation at frequency of 12GHz appears to be lopsided. This is because the inverter NMOS transistor size is too large relatively to PMOS. After testing and fine-tuning the LC VCO circuit, a PMOS to NMOS ratio of 8 to 1 appears to give the best response for the oscillating frequency of 23.1GHz as shown in Figure The NMOS transistors of the LC tank provide the negative resistance to compensate the loss of the LC network. The larger the tank size (i.e. larger capacitance and inductance), the larger the NMOS transistor size needs to be in order to keep the oscillating condition.

Fig LC Voltage Controlled Oscillator Output Waveform


Fig LC Voltage Controlled Oscillator Output Waveform Improved

Using Real Models for Simulation in The LC VCO Circuit

Thus far, ideal inductors and capacitors were used in the experiments to verify the oscillation of the LC tank. However, real inductors and capacitors models used in CMOS technology have internal resistance as well as other physical properties. In order to fully design and simulate the LC tank VCO, a real capacitor and inductor models with all of the physical properties are necessary to be used in the simulation. The inductor model used in the simulation contains wire length and width, number of coil turns, and the permittivity of the material. The capacitor model used in the simulation contains the plate geometry and dimension, the distance between the plates, and the permittivity of the material.

Fig 3.3.1 LC VCO Using Real Component Model

The response of the circuit was different from the previous circuit that used an ideal capacitor and inductor model. The oscillation does not start, unless the transistor size of the NMOS transistor, providing the negative resistance is large enough. In this particular case, it had to be 48 micrometer for the oscillating condition to occur.

The LC tank is comprised of two symmetry inductors in series with two NCAP varactors, with a tuning voltage terminal connected to the positive side of both of the NCAP varactors' terminals, as shown in figure 3.3.1. In this particular configuration, the tuning voltage will vary the capacitance of the varactors, thus changing the size of the LC tank.


Variable Frequency Divider Structure

4.1.1 CML Master-Slave Latch as a Divider

A high speed wide band frequency divider structure is selected for this research. This structure uses the low voltage swig current mode, which allows the operation at very low power dissipation. For a conventional divider application, two CML latches that are identical are connected in a master-slave configuration as shown in figure 4.1.1

Fig 4.1.1 CML master-slave latch as a divider [3].

4.1.2 High Frequency CML Divider

The CML latch clocking structure is simplified by employing a single clock transistor pair to switch the current between the sample-and-hold pair of the master and slave latches [6]. The new configuration of the frequency divider circuit is shown in figure It uses a single biased current source for both of the two latches.

Fig High frequency CML divider core structure [3].

The master-slave combined latch technique uses smaller transistor sizes for the hold pairs of both latches to accomplish the sample/hold current difference [6]. Because of the lower current flowing through the hold pair, the width of the current source does not need to be doubled. This results in a reduction of the overall static power issipation of the frequency divider circuit.

Proposed Variable High Frequency CML Divider

In order to make the high frequency CML divider circuit work with 40GHz , the transistor size ratio must be in an operable range. It has to not be too small that it would shoke the current, and it must not be too large that it would nagate the sample/hold current difference. An inverter circuit with a N/P MOS transitor ratio of 5 is connected to both ends of the output of the divider circuit to provide load, as well as enhancing the output signal. This new configuration also allows the divider to vary its dividing factor as a function of load resistance from resistor R1 and R3.

The proposed frequency divider circuit shown in figure 4.2.1 takes an input frequency of 40-43GHz through "CLK" and divide up the input frequency as a function of the load resistor R1, R3 and R1, R2. To determine the relationship between the resistor value to the dividing coefficient of the circuit, an experiment was conducted to graph out the charecteristics of the output frequency as a function of load resistance R1 and R3, while other components remain constant.

Figure 4.1.3 CML 40GHz high frequency divider circuit in CMOS 90nm process

To determine the relationship between the resistor value to the dividing coefficient of the circuit, an experiment was conducted to graph out the charecteristics of the output frequency as a function of load resistance R1 and R3, while other components remain constant. The following graphs illustrates the output of the frequency as the resistance R1and R3 varies.

Graph 1. output frequency when R1 and R3 is set to 50k Ohm

This graph shows that the duty cycle of the signal is far off from our goal of 50%. There fore, the lower limmit of our resistance value of R1 and R3 will be set higher than 50k Ohm. When the resistor value is set to 900k Ohm, the frequency divider is no longer dividing the input signal. There fore, we will set the maximum resistance value of R1 and R3 to be lower than 900k Ohm.

Table 1 summarizes the result of the experiment. Graph 7 illustrates the characteristics of the circuit as a function of R1 and R3 as it appears to be logarithmic function.





















Table 1. output frequency VS R1 and R3

Graph 7. output frequency VS R1 and R3 curve


In order to utilize the frequency divider circuit with any Phase Lock Loop frequency synthesizer system, a constant and reliable frequency divider circuit with a stable divider constant is needed. Experiments were conducted to find the relationship between the output frequencies as a function of resistance of the load resistor. This is done in order to attain the ability to design a frequency divider circuit by calculating the resistor value needed for a specific dividing constant. As a result, a negative exponential graph was attained representing the relationship between the output frequencies as a function of the load resistance. From the resulting decaying behavior of the output frequency as a function of the load resistance relationship, it is best to use the region of the graph where the slope behaves like a line with a constant slope. The reason being is for the ease of formulating the characteristic equation, and there would be a large tuning range with little variation of the resistor value.

Figure 2. Load resistor in the divider circuit

Figure 3. Load Resistance VS Output Frequency graph

For a linear graph with a constant slope, the governing equation is easy to obtained from simple line equation y = mx+b. The slope is obtained by calculating the rate of change of the output frequency as the load resistance increases.

Figure 4. Load Resistance VS Divider Constant graph

The equation obtained from the graph is approximated to be the expression of

N = 0.59R + 73

The boundary of the load resistor value, however, needs to be set in order to keep the relationship between the divider constant and the load resistance linear. As of input frequency of 40GHz and the divider constant ranging from 50 to 200, the limit of the load resistor values is

Rmax ≤ 250kΩ

Rmin ≥ 100kΩ