Reliability Of Flip Flop And Latches Biology Essay

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The effect of aging has become an important reliability concern in Silicon MOSFET technology today. In-order to satisfy Moores law and continue scaling towards smaller and higher performance circuits, high-K NMOS devices has replaced conventional silicon in fabrication. With the introduction of high-K metal gate, Bias Temperature Instability is graver than ever before. NBTI (Negative Bias Temperature Instability) which subsequently affects PMOS brings about an increase in the threshold voltage while PBTI (Positive Bias Temperature Instability), which affects High-K NMOS devices, decreases the threshold voltage of the device. Flip-flop circuits form an integral part as storage elements in today's pipelined architecture. These devices can easily get affected by such aging and thereby causing timing violations. It is the timing characteristics of the Flip-Flop that usually determine the frequency of operation of the circuit. This project studies the effect of NBTI and PBTI on different flip-flop circuits with key parameters such as Setup time, Hold time and Clock to Output Delay. It also presents a detailed comparison of various popular Flip-Flop circuits with its aging affected readings. Finally, a design solution using Dual threshold Voltage technique has been presented which not only shows high resistance to aging but also shows an improvement over a period of years.

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Introduction

1.1 Background

Device Instability is one of the major hurdles in the scaling of MOS devices. The Bias temperature Instability is considered as one of the major reliability concerns in modern CMOS technologies. BTI can be of two types, Negative Bias Temperature Instability (NBTI) and Positive Bias Temperature Instability (PBTI). NBTI has been the major concern over the past few years and is known to largely affect PMOS devices while NMOS devices showed negligible degradation to them [1]. However, as High-K metal gate usage was adapted in order to satisfy and extend Moore's law for the fabrication of newer technologies, it has been observed that there has been a significant amount of degradation due to PBTI. While the effects of NBTI show little or no improvement from SiO2 to High-K gate, PBTI has become a major degradation factor for NMOS devices and is considered to be a greater reliability concern for all High-K devices in the future. Flip-Flops are an integral part of modern CPU architectures. Since Flip-Flops are clocked storage devices, they are widely used for storage in pipelined architectures. Thus, the timing characteristics of Flip-Flops generally determine the operating frequency of the circuit [3].

This paper studies the combined effect of NBTI and PBTI on Flip-Flop circuits with the usage of 32 nm CMOS technology. Although effect of aging on Flip-Flops has been studied, very less amount of work compares different Flip-Flop circuits for aging. Also, most papers around deal with effect of NBTI alone. The paper then presents the inference of all the results via comparison of these circuits. We use 32 nm High-K metal gate Predictive Model Technology (PTM) by Arizona State University to study the aging effects. All simulations are performed using H-Spice and Synopsys Cosmos tools for construction and observation of the circuit. Later, the circuits are applied with specific aging to all transistors with a time period of 2 years and supply voltage of 0.9 Volts.

FLIP-FLOP AND THEIR TIMING METRICS

Flip-Flops are considered to be the building blocks of sequential circuits. The most basic and popular latch is the S-R latch.

Figure : Basic S-R Latch

As shown above, the S-R latch is constructed with 2 cross coupled NOR gates. The set and reset signals store the value 1 and 0 respectively while the state where both are 0 will hold the current value. As latches are level triggered, they are also designed to trigger at the edge of the clock. These devices are called as Flip-Flops. Most modern Flip-Flop circuits work under similar behavior as the S-R Latch where the S and R input signals are replaced by clock and data. The clock signal usually determines the trigger and thus the operation of the circuit. Due to their simplicity and small size, Flip-Flops are the most popular choice for small register designs. They are extensively used in pipelined architecture holding the next instruction while the current instruction is being processed. However, to cope with high speed and low power designs, large modifications have been made to Flip-Flop circuits making them more complex but more effective. Since they are a popular choice as clocked memory elements, the timing metrics of the Flip-Flops usually determine the frequency of operation of the entire circuit.

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Due to the importance of Flip-Flop circuits in modern day CMOS high speed circuits, it is important to to design the flip-flop with timing metrics into consideration.

Figure : Timing Diagram of Flip-Flops

Setup Time: Setup time Tsu is defined as the minimum time required for the data signal before the active edge of the clock for a valid output.

Hold Time: Hold time Tho ­is defined as the minimum time required by the data signal must remain valid.

Clock to output delay: The clock to Q delay (clock to output) is the propagation time from 50% of the clock signal to 50% of the output with the setup time constraint fulfilled.

Eventually, these are main parameters which dominate the metrics required for the design of the flip-flop.

The overall delay of the circuit can be calculated as :

Tff = Tsu + Tcq , where Tff is the total delay of the circuit.

On the basis of operation of the circuit, we can categorize Flip-Flops into two broad catagories:

Static Flip-Flops

Dynamic Flip-Flops

Static Flip-Flops retain their previous state when the Flip-Flop is opaque. They usually comprise of two stages, Master stage and Slave stage. We are going to analyze 3 such circuits,

Transmission Gate Master- Slave Flip-Flop

Clocked CMOS Flip-Flop

Modified Transmission gate Flip-Flop

Since flip-flop timing metrics are the deciding factors for the frequency of the circuit, it is important to design a flip-flop such that it is resilient to external factors that might affect the performance of the circuit. Thus, our analysis of aging is centered on these parameters.

BTI MODEL

As discussed previously, this paper intends to compare the effects of Aging on different Flip-Flops. For this purpose, we would be using the Predictive Technology Model provided by the Arizona State University. We will be using the Beta version of this model, using the High-K metal gate for our circuits in 32 nm technology to observe the changes of Threshold voltage Vt over time. Using this this model, the dependence of Bias Temperature Instability can be studied. The timing diagram of stress and recovery for a transistor is as shown below:

Figure : Duty Cycle and stress

Here Vgs is the input to the transistor an n is the number of the cycle

Phase 1: Stress, t = (t1, t2)

Δ Vth = . δv..………………………………………………… eq. 1

Phase 2: Recovery, t= (t2, t3)

Δ Vth = (Δ Vth - δv ). [ 1 -√{Å‹(t-t0)/t}]………………………………………….…………… eq. 2

Kv = A . Tox . . exp( ) [ 1- ]). Exp [- ]………………eq.3

Where,

Eox =

The following are the values for the corresponding co-efficients,

A= 1.8 (mV/nm/C0.5)

α=1.3, EO= 2.0 (Mv/cm)

Ea=0.13(eV)

η = 0.35

δv=5.0(mV).

With the help of this model, we can calculate the threshold voltage shift due to the effect of aging. To simplify calculations, we use a program written in MATLAB.

For 32 nm High-K model, we use the following set of values

Table : BTI Model parameters for 32 nm High-K metal Technology

Vdd

Tox

Vth

0.9 V

1.65e-9

0.2 V

Where,

Vdd -> Supply Voltage

Tox -> Thickness of the oxide layer

Vth -> Initial Threshold voltage

Also, there are other parameters required for the circuit. These parameters are, the drain to source voltage Vds, the Duty cycle β (1 for DC stress and between 0 and 1 for AC analysis), the cycle time and the life time of the circuit. For most purposes, based on these values, the shift in threshold voltage can be calculated. We use H-Spice and Synopsys tools for simulations and observations.

As discussed before, the Bias temperature instability affects the transistor in two ways. NBTI, or negative bias temperature instability affects the PMOS on a large scale by causing the threshold voltage of the transistor to increase thereby reducing the ION current of the transistor. NMOS was known to be little or unaffected by NBTI and thus, most research work specially on Flip-Flops covers the effect of NBTI only. However, with the wide use of High-K technology with newer technology levels, the NMOS has shown a considerable amount of degradation where the voltage of the transistor decreases. Thus, it is imperative that the circuit has to be analyzed for the combined effect of both NBTI and PBTI on its transistors. Therefore, we analyze all our circuits by applying both, NBTI and PBTI to the circuit. All transistors have their length minimum sized with their widths optimized.

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Flip-Flop circuits and topologies

Static Flip-flops (Master-Slave)

Static Flip-Flops show negative hold time and positive setup times. We are going to discuss three static flip-flops here

Transmission Gate Master - Slave Flip-Flop

Figure : Transmission Gate Master Slave Flip-Flop

The figure here has minimum sized length and optimized widths. These are the readings of the flip-flop. Here are the readings for 0 to 1 transition.

Table : TGMSFF timing analysis for 0 to 1 transition

Parameters

Clock to Out delay

Setup time

Hold time

Without Aging

17.65

9

-5

With Aging

18.927

9

-5

As we can see here, there is an increase in the clock to Q delay of the circuit. Cacluating the overall delay of the circuit,

Tff = 26.65 p secs before aging and Tff = 27.927 p secs. Thus, it shows an increase of 4.79 %.

Table : TGMSFF timing analysis for 1 to 0 transitions

Parameters

Clock to Out delay

Setup time

Hold time

Without Aging

16.407

7

-5

With Aging

16.86

8

-5

Thus, the flip-flop setup time and clock to Q delay increases.

Thus total delay of the circuit is,

Tff = 23.407 p secs before aging and Tff = 24.86 p secs. Thus, it shows an increase of 6.20 %.

This shows that PBTI impact on these transistors is stronger than NBTI whose impact relatively is slightly lower. This increase is because of the inverters I1 and I2 in the Master pair.

Modified Transmission Gate Flip-Flop

Figure : Modified Transmission Gate Master Slave Flip-Flop

This circuit is similar in operation to the transmission gate flip-flop discussed before with one key and important difference.

For the direct path from data to output, this flip-flop shows 2 less inverters. Instead, there are additional inverters placed in the feedback path of both master and slave parts. From operational point of view, this Flip-Flop is identical.

Table : MODMSFF timing analysis for 0 to 1 transitions

MODMSFF

Clock to Out delay

Setup time

Hold time

Without Aging

8.3994

7

-6

With Aging

8.6915

7

-6

The overall delay of the circuit would be,

Tff = 15.3994 p secs before aging and Tff = 15.6915 p secs after aging. Thus, the overall delay of the circuit is reduced by more than 50 % . It shows an increase due to increase as low as 1.89%.

Table : MODMSFF timing analysis for 1 to 0 transition

Parameters

Clock to Out delay

Setup time

Hold time

Without Aging

11.6

8

-6

With Aging

12.084

8

-6

The total delay of the circuit would be,

Tff = 19.6 p secs before aging and Tff = 20.084 p secs after aging. Thus, the overall delay of

The 1 to 0 transition a lower increase of about 29% from the other flip-flop. Also, the increase in delay due to aging is relatively low (2.46 %). Thus, this Flip-Flop is faster as shows more resistance to aging than the conventional transmission gate master slave Flip-Flop.

Clocked CMOS Master Slave Flip-Flop (C2MOSFF)

Figure :C2MOSFF

This is another another type of Master - Slave Flip-Flop. This circuit consists of a locally generated inverted clock as shown in the figure 6.

Table :C2MOSFF timing analysis 0 to 1

Parameters

Clock to Out delay

Setup time

Hold time

Without Aging

6.7677

26

-18

With Aging

6.9207

26

-18

The total delay of the circuit would be,

Tff = 32.7677 p secs before aging and Tff = 32.9207 p secs after aging. Thus, there is an overall increase of only 0.466%.

As you can see, this Flip-Flop has a huge setup time making the overall delay of the circuit quite higher. However, the flip-flop shows very little change in aging her as there is negligible increase in the delay of the circuit.

Table :C2MOSFF timing analysis for 1 to 0 transitions

Parameters

Clock to Out delay

Setup time

Hold time

Without Aging

8.6686

18

-26

With Aging

8.9707

19

-26

Thus, the total delay of the circuit would be,

Tff = 26.6686 p secs before aging and Tff = 27.9707426 p secs after aging. This circuit shows an increase of setup time, and an overall increase of 4.95% in the delay due to aging.

Dynamic Flip-Flops (Pulse Triggered)

As we can see here, the master slave latchs show an increase in delay due to aging. Let us analyze the pulse triggered latches here. Pulse triggered latches have a pulse generator in their first stage and a latch in their 2nd stage. Thus, the first stage generates a pulse on the rising edge of the clock while the 2nd stage captures the pulse generated in the first stage. Due to the pulse generation, these Flip-Flops have a negative setup time while their hold times are negative. Since the hold times are negative, and do not constitute a part of the overall delay of the circuit, we can ignore their readings on this stage.

Hybrid Latch Flip-Flop (HLFF)

This Flip-Flop was a part of the AMD K-6 design.

Figure : Hybrid Latch-Flip-Flop

This latch features the soft clock edge property where there is a brief transparency window created due to the 3 inverters highlighted inside the blue block. The size of the window is equal to the delay of the 3 inverters. Due to the inverter stage, the data is allowed to pass even after the rising edge of the clock and hence, this Flip-Flop shows a negative setup time and a positive hold time. The 3 inverter series 110, 112 and 113 are the pulse generating stage, while the rest of the stage is for sampling and holding. This circuit will show a varying duty cycle on different transistors, as we can see, the node V1 here is the input to transistors 134 and 145. Thus, these transistors will show a duty cycle of 25% and 75% respectively while the rest of the circuit will have a 50% duty cycle. Thus, the BTI impact is not uniform throughout the transistor.

Table : HLFF timing analysis for 0 to 1 transition

HLFF (0 to 1)

Clock to Out delay

Setup time

Without Aging

17.988

-16

With Aging

18.581

-16

Thus, the total delay of the circuit would be, Tff = 1.988 p secs before aging and Tff = 2.581 psecs after aging. This circuit shows an overall increase of 29.82% in the delay due to aging. This number is quite large and would require necessary design changes to reduce the impact of aging on it.

Table : HLFF timing analysis for 1 to 0 transition

HLFF (1 to 0)

Clock to Out delay

Setup time

Without Aging

9.0525

-5

With Aging

9.881

-5

For 1 to 0, Tff = 4.0525 p secs before aging and Tff = 4.881 psecs after aging. This circuit shows an increase of setup time, and an overall increase of 20.44% in the delay due to aging. Thus, this Flip-Flop shows a tremendous impact on both transitions.

Semi Dynamic Flip-Flop (SDFF)

Figure : Semi Dynamic Flip-Flop (SDFF)

In this Flip-Flop, the transparency window is due to the 2 transistors and the NAND gate on the first stage of the circuit. This stage generates the pulse while the 2nd stage captures the generated pulse. For this circuit, the output node of the first PMOS connected to the clock will have a 75% duty cycle. Thus, all transistors connected to that node will display different duty cycles, namely the 2 transistors in the NAND gate, the PMOS have its duty cycle as 25% and NMOS would have 75% respectively. Both the inverters would show the same as well as the PMOS and the NMOS connected to it at the final stage. The rest of the circuit will have a 50% duty cycle. Thus, there is a large amount of NBTI and PBTI variation and thereby, the effect of aging is largely varying.

Table : SDFF timing analysis for 0 to 1 transition

SDFF (0 to 1)

Clock to Out delay

Setup time

Without Aging

29.431

-10

With Aging

30.488

-10

Thus, the total delay for 0 to 1 transition would be Tff = 19.431 p secs before aging and Tff = 20.488 psecs after aging. This circuit shows an increase of setup time, and an overall increase of 5.23% in the delay due to aging. Although this number is small in comparison with hybrid latch Flip-Flop, it is large and needs careful design consideration.

Table : SDFF timing analysis for 1 to 0 transition

SDFF (1 to 0)

Clock to Out delay

Setup time

Without Aging

7.3161

-19

With Aging

7.462

-20

For 1 to 0, the total delay would be,

Tff = -12.31 p secs before aging and Tff = -13.462 psecs after aging. As you can already see, this flip-flop shows a decrease in setup time and thus an overall decrease in delay by 7%.

Modified Sense Amplifier based Flip-Flop(MSAFF)

This circuit is based on the popular sense amplifier based Flip-Flop which consisted of a sense amplifier stage which was used to generate S' and R' from clock and data inputs, these 2 signals were the inputs of cross coupled NAND gates which acted like an S-R flip-flop.

Figure : Modified Sense Amplifier Based Flip-Flop

The modified circuit has a similar first stage as the original sense amplifier flip-flop. The 2nd stage has 2 inverters which convert the S' and R' inputs to S and R respectively. The remaining circuit consists of a driver and a keeper stage. The driver transistors are sized larger than the keeper transistors which are disengaged during the transitions. As shown in the figure, this Flip-Flop has a mirrored circuit and is designed such that it displays symmetrical delays.

Thus, the circuit calculations are as follows:

Table : MSAFF timing analysis

MSAFF

Clock to Out delay

Setup time

Without Aging

29.408

-8

With Aging

30.172

-8

As we can see, the Clock to Q delay for this circuit is fairly large in comparison to other Flip-Flop circuits; this is because of the first stage which is used to generate S and R signals for the 2nd stage.

The total delay of the circuit would be,

Tff = 21.408 p secs before aging and Tff = 22.172 psecs after aging. As you can already see, this flip-flop shows lower increase than the other dynamic flip-flops (3.5%).

READINGS AND ANALYSIS

Comparing the data for amongst the Master-Slave Flip-Flops

Figure : Comparative readings for Static Flip-Flops

It is clear from these readings that the Modified Transmission Gate Master Slave Flip-Flop shows the overall performance with least impact to aging. Though the Clocked CMOS flip-flop shows lower change in 0 to 1 transition, it has the highest increase in 1 to 0 transitions thus making the average change of the MODMSFF better. Also, MODMSFF shows lower delay than other circuits.

Comparing the data for Pulse triggered Flip-Flops

Figure : Comparative readings for Dynamic Flip-Flops

As we can see here, the overall delay of HLFF is the lowest of the series. However, this device shows a significant amount of increase. As for the SDFF, it has a high delay but a low increase in 0 to 1 transition and a significant decrease to aging in 1 to 0 transitions. This is because, in 1 to 0 transition, the setup time is lower than the Clock to Q delay, and due to aging degradation, it degrades such that the setup time goes more negative and thus, reducing the overall delay even further.

Comparing all the Flip-Flops in terms of percentage increase due to the effect of aging:

Figure : Comparison of all Flip-Flops in terns of percentage increase due to aging

From this figure, it is clear that MODMSFF shows the best resistance to the effect of aging. Also, it should be noticed that most Flip-Flops show a higher increase in 1 to 0 transitions. This is due to the effect of PBTI on the NMOS transistors. Most of the previous literatures on aging of flip-flops have calculated the effect of NBTI alone and thus ignored the calculations for 1 to 0 transitions. These readings clearly show that PBTI is as serious reliability issue as NBTI. From the pulse triggered set, it should be noticed that the Modified Sense Amplifier based Flip-Flop shows the best resistance to the effect of aging. Although Semi dynamic Flip-Flop does show a decrease in delay, which is desired, its increase in 0 to 1 is comparatively higher.

DUAL THRESHOLD VOLTAGE TECHNOLOGY

By observing the figure above, it is clear that pulse triggered flip-flops can possibly get faster due to aging (SDFF showed a decrease in delay). However, most cases showed some amount of increase due to BTI variations. Inorder to achieve a Flip-Flop design that is largely resistant to aging, it is important to make such design changes that would reduce the degradation on the critical path of the transistor. We already know that Dual threshold voltage or Dual Vth is already a popular method for a robust design. With dual Vth designs, the circuit can be made High VT, which would reduce the leakage but make the device slower, or use Low Vt design having the opposite effect. Dual threshold voltage is also easy to fabricate by adding an additional mask layer during fabrication.

As we already know, the setup time of pulse triggered latches is negative due to the delay caused by the pulse generating circuit. Thus, by choosing to make these paths as low Vt, we can making their degradation higher and thus decrease the overall setup time of the circuit. Subsequently, the remaining circuit can be designed as high Vt which would compensate for the degradation.

Let us observe the readings of pulse triggered latches with these readings.

Dual Vt Hybrid Latch Flip-Flop

Figure : Dual Vt Hybrid Latch Flip-Flop

From the above circuit, the circuit highlighted in the blue box would be made low Vt, and the remaining circuit would be designed for high Vt . Thus, the negative clock generating block, block 110 would be low Vt, while block 130, the sample and hold block would be High Vt.

Table : Dual Vt HLFF timing analysis for 1 to 0 transition

Dual Vt HLFF (1 to 0)

Clock to Out delay

Setup time

Without Aging

10.949

-4

With Aging

11.381

-4

Thus, Tff = 6.949 p secs and Tff = 7.381 p secs due to aging. This computes to an increase of 6.21 %, which is relatively much lower than the original circuit.

Table : Dual Vt HLFF timing analysis for 0 to 1 transition

Dual Vt HLFF (0 to 1)

Clock to Out delay

Setup time

Without Aging

20.406

-10

With Aging

20.93

-10

Thus, Tff = 10.406 p secs and Tff = 10.93 p secs due to aging. This computes to an increase of 5.03 % which is relatively much lower than the original circuit.

Dual Vt Semi Dynamic Flip-Flop

For the Semi Dynamic Flip-Flop, we apply Dual Vt to the 2 inverters and the NAND gate generates the pulse trigger for the circuit.

Figure : Dual Vt Semi Dynamic Flip-Flop

As shown above, the highlighted box, the pulse generating circuit is made low Vt, and the rest of the circuit is designed as high Vt.

Table : Dual Vt SDFF timing analysis for 0 to 1 transition

Dual Vt SDFF (0 to 1)

Clock to Out delay

Setup time

Without Aging

35.478

-5

With Aging

36.713

-6

Thus, Tff = 30.478 p secs and Tff = 30.713. p secs due to aging. This computes to an increase of 0.77% which is relatively much lower than the original circuit's increase.

Table : Dual Vt SDFF timing analysis for 1 to 0 transition

Dual Vt SDFF (1 to 0)

Clock to Out delay

Setup time

Without Aging

8.1791

-22

With Aging

8.3591

-24

Thus, Tff = -13.8209 p secs and Tff = -15.6409 p secs due to aging. This computes to an increase of 13% decrease.

For Sense Amplifier Flip-Flop circuit, we apply High Vt to the driver circuit, and apply low Vt to the rest.

Dual Vt Modified Sense Amplifier based Flip-Flop

Figure : Dual Vt Sense Amplifier Flip-Flop

Here, transistors 251, 234, 249, 247 and 236 are designed high while the remaining circuit is designed low.

Table : Dual Vt MSAFF timing Analysis

Dual Vt MSAFF

Clock to Out delay

Setup time

Without Aging

25.938

-7

With Aging

26.498

-8

Thus, Tff = 18.938 p secs and Tff = -18.498 p secs due to aging. This computes to an overall decrease of 2.32 % for this circuit. As compared to the original circuit, this decrease is a huge achievement for the circuit performance improvement.

UPDATED READINGS

Now that we know that Dual Vt brings about an improvement in the overall delay of CMOS technology, let us compare all the Flip-Flops with Dual VT updated readings.

Figure : Dual Vt Comparative Readings of Dynamic Flip-FLops

As we can see in figure 16, there is a huge drop in the increase of delay due to aging for all Flip-Flops. There is almost 3 times drop in increase of total delay due to aging for HLFF. For SDFF, there is a negligible increase for the 0 to 1 transition. For 1 to 0 transition, the SDFF shows a decrease in total delay. Although there is an overall decrease in the increase due to aging for these two Flip-Flops, the total delay of the circuit increases by a small margin. However, Sense Amplifier based Flip-Flop is unique in this matter. The total delay of the Flip-Flop decreases by almost 12% with Dual Vt. Additionally, this Flip-Flop shows a decrease in total delay after aging.

Figure : Updated comparison of percentage increase with Dual Vt Flip-Flops

Here, we can see that Dual Vt MSAFF and Dual Vt SDFF show a reduction in total delay after aging. Although, SDFF shows a reduction in overall delay due to aging, this happens only in 1 transition, the 1 to 0 transition. However, due to circuit symmetry, MSAFF will show reduction in both transitions. Also, MSAFF the total delay of the circuit is reduced for MSAFF with the usage of Dual Vt. Thus, it is clear from this design that the Flip-Flop that shows best resistance is the Modified Sense Amplifier Flip-Flop.

CONCLUSION

In this paper, we have observed the impact of aging effects of 6 different Flip-Flop circuits. To obtain this, we calculated the aging parameter using the PTM model provided by Arizona State University and used Synopsys tools for observations and circuit construction. We calculated NBTI and PBTI at transistor specific β with supply voltage of 0.9 V for a period of 5 years at the temperature of 1000C. A total of 6 different Flip-Flop circuits we analyzed and evaluated categorized in 2 groups, Static Flip-Flops and Dynamic Flip-Flops. The main constraint for timing evaluations used here were Setup Time and Clock to Q delay, as they are the major constraints for the performance of the circuit. It was observed that the Modified Transmission Gate Master Slave Flip-Flop showed the best resistance to aging with marginal increase in both transitions. However, it was noticed that Semi-Dynamic Flip-Flop showed a decrease in Setup time and hence a decrease in overall delay of the circuit for 1 particular transition. Thus, a popular method of reliability design was applied, called Dual Threshold voltage where the Dynamic Flip-flops were applied with dual threshold voltage selectively. These resulted in a huge improvement in the overall performance of the circuit. Hybrid Latch Flip-Flop was observed to have dropped from 20 and 29 % to 5 and 6% increases due to aging for 0 to 1 transition and 1 to 0 transitions. The Semi Dynamic Flip Flop now showed a negligible amount of increase in delay for 0 to 1 transition and a significant decrease in 1 to 0 transitions. Finally, the Modified Sense Amplifier Flip-Flop which has a symmetrical output also displayed a decrease with the effect of aging. Thus, by the use of Dual Voltage, the overall delay of the circuit can be decreased and the Flip-Flop can be made aging resilient.