Proposed Three Multiplier Configurations Biology Essay

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The software, MATLAB is used to simulate the proposed modules. The different outputs, SNR and PSD of DSM1, DSM2, DSM3 and DSM4 are presented. The outputs of the proposed three multiplier configurations with error signal are exhibited. The performance of single-phase/three-phase SCs with single- input/multiple-inputs using proposed modules are presented.

4.2 Simulation Results of Proposed DSMs

The simulation results of proposed DSMs namely DSM1, DSM2, DSM3, and DSM4 are presented in this section.

4.2.1 Simulation Results of Proposed DSM1

Fig.4.1 (b) to Fig.4.1 (e) show the different outputs of the proposed DSM1 for sinusoidal signal of normalized peak amplitude xnorp (peak amplitude divided by n ) is equal to 0.5 and frequency 45Hz.which is shown in Fig.4.1 (a). Fig. 4.1(b) shows the second integrator output of the proposed DSM1, the absolute maximum value of which is 6.2V. Fig.4.1(c) shows the output of the quantizer of the DSM1. The output is a sequence of pulses of amplitude +1,-1, confirming the normal operation of the circuit. There are no continuous ones or zeros (in the expanded view) which signifies instability. Fig. 4.1(d) shows the demodulated signal of the quantizer output of DSM1. The demodulated signal is the average value of pulses at the output of the quantizer during each update period. It can be seen that the demodulated signal reproduces the sampled analog input signal. In Fig. 4.1(e) is shown the error signal and the maximum absolute value of the error signal is 0.5mV. The error in the proposed DSM1 is given by,

error= normalized input (x/n) - average value of the quantizer output (y)

The overall percentage of error (|maximum error| -100) is 0.05% for the considered example.

Figure 4.1 Outputs of Proposed DSM1 for Sine Signal. [Horizontal axis-

Time in sec., Vertical axis- Voltage in Volts, TU = 0.2442msec.,

TC = 0.1μsec., xnorp = 0.5 and n = 1.5].

Fig. 4.2(a) shows the sine signal of normalized peak amplitude 0.9 and frequency 45Hz. Fig. 4.2(b) shows the unstable condition of DSM1, when the normalized input exceeds 0.74. Under this condition the quantizer output is saturated. The average value of the output signal no longer reproduces the sampled input signal.

Figure 4.2 Instability of Proposed DSM1 [Horizontal axis- Time

in sec., Vertical axis- Voltage in Volts, TU = 0.2442msec.,

TC = 0.1μsec., xnorp = 0.9 and n = 1.5].

Fig. 4.3 shows the SNR plots of conventional DSM and DSM1. The SNR is found by using Delta-Sigma Tool Box by R.Schreier (Schreier R. (1998) for sinusoidal signals of different amplitudes (peak amplitude). The maximum SNR of conventional DSM is equal to 71.5 dB when xnorp is equal to -7dB (0.447). The dynamic input range of positive SNR is equal to 76.3dB. When xnorp is greater than

-7dB the SNR falls. When xnorp is equal to -5dB (0.56), the SNR has dropped to 39.6dB. Further increase in xnorp makes the conventional DSM unstable. Fig. 4.3 shows that the maximum SNR of proposed DSM1 is equal to 80.5dB when xnorp is equal to -3.5dB (0.668). The dynamic input range of positive SNR is equal to 89dB. When xnorp is greater than -3.5dB the SNR starts falling down. When xnorp is equal to -3dB (0.708), the SNR is equal to 79.6dB and when xnorp is equal to -2.5 dB (0.75), the SNR has dropped to 56.6dB. Further increase in xnorp makes DSM1 unstable. The safe range of DSM1 is -89dB to -3dB and DSM1 is better than conventional DSM in this range.

Figure 4.3 Comparison of SNR of Proposed DSM1 with Conventional DSM (OSR=64).

In the proposed DSM1, the signal is sampled at TU and DSM is operating at TC. Therefore, the quantizer output is at TC. The output of quantizer is passed through a running average filter which is operating at TU. The power spectral density (PSD) is found for the filter output and is shown in Fig. 4.4. The PSD gives the power spectrum of the applied load voltage. The noise floor is below -100dB and signal level is at -8dB. The PSD is drawn (Schreier R. (1998)) using FFT (Fast Fourier Transform) length of 4096 and with sampling frequency fU (1/TU) is equal to 4.096 kHz.

Figure 4.4 PSD of DSM1 (xnorp = 0.5).

4.2.2 Simulation Results of Proposed DSM2

Fig. 4.5 shows the simulation results of proposed DSM2 for a dc (x = 0.5) input signal. The simulation results for x1(k), x2(k) and y(k) and the analytical results obtained in section 3.2.2.4 of chapter 3, are the same. Fig. 4.6(c) to Fig. 4.6(e) show the different outputs of proposed DSM2 and Fig. 4.6(b) shows the second integrator output of proposed DSM1 for sine signal of normalized peak amplitude 1 and frequency 45Hz.which is shown in Fig. 4.6(a). From Fig. 4.6(b), it can be seen that in DSM1, when |xnor|>0.7 the second integrator output abruptly increases, making DSM1 unstable. Fig. 4.6(c) shows the second integrator output of DSM2, the absolute maximum value of which is less than10. Fig. 4.6(d) shows the output of the quantizer of DSM2. The output is a sequence of pulses of amplitude +1,-1 and 0, confirming the normal operation of the circuit. Fig. 4.6(e) shows the normalized average value of the quantizer output (y-n) during each sampling period. It can be seen that the demodulated signal closely follows the sampled analog input signal for the entire normalized range -1 to +1. In Fig. 4.6(f) is shown the error signal and the maximum absolute value of the error signal is 0.77mV. In DSM2 the error signal is given by,

error = normalized input (x/n)-normalized average value of the quantizer output (yn).

Therefore, overall percentage of error is equal to 0.077% for the considered example.

Figure 4.5 Outputs of Proposed DSM2 for DC Signal (x = 0.5)

[Horizontal axis- Time in sec., Vertical axis- Voltage in Volts,

TU =2 msec., TC = 0.1 msec. and n=2].

Figure 4.6 Outputs of DSM2 and Second Integrator Output of DSM1 for Sine Signal [Horizontal axis- Time in sec. Vertical axis- Voltage in Volts,

TU=0.2442msec., TC=0.1μsec., xnorp =1 and n=1.5].

Fig. 4.7 compares the SNR of conventional second order DSM and the proposed DSM2. In DSM2, the SNR never falls after certain range of input signal. The SNR steadily increases and reaches 77.7dB when xnorp is equal to 0dB. The dynamic input range of positive SNR of DSM2 is 85dB. The maximum SNR of conventional DSM is 71.5 dB when xnorp is equal to -7dB and when xnorp >-7dB, the SNR falls. For xnorp ï‚£ -7dB, the SNR plot of DSM2 almost follows the SNR plot of conventional DSM. For xnorp> -7dB, the SNR continues to increase. Considering the complete input range, the SNR of DSM2 is better than that of conventional DSM

Figure 4.7 Comparison of SNR of Proposed DSM2 with Conventional DSM (OSR=64).

The PSD is found for the filter output as in the case of DSM1 and is shown in Fig.4.8. The PSD gives the power spectrum of the applied load voltage. The noise floor is at -100dB and signal level is at -3dB. The PSD is drawn using FFT length of 4096 and with sampling frequency fU is equal to 4.096 kHz.

Figure 4.8 PSD of DSM2 (xnorp = 1).

4.2.3 Simulation Results of Proposed DSM3

The sine signal of normalized peak amplitude 1 and frequency 45Hz. is used for the simulation of DSM3. From Fig. 4.3, it is clear that the conventional DSM is needed to be replaced by DSM1 for the range -89dB to -3dB for better SNR and stability. From Fig. 4.7, it is evident that the conventional DSM is needed to be replaced by DSM2 for the range -7dB to 0dB for better SNR and stability. Since SNR of DSM1 is better in the range -7dB to -3dB (compared to DSM2), DSM2 need to take over after -3dB. Therefore, in DSM3, when |xnor| ï‚£ -3dB, DSM1 operates and when |xnor | > -3dB, DSM2 operates. It is evident from Fig. 4.9 (b) that the absolute maximum value of the second integrator output never exceeds 10. Fig. 4.9(c) shows the output of the quantizer of DSM3. The output is a sequence of pulses of amplitude +1,-1 when DSM1 is functioning. When DSM2 is functioning, the output is a sequence of pulses of amplitude +1,-1, 0. This confirms the normal operation of the circuit. Fig. 4.9(d) shows the normalized average value of the quantizer output during each sampling period. The demodulated signal reproduces the sampled analog input signal. In Fig. 4.9(e) is shown the error signal (x/n-yn) and the maximum absolute value of the error signal is 0.68mV (0.068%)

Figure 4.9 Outputs of Proposed DSM3 for Sine Signal [Horizontal axis- Time in sec., Vertical axis- Voltage in Volts, TU=0.2442msec., TC=0.1μsec.,

xnorp =1 and n=1.5].

The SNR plot of DSM3 is shown in Fig. 4.10. The SNR plot of DSM3 follows the SNR plot of DSM1 till xnorp ï‚£ -3dB. When xnorp > -3dB, the SNR plot of DSM3 follows the plot of DSM2. The dynamic input range of positive SNR of DSM3 is 89dB. DSM3 is better than the conventional DSM for the full range of input signal (-89dB to 0dB). The PSD of DSM3 is the same as that of DSM2 for xnorp=1.

Figure 4.10 Comparison of SNR of Proposed DSM3 with

Conventional DSM (OSR=64).

4.2.4 Simulation Results of Proposed DSM4

Fig. 4.11(b) to Fig. 4.11(e) show the different outputs of proposed DSM4 (third order i.e. three integrators are cascaded) for sine signal of normalized peak amplitude 1 and frequency 45Hz. which is shown in Fig. 4.11(a). From Fig.4.11(b), Fig.4.11(c) and Fig. 4.11(d) it is evident that the integrators output never increase abruptly. The upper bounds of the integrator outputs are well within the safe limits. Fig.4.11(e) shows the output of the quantizer of DSM4. The output is a sequence of pulses of amplitude +1,-1 and 0, confirming the normal operation of the circuit. Fig. 4.11(e) shows the normalized average value of the quantizer output during each sampling period. It can be seen that the demodulated signal closely follows the sampled analog input signal for the entire normalized range -1 to +1. In Fig. 4.11(f) is shown the error signal (x/n-yn) and the maximum absolute value of the error signal is 0.8mV (0.08%).

Figure 4.11 Outputs of Proposed DSM4 for Sine Signal

[Horizontal axis- Time in sec., Vertical axis- Voltage in Volts,

TU=0.2442msec., TC=0.1μsec., xnorp =1 and n=1.5].

Fig. 4.12 compares the SNR of conventional second order DSM and the proposed DSM4. In DSM4, the SNR never falls after certain range of input signal. The SNR increases with different slopes and reaches 75.9dB when xnorp is equal to 0dB.The dynamic input range of positive SNR of DSM4 is 75dB. The maximum SNR of conventional DSM is 71.5 dB when xnorp is equal to -7dB and when xnorp >

-7dB, the SNR falls. For xnorp ï‚£ -7dB, the SNR plot of DSM4 almost follows the SNR plot of conventional DSM. For xnorp> -7dB, the SNR continues to increase. For the entire input range, DSM4 is better than conventional DSM.

Figure 4.12 Comparison of SNR of Proposed DSM4 with Conventional DSM

(OSR=64).

The PSD is found for the filter output as in the case of DSM1 and is shown in Fig.4.13. The PSD gives the power spectrum of the applied load voltage. The PSD is drawn using FFT length of 4096 and with sampling frequency fU is equal to 4.096 kHz.

Figure 4.13 PSD of DSM4 (xnorp = 1).

4.3 Simulation Results of Proposed Multipliers

The simulation results of proposed multipliers namely MUL1, MUL2 and MUL3 are presented. The %error in the proposed multipliers of two sampled inputs (x and y) is given by,

(4.1)

where error = normalized ideal product (xy/n) - normalized average value of the multiplier output (zn). The feedback gain constant is also referred as Full Scale of supply voltage (FS).

4.3.1 Simulation Results of Proposed MUL1

(DSM1)1 is fed with a random signal which is sampled at 0.05sec. (TU1) and denoted as x. (DSM1)2 is fed with another random signal which is sampled at 0.01sec. (TU2) and denoted as y. The sampled random signals x and y are shown in Fig. 4.14(a) and Fig. 4.14(b) respectively. The (DSM1)1 clock period TC1 is equal to 10μsec. and (DSM1)2 clock period TC2 is equal to 0.1μsec. The random signals can take any values in the range -7 to +7. Fig. 4.14(c) shows the ideal product of the two sampled analog signals which are normalized to the full scale and is equal to. Fig. 4.14(d) shows the normalized average value of the bit stream (zn) at the output of the proposed multiplier in each sampling period (TU2). It can be seen from Fig. 4.14(d) that the normalized analog signal at the output of the proposed multiplier closely follows the normalized ideal product value. Figures 4.14(c) and 4.14(d) show the normalized product value after a delay of TU2. Fig. 4.14(e) shows the error signal ((c)-(d)) in each sampling period. The absolute maximum value of the error signal is 12.8 mV. The percentage of error signal is given by. From Fig. 4.14(e), the maximum percentage of error signal is equal to 1.28%. Two DSM1s are used for multiplication of two sampled analog signals and the result is in digital form. For considered two low frequency analog signals, the maximum absolute value of the error signal in the proposed multiplier is 1.28% when the DSM1s operating clock periods are 10μsec. and 0.1μsec. If the clock periods are lower, the accuracy will be better. However, with the considered specification, in the point of accuracy the proposed multiplier is better than the standard low cost precision multipliers and can process wider range of input signals (70% of FS). The major advantage is that it multiplies two low frequency analog signals and provides digital output useful for power electronics applications directly.

Figure 4.14 Functioning of Proposed MUL1. (Horizontal axis-Time in sec.

Vertical axis- Voltage in Volts, TU1 =0.05 sec., TU2 =0.01 sec.,

TC1 = 10μsec., TC2 = 0.1μsec. and n=10)

4.3.2 Simulation Results of Proposed MUL2

The proposed DSM based multiplier configuration 2 is simulated with TU =0.01 sec. and TC = 0.1μsec. Fig. 4.15(a) shows the sine signal of peak amplitude

7V and frequency 1 Hz (x) which is the multiplicand signal. Fig. 4.15(b) shows the sine signal of peak amplitude 7V and frequency 0.1 Hz (y) which is the multiplier signal. Fig. 4.15(c) shows the ideal product (normalized to FS) of the two analog signals and Fig. 4.15(d) shows the average value (normalized to FS) of the bit stream at the output of the proposed multiplier in each sampling period. It can be seen from Fig. 4.15(d) that the normalized analog signal at the output of the proposed multiplier closely follows the normalized ideal product value. Figures 4.15(c) and 4.15(d) show the normalized product value after a delay of TU. The error signal ((c)-(d)) is shown in Fig. 4.15(e). The absolute maximum value of the error signal is 0.344mV (0.0344%).

Figure 4.15 Functioning of Proposed MUL2. (Horizontal axis-Time in sec.,

Vertical axis- Voltage in Volts, TU =0.01 sec., TC = 0.1μsec. and n=10)

4.3.3 Simulation Results of Proposed MUL3

Fig. 4.16 shows the ideal product normalized to FS, actual product of the proposed multiplier normalized to FS and error signal of two sampled low frequency signals x and y with TC =0.1μsec. and TU = 0.01sec. Figures 4.16(c) and 4.16(d) show the normalized product value after a delay of TU. The ranges of x and y are -7 ï‚£ x ï‚£ +7 and -10 ï‚£ y ï‚£ 10 respectively. From Fig. 4.16(e) the percentage of overall maximum error signal is 0.026%.

Figure 4.16 Functioning of Proposed MUL3. (Horizontal axis-Time in sec.,

Vertical axis- Voltage in Volts, TU =0.01 sec.

TC = 0.1μsec. and n=10)

4.4 Simulation Results of Proposed SCs

The simulation results of proposed single-input single-phase SC, two-inputs single-phase SC, single-input three-phase SC and two-inputs three-phase SC are presented in this section.

4.4.1 Simulation Results of Proposed Single-Input Single-Phase SC

Figs. 4.17(b) to 4.17(d) show the different outputs of proposed SC when the normalized control signal is a random signal between  1 which is shown in Fig. 4.17(a). From Fig. 4.17(b) it can be seen that the second integrator output is always less than 10. Fig. 4.17(c) shows the normalized ideal output of the SC. Fig. 4.17(d) shows the normalized actual output of the SC which is the average value of the pulses at the bridge output normalized to FS over each sampling period. The error signal is shown in Fig. 4.17(e) and is less than 40mV ( )

Figure 4.17 Outputs of Proposed Single-Phase SC with Random Input Signal

(Horizontal axis-Time in sec., Vertical axis-Voltage in Volts,

TU = 0.2442msec., TC =0.1μsec., n=1.5 and VS = 48V).

4.4.2 Simulation Results of Proposed Two-Inputs Single-Phase SC

The crane control system is taken as example. Fig. 4.18(a) shows the control signal from the operator. Fig. 4.18(b) shows the signal from the gear limit switches. The signal from the gear limit switches reduces the control signal to the safe limit. This is achieved by multiplying the two signals. From t=0 to t=0.1, the safety switches reduces the control signal to 50% and reduction in other time slots can be seen from Fig. 4.18(b). Fig. 4.18(c) shows the ideal output of the SC (n=1). Fig. 4.18(d) shows the actual output of the SC which is the average value of the pulses at the bridge output over each sampling period. Fig. 4.18(e) shows the error signal and the maximum value of the error signal is 20mV (0.04%).

Figure 4.18 Outputs of Proposed Single-Phase SC with Two Input Signals

(Horizontal axis- Time in sec., Vertical axis- Voltage in Volts,

TU = 0.01sec., TC = 1μsec., n = 1 and VS = 48V).

4.4.3 Simulation Results of Proposed Single-Input Three-Phase SC

The proposed three phase SC is simulated with n=1.1, fU=2.048 kHz and fC=10MHz. The sampled sinusoidal input signal of normalized peak amplitude of 1V and frequency 13Hz. is used for the simulation. Fig. 4.19 shows three-phase (a-b-c) output of the quantizer and the difference in phase voltages. The outputs lead by 120° in the phase sequence a-b-c. The overall maximum difference in phase voltages for the considered example is 6mV.

Figure 4.19 Three-Phase Voltages of the Proposed Three-Phase SC. (x-axis:

Time in sec., y-axis: Voltage in volts for (a), (c), (e), (g),(h),(i) and radians for (b), (d), (f), TU=0.4884msec., TC=0.1μsec., xnorp=1, n = 1.1)

Comparison of SNR of three-phase SC presented by Glen Luckjiff and Ian Dobson (2005), and proposed SC with variation of normalized input amplitude of sinusoidal signal is shown in Fig.4.20. The increased attenuation of noise transfer function for dc signal reduces the quantization noise in the signal band. Therefore, if the DSM is operated with dc input and low clock period for sufficient time (update period) the average value of the digital output will be good approximation of dc input signal. The merit of operating on dc signal dominates from -50dB to -12.5dB of input signal and hence SNR of proposed SC is better than that reported by Glen Luckjiff and Ian Dobson (2005), in this range. In the proposed circuit, the operating time of DSM is proportional to the amplitude of sampled analog input signal. When the magnitude of sampled analog input signal decreases the DSM circuit operates for shorter time and so the quantization noise level increases and SNR decreases. The effect of controlling the operating time of DSM, proportional to sampled analog input signal, dominates from -13dB to -1.5dB (0.84) of input signal and hence the SNR of proposed SC is lesser than the three phase SC presented in Glen Luckjiff and Ian Dobson (2005), in the given range. As the input increases from -2dB to 0dB, the SNR of SC presented in Glen Luckjiff and Ian Dobson (2005), falls and becomes unstable because the second integrator output increases rapidly which overload the quantizer. In the proposed SC for input ranging from 0.84 to 1(16% of full scale), the SNR never falls but slowly increases and reaches 64.3dB when the input is 1.

Figure 4.20 Comparison of SNR (OSR=32).

The PSD of output signal of proposed SC (load voltage) is shown in Fig.4.21. The PSD is found for the filter output as in the case of DSM1. The signal level is -2 dB and the noise floor is -100dB.

Figure 4.21 Power Spectral Density (xnorp = 1) of Proposed Three-Phase SC.

4.4.4 Simulation Results of Proposed Two-Inputs Three-Phase SC

The proposed three phase SC with two input signals is simulated with n=1, fS=4.095 kHz and fC=10 MHz. One input signal is a sine waveform which is used to control the operating period of DSM and the other is a square waveform which is fed to the input of DSM after sampling. Fig.4.22 shows three phase (a-b-c) output of the quantizer. The magnitudes of the three phase outputs are equal and proportional to the product of the input signals during each sampling period. The outputs lead by 120° in the phase sequence a-b-c.

Figure 4.22 Functioning of Proposed Three-Phase SC with Two Input

Signals. (Horizontal axis- Time in sec., Vertical axis- Voltage in volts,

TU=0.2442msec., TC=0.1μsec. and n = 1)

The differences between the magnitudes of the phase voltages are shown in Fig.4.23. The overall maximum difference in phase voltages for the considered example is 18mV.

Figure 4.23 Differences in Phase Voltages of Three-Phase

SC with Two Input Signals (Horizontal axis- Time in sec.,

Vertical axis- Voltage in volts).

4.5 Conclusion

From the simulation results of proposed DSMs, DSM3 is more suitable for replacement of conventional second order DSM. The dynamic input range of positive SNR of DSM3 is 89dB. DSM3 is stable for the full range of normalized input signal (-1 to +1) and maximum value of SNR is 80.5dB. In the PSD plot the noise floor is well below the signal level. From the simulation results of proposed multipliers, MUL3 is more suitable to use in multiple inputs single-phase/three-phase SCs. The range of inputs of MUL3 is 70% and 100% and the maximum error signal of MUL3 is 0.026% for the considered input signals.

The performance of proposed, single-input single-phase SC and two-inputs single-phase SC are the same as the performance of DSM3 and MUL3 respectively. The proposed single-input three-phase SC can handle full range of normalized input (-1 to +1) and the SNR never falls after certain range of input signal. As xnorp increases towards 1, the SNR steadily increases and reaches 64.3dB when xnorp =1. The spectral performance is comparable with the three-phase SC which is presented in Glen Luckjiff and Ian Dobson (2005). In the case of two-inputs three-phase SC, the maximum difference in the phase voltages is equal to 18mV for the considered two input signals.

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