# Most Telecommunication Devices Are Portable Biology Essay

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Many modern electronic devices are mixed-signal systems where analog signals are converted into digital data for processing in the digital domain. Therefore, the performance of the system relies on the performance of analog-to-digital (ADC) converters. Telecommunications device demands for high-resolution and high-speed converters. Advancement in CMOS technology has made the operating voltage of integrated circuits becomes lower every year. By lowering the power supply, it reduces the signal swing but increase the power consumption.

Nowadays, most telecommunication devices are portable and require low power consumption battery life can be maximized. All of these requirements imply that the op-amps, the core of practically all analog-to-digital converters, need to have high speed, high gain, large output swing, and low noise, while can operate at low supply voltage and consume as little power as possible. Moreover, for fully differential topology requires a common-mode feedback (CMFB) amplifier to sense common-mode output voltage, invert the phase, and feedback to op-amp(Wongkomet et al., 2005). This consumes additional power because the CMFB amplifier must be as fast as the op-amp(Wongkomet et al., 2005).

## 1.2 Problem Statement

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In this project, it is desirable that a low power design is achieved. In order to reach the low power design, telescopic topology has been chosen. Telescopic op-amp has the advantages of low power compare to folded cascode op-amp because telescopic op-amp only has single current branch. Disadvantage of a telescopic op-amp is severely limited output swing. It is smaller than folded cascode because the tail transistor directly cuts into output swing from both sides of the operational amplifier. According(Kumar, 2009), fully differential topology is needed because it's increased the output swing due to the change in phase between differential outputs. The output voltage swing increases by a factor of two over a single-ended output with the same voltage swing.

To design a 1.5 bit pipelined ADC for Worldwide Interoperability for Microwave Access (WiMAX) application, op-amp bandwidth needs to be double from WiMAX operating frequency. Hence, the bandwidth requirement is 44MHz.

## 1.3 Objectives

The main objectives for this project are:

To design a Telescopic Op-Amp with CMFB (Common Mode Feedback).

To achieve 44MHz bandwidth according to WIMAX specification.

To achieve minimum 48dB DC gain.

To simulate the characteristics of the Op-Amp that has been design.

To perform a single 1.5 bit stage pipelined ADC conversion using the designed op-amp and CMFB.

## 1.4 Scope

This project can be categorized into four major parts. First part is the op-amp design. One of requirement of the op-amp is it must have 8 bit resolutions which translate to 48dB DC gain. For Wimax application the op-amp requires minimum bandwidth of 44MHz. To ensure stability it is required that the op-amp must have phase margin in the range of 50 degrees to 70 degrees.

Second part is to design common mode feedback (CMFB) for the op-amp. Two-stage op-amp normally requires a common-mode feedback amplifier to sense common mode output voltage, invert the phase, and feedback to the first stage. This consumes additional power because the CMFB amplifier must be as fast as the main amplifier.

Third part is to simulate the complete design to get the characteristic of the op-amp. Characteristics of op-amp such as Common Mode Rejection Ratio, Power Supply Rejection Ratio, power consumption and slew rate are needed to measure the performance of the op-amp.

The last part is to use the op-amp and CMFB and other blocks to perform a 1.5bit stage pipelined ADC. Simulate these designs to ensure the op-amp and CMFB able to 1.5 bit ADC conversion with 44MHz sampling clock.

## 1.5 Thesis Outline

Chapter 2 discuss the literature review on 1.5 bit/stage pipelined ADC, Multiplying Digital to Analog Converters, telescopic topology and common mode feedback.

Chapter 3 focus the methodology on designing fully differential telescopic op-amp. In this chapter will show the details calculation on gain, small signal analysis, frequency response, gain-bandwidth product and output resistance. While transistor parameters were obtained trough simulations.

Chapter 4 provide the result of this project. The designed op-amp characteristics simulations are shown in this chapter as well as the 1.5 bit/stage pipelined ADC simulation to verify the design.

Lastly, Chapter 5 will conclude this dissertation by discussion, future work and conclusion.

## CHAPTER 2

## LITERATURE REVIEW

## 2.1 1.5 Bit/Stage Pipelined ADC Architecture

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1.5bit_pic.PNG

Figure 2.1: 10 bit pipelined ADC with 1.5 bit/stage architecture

Pipelined ADC topology is a popular option for ADCs which require resolutions on the order of 8-14 bits and sampling rates between a few MS/s to hundreds of MS/s. The popularity of the topology can be attributed to its relatively simple and repetitive unit structure, as well as a significant reduction in the number of comparators required to achieve a fixed resolution when compared to other Nyquist rate data converters such as Flash, and Folding + Interpolating based converters.

Figure 2.1 shows how a 10 bit pipelined ADC is construct using repetive unit of 1.5 bit/stage architecture. Each 1.5 bit/stage will gives 2 bit output. Normally 2 bits will give 4 combinations which are 00, 10, 10 and 11. The architecture is call 1.5 bit because; its only gives 3 combinations (00, 01 and 10) instead of 4 combinations.

The 1.5 bit/stage ADC can divide into two major building blocks, which are ADC or sub-ADC and Multiplying Digital-to-Analog Converter (MDAC). The sub-ADC has two comparators which compares the input with reference voltage and gives two bits digital output. Pipelined ADC uses switched capacitor configuration because it is relatively simple, but it can do mathematical operation such as subtraction and multiplication simultaneously. Combination of sample and hold, subtraction, gain and DAC function into a single switched capacitor circuit are call MDAC as shown in Figure 2.1.

## 2.2 1.5 Bit Stage Pipelined ADC operation

The operation for 1.5 bit/stage can be summarized as Table 2.1. The regions of operation are determined by the comparator outputs in the sub-ADC. If, the output of sub-ADC is 10 then MDAC will perform. When the comparator detect that is in between and, the comparator send output 01 to MDAC to perform operation. Lastly, the MDAC will perform when the comparators detect.

Table 2.1: 1.5 bit/stage transfer function (Yuan et al., 2007)

## VIN

## Region

## Residue

## 10

## 01

## 00

## 2.3 Multiplying Digital-to-Analog Converter (MDAC)

single ended MDAC.PNG

Figure 2.2: Single-ended Multiplying Digital-to-Analog Converter (Ahmed, 2010)

Using a single-ended Multiplying Digital-to-Analog Converter as shown in Figure 2.1 as example the operation 1.5 bit/stage can be explain in details. Sample phase are represent by É¸1, while hold phase represent by É¸2. Switch Sa, Sb and Sc are control by a logic function. For example when the comparator signal 10 the logic function make switch Sa close while switch Sb and Sc remain open. Switch S1 to S7 are control by sampling clock according to their phase.

When input is between and, comparator output = 01 and switch Sc closed. During É¸1, switch S3, S4 and S7 are closed.

During É¸2, switch S1, S2, S5 and S6 are closed. C1 is discharged to ground, therefore by charge conservation.

Therefore,

If C1 = C2,

When input exceeds, comparator output = 10 and switch Sa closed. Over range error, therefore subtract from input. During É¸1, switch S3, S4 and S7 are closed.

During É¸2, switch S1, S2, S5 and S6 are closed. C1 is charged to, therefore by charge conservation.

Therefore,

If C1 = C2

When input below - , Comparator output = 00 and switch Sb closed. Under range error, therefore add from input. During É¸1, switch S3, S4 and S7 are closed.

During É¸2, switch S1, S2, S5 and S6 are closed. C1 is charged to, therefore by charge conservation.

Therefore,

If C1 = C2,

From (2.1), (2.1) and (2.3), the transfer function of 1.5 bit/stage pipelined ADC can be plotted as Figure 2.3.

1.5bitstage_transfer_fucnction.PNG

Figure 2.3: 1.5 bit/stage pipeplined ADC transfer function

## 2.4 Telescopic Op-amp Topology

OPamp.png

Figure 2.4: Telescopic op-amp topology

Telescopic op-amp has a good voltage gain which comparable to two stage op-amp. This structure has been called a "telescopic cascode" op-amp because the cascode transistors are connected between the power supplies in series with the transistor in the differential pair, resulting in which the transistors in each branch are connected along the straight line. The main advantage of telescopic cascode op-amp is that they have the highest speed compare to other topology. Table 2.2, shows the performance of four different op-amp topologies.

Disadvantage of telescopic topology is it reduces the common mode input range(Gray et al., 2001). To improve the common mode input range, P-channel transistors were used as the differential input. By using P-channel as the input the speed of the op-amp is lower than using N-channel input because, P-channel device have lower mobility than N-channel device.

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Examples of our workTable 2.2: Performance of four different topologies (Razavi, 2001)

Topology

Gain

Output swing

Speed

Power consumption

Telescopic cascode

Medium

Medium

Highest

Lowest

Folded cascode

Medium

Medium

High

Medium

Two stage

High

Highest

Low

Medium

Regulated cascode

High

Medium

Medium

High

Telescopic configurations were considered since we required at least one cascode stage for gain on the order of (gmro)2. A high swing configuration still needs to be used to insure that all the devices in the stage are saturation. In comparing the two topologies, the folded cascode has more current legs and more devices in the signal path. This leads to larger static current and more noise contributors. On the other hand, the telescopic configuration has half as many current legs and fewer devices.

Telescopic operational amplifiers shown in Figure 2.4, all transistors are biased in saturation region. Transistors MP1 - MP3, MN2 - MN4, and tail current source MP0 must have at least Vdsat to offer good common - mode rejection, frequency response and gain (Mortazavi et al., 2001).

Telescopic op-amp is clearly the choice for high bandwidth and low power 1.5 bit/stage pipelined ADC design. The designed telescopic op-amp is use as gain stage in MDAC building blocks. The op-amp is configured as fully differential op-amp. Hence, common mode feedback is needed to stabilize the op-amp output common mode.

## 2.5 Common Mode Feedback

Previously, circuits have mainly one input and one output and both referred to ground. Low voltage power supply makes single ended circuits very difficult to perform optimally. An alternative to single-ended circuits is to use fully differential circuits. To double the output swing a fully differential circuit are used. The output terminals of fully differential circuits are equal and opposite polarity. Additional properties of fully differential circuits are: improved output swing, linearity and common-mode rejection ratio (CMRR).

CMFB_concept.PNG

Figure 2.5: Conceptual block diagram of the CMFB loop(Gray et al., 2001)

A CMFB circuit, in a fully differential circuit, is generally needed for two reasons. First, to control the common mode voltage at different nodes that cannot be stabilized by the negative differential feedback. This is usually chosen as a reference voltage yielding maximum differential voltage gain and maximum output voltage swing. Second, to suppress the common mode components, that tends to saturate different stages, through applying common mode negative feedback.

From Figure 2.5, the task of CMFB can be divided into three operations which is sensing the output common mode (CM) level, comparison with a reference voltage and returning the error to the amplifier's bias network. The propose CMFB circuit for this work is shown in Figure 2.6. The CMFB has the same architecture as the op-amp but transistor MP3 were split into two transistors MP3a and MP3b. Therefore, (W/L)MP3a and (W/L)MP3b is equal to half of (W/L)MP1. Both outputs from the op-amp are connected to the gate of transistors MP3a and MP3b. Transistor MP3a and MP3b sense the output common mode level from the op-amp, while transistor MP1 compare it with reference voltage Vref and return the error to the op-amp through Vcmc.

CMFB.png

Figure 2.6: Propose common mode feedback circuit

## CHAPTER 3

## TELESCOPIC OP-AMP WITH COMMON MODE FEEDBACK DESIGN METHODOLOGY

## 3.1 Telescopic Op-Amp with CMFB Design Flow

Design Flow.png

Figure 3.1: Telescopic op-amp with CMFB design flow

## 3.2 Gain and Bandwidth

Designing an op-amp for WiMAX ADC application requires very high bandwidth. For this design, the op-amp bandwidth should be two times bigger than WiMAX operating frequency because of the Nyquist sampling theorem. The Nyquist sampling theorem provides a prescription for the nominal sampling interval required to avoid aliasing. It may be stated simply as follows:

The sampling frequency should be at least twice the highest frequency contained in the signal. Or in mathematical terms: (Olshausen, 2000)

Where is the sampling frequency (how often samples are taken per unit of time or space), and is the highest frequency contained in the signal. WiMAX operates at 22MHz; therefore the bandwidth for this op-amp is 44MHz.

Table 3.1: Op-amp gain requirement

Number of bits

1

2

3

4

5

6

7

8

9

Gain

2

4

8

16

32

64

128

256

512

Gain(dB)

6

12

18

24

30

36

42

48

54

The op-amp voltage gain can be determined by the number of bits. For example, an 8 bits ADC requires voltage gain of = 256 or 48dB. Table 3.1 shows the op-amp voltage gain requirement according to number of bits.

## 3.3 Telescopic-Cascode Topology

A simple single stage op-amp has a low gain which is. Usually active load is used; therefore the gain is equal to or generally. The total output resistance is parallel of NMOS output resistance and PMOS output resistance. To increase the gain, telescopic topology were chose. Transistor MP1 and MP2 from Figure 3.2 work as cascode amplifier, while transistor MN1 and MN2 works as cascode active load. For example, a basic single stage op-amp has gain. A telescopic topology can achieve gain equal to = 400 with only one stage. Adequate voltage gain is a requirement in a given application to achieve the desired accuracy in the closed-loop gain.

OPamp.png

Figure 3.2: Telescopic op-amp

Telescopic topology has high voltage gain which comparable to 2-stage op-amp. Due to its design with only single stage, telescopic op-amp consumes less power compare to other op-amp topology. Other main advantages of telescopic op-amp is that the can be designed so that the signal variations are entirely handled by the fastest-polarity transistors in a given process.

By stacking the transistor in cascode, telescopic op-amp suffers poor common-mode input range and small output swing. Poor common-mode input range can be solved by using PMOS input instead of using NMOS input. Fully differential op-amp improves the output swing.

## 3.4 Small Signal Analysis

Consider Figure 3.2 has a general voltage gain, where is the short circuit transconductance and is the total load resistance from the output terminal. From Figure 3.2, the transconductance is equal to, which is the transconductance of the input transistor. The total output load is equal to total resistance of the NMOS and PMOS transistors looking from the output.

(3.1)

Figure 3.3 shows the equivalent small signal circuit to calculate the output resistance.

RL.png

Figure 3.3: Small signal equivalent circuit for NMOS transistors

To calculate the total output resistance, connect a test voltage to the output and all DC bias voltage must be grounded. By performing KVL at the output;

(3.2)

The total supply current, is equal to;

(3.3)

From (3.2),

(3.4)

Voltage drop at resistor ;

(3.5)

Voltage drop at resistor ;

(3.6)

From Figure 3.3;

(3.7)

Substituting (3.5), (3.6) and (3.7) into (3.2) gives;

(3.8)

(3.9)

Therefore, output resistance;

(3.10)

Similarly the output resistance for the PMOS transistor looking from the output is equal to;

(3.11)

Substituting (3.10) and (3.11) into (3.1) gives;

(3.12)

Therefore, voltage gain for telescopic op-amp;

(3.13)

Voltage gain for telescopic op-amp in Figure 3.2 can be simplified designing. By designing, the internal output resistance for MP1 and MP2 will be equal. Therefore, the voltage gain can be simplified as.

## 3.5 Frequency response

Figure 3.4 shows the equivalent circuit for frequency response, where. equals to which is a Miller capacitance looking from the input. equals to , while . The total capacitance at the output is while is the load resistance looking from the output, which is equivalent to.

freq_response.png

Figure 3.4: Frequency response equivalent circuit

Performing KCL at node and;

(3.14)

(3.15)

Simplifying the equation;

Rearrange (3.14);

Rearrange (3.15);

Substituting (3.17) and (3.18) into (3.16) gives;

Simplifying (3.19);

Second order transfer function;

Comparing (3.21) with denominator (3.20) gives;

By designing the second dominant pole far away from the first dominant pole;

Therefore;

The value ofand is very small, thereforeand (3.22) can be simplified as;

Substituting (3.26) into (3.23) gives;

From the analysis, telescopic topology has two dominant poles at and, unity gain frequency occurs at (Jiang et al., 2003). In order to get higher bandwidth, should be outside the unity gain frequency.

## 3.6 Gain-bandwidth product (GBW)

Equation (3.28) shows the relations ship of unity gain frequency and gain-bandwidth product. From previous chapter, we know that unity gain frequency occurs at.

By substituting into (3.28), we get

Transconductance equal to

Substituting (3.30) into (3.29), then solve the equation for

Using the relationship of gain-bandwidth product and unity gain frequency, we can determine current that following through MP1. Equation (3.29) shows the relationship of voltage gain and bandwidth where else equation (3.13) did not. By using equation (3.29), such op-amp with the desired voltage gain and bandwidth can be design.

## 3.7 Transistor characteristics

CUT_Nmos_id_vgs_wave.png

(a)

CUT_id_vds_wave_combi.png

## (b)

Figure 3.5: (a) NMOS (b) PMOS

In op-amp design, it is important to get the transistors characteristics by simulating the curve. From the curve we can determine the value of and provided we already have all the transistors voltage level. Table 3.2, shows the voltage level for transistor in the op-amp. From the specification, the input common mode and output common mode is 1.2V. Using the specification, voltage drop across drain and source for each transistor can be set as Table 3.2. Therefore, the voltage level for source of:-

## =

Then we can obtain

Table 3.2: Transistors voltage level

## Â

VG

VD

VS

|VGS|

|VDS|

MP0

2

2.5

3.3

1.3

0.8

MP1

1.2

1.8

2.5

1.3

0.7

MP2

0.6

1.2

1.8

1.2

0.6

MP3

1.2

1.8

2.5

1.3

0.7

MP4

0.6

1.2

1.8

1.2

0.6

MN1

2

1.2

0.6

1.0

0.6

MN2

1.0

0.6

0

1.0

0.6

MN3

2

1.2

0.6

1.0

0.6

MN4

1.6

0.6

0

1.0

0.6

Repeat (3.32) and (3.33) for every transistor to get the result as in Table 3.2. Using the value of from (3.33), from (3.31) and we can plot the curve for to obtain and. The transistors voltage level is very useful to determine the value of W, L, VGS, VDS and even bias voltage for each transistor.

CUT_Nmos_id_vgs_cir.png

(a)

CUT_Pmos_id_vgs_cir.png

(b)

Figure 3.6: Transistor characteristics circuit (a) NMOS (b) PMOS

When deciding the voltage level for each transistor, it is important to consider the operating region for each transistor. For example, transistor - are bias to operate in the saturation region. While, transistor - are bias to operate in the linear region. Correct operating region for every transistor will ensure the op-amp to work optimally and provide good voltage gain

## CHAPTER 4

## RESULT AND CHARACTERISTICS SIMULATION

## 4.1 Op-amp Characteristics Summary

Table 4.1: Op-amp characteristics summary

Item

Test Condition

Simulation Result

DC Gain (dB)

CL = 1pF

41

Bandwidth (MHz)

CL = 1pF

54.71

Unity Gain

Frequency(GHz)

CL = 1pF

3.681

Phase margin (degrees)

CL = 1pF

44.81

CMRR (dB)

R1= 100kÎ©, R2= 1kÎ©

40.81

PSRR (dB)

R1= 100kÎ©, R2= 1kÎ©

-20.83

Slew Rate (V/Î¼s)

VIN = 0.5 Vpeak-to-peak

CL = 1pF

R1= 100kÎ©, R2= 1kÎ©

2130

Rise Time (ns)

VIN = 0.5 Vpeak-to-peak

CL = 1pF

R1= 100kÎ©, R2= 1kÎ©

0.147

Settling Time (ns)

VIN = 0.5 Vpeak-to-peak

CL = 1pF

R1= 100kÎ©, R2= 1kÎ©

7.5

Common Mode Input Voltage Range (V)

N/A

0.8

(1.2V to 2.0V)

Maximum Output

Voltage (V)

N/A

1.854

Current consumption (mA)

VOUT = 1.2V

112

## 4.2 Telescopic-Cascode Operational Amplifier with CMFB

Circuit_all.png

Figure 4.1: Telescopic op-amp circuit

Figure 4.1 shows the telescopic op-amp circuit and the naming for each transistor. From Figure 4.1, MN1- MN4 work as load transistors. To increase the voltage gain, these transistors were design in triode region so they can provide good load for the op-amp. Cascode configuration in telescopic topology is known for its high voltage gain comparable to two stage op-amp.

Table 4.2: W and L for op-amp

Transistor

W(Âµm)

L(Âµm)

Multiplier

MP0

74.05

0.30

48

11848

MP1

89.65

0.30

20

5976.67

MP2

77.75

0.30

32

8293.33

MP3

89.65

0.30

20

5976.67

MP4

77.75

0.30

32

8293.33

MN1

76.25

0.34

40

8970.59

MN2

76.25

0.34

40

8970.59

MN3

76.25

0.34

40

8970.59

MN4

76.25

0.34

40

8970.59

There are two dominant poles for telescopic topology, which are (3.26) and (3.27). Pole contributes to the bandwidth, while can cause some problem in the frequency response if it is designed properly. The pole that contributes to is the total internal capacitance between MP1 and MP2 where. Pole has been designed outside the unity frequency so it does not give any effect to frequency response.

Table 4.3: Op-amp DC operating point

## Â

ID(mA)

VGS(V)

VDS(V)

VDSAT(V)

VTH(V)

MP0

112

1.3000

0.7949

0.4841

0.6473

MP1

56

1.3050

0.677

0.4875

0.6473

MP2

56

1.1920

0.614

0.4124

0.6473

MP3

56

1.3050

0.677

0.4875

0.6473

MP4

56

1.1920

0.614

0.4124

0.6473

MN1

56

0.9998

0.6139

0.1643

0.7688

MN2

56

1.0000

0.6002

0.1644

0.7688

MN3

56

0.9998

0.6139

0.1643

0.7688

MN4

56

1.000

0.6002

0.1644

0.7688

Table 4.1 and 4.2 show all the component parameters for the design and its DC operating point. To achieve 44MHz bandwidth, 56mA of current is needed support this high bandwidth. To ensure that all transistors are working their correct region must be bigger than.

CMFB_cir.PNG

Figure 4.2: Common mode feedback circuit

The common mode feedback for this work uses the same topology as the op-amp but with minimal changes. CMFB needs to be same topology, transistor dimension and current consumption so the CMFB will be as fast as the op-amp. Transistor MP3 has been split in to two transistors MP3a and MP3b and connected op-amp output to sense the common mode level.

Table 4.4: W and L for CMFB

Transistor

W(Âµm)

L(Âµm)

Multiplier

MP0

74.05

0.30

48

11848

MP1

89.65

0.30

20

5976.67

MP2

77.75

0.30

32

8293.33

MP3a

89.65

0.30

10

2988.33

MP3b

89.65

0.30

10

2988.33

MP4

77.75

0.30

32

8293.33

MN1

76.25

0.34

40

8970.59

MN2

76.25

0.34

40

8970.59

MN3

76.25

0.34

40

8970.59

MN4

76.25

0.34

40

8970.59

## 4.3 DC Gain and Frequency Response

gain_circuit_CUT.png

Figure 4.3: DC gain and frequency response test circuit

DC gain and frequency response can are simulated by connecting the component as Figure 4.3. For this simulation, 1pF capacitor is connected to each of the output terminal as load. Figure 4.4, shows that the telescopic op-amp has 41dB DC gain and 54.71MHz of bandwidth measured at -3dB. Phase margin are measured when the unity gain frequency occur at 3.681GHz. Phase margin is equal to 44.81° when measured at unity gain frequency.

gain_41db_wave_CUT.png

Figure 4.4: DC gain and frequency response plot

## 4.4 Common Mode Rejection Ratio (CMRR)

Common mode rejection ratio (CMRR) is an important op-amp characteristic. CMRR is defined as the ratio of differential gain (Adm) to the common mode gain (Acm). Figure 4.5, shows the test circuit to measure CMRR. In real world measurement the value of resistor R1 and R2 must match within 1ppm (0.0001%) to measure CMRR > 100dB.

CMRR_cir_theory.PNG

Figure 4.5: Common mode rejection ratio test circuit

From Figure 4.5, the changes at the output terminal VOUT can be express as

By selecting R1 >> R2. Therefore, . (4.1) can be simplify as

CMRR can be express as

The selected value for resistor R1 and R2 for CMRR simulation is 100kÎ© and 1kÎ© respectively. When resistor R1 value is much bigger than the value of resistor R1, the test circuit will operate like non-inverting amplifier. Therefore, CMRR can be measured as. As a result, the telescopic op-amp has a CMRR of 40.81dB.

Screenshot-Projects CMRR_smallerL.png

Figure 4.6: Common mode rejection ratio simulation result

## 4.5 Power Supply Rejection Ratio

PSRR_cir.PNG

Figure 4.7: Power supply rejection ratio test circuit

Power supply rejection ratio (PSRR) is defined as ratio of changes in supply voltage to changes of output. For example, if the output voltage changes of X volts when the supply voltage changes of Y volts. Then PSRR is defined as Y/X in decibel. To simulate PSRR, the op-amp is connected as non-inverting amplifier as in Figure 4.7. At the supply, AC voltage is added with the DC supply voltage to simulate the changes in supply voltage. PSRR is equal to. Figure 4.8, shows the simulation result for PSRR measurement. The designed op-amp has a PSRR of 20.83dB.

PSRR_wave.PNG

Figure 4.8: Power supply rejection simulation result

## 4.6 Slew Rate, Rise Time and Settling Time

SR_cir.PNG

Figure 4.9: Slew rate, rise time, settling time test circuit

Slew rate, rise time and settling time can be measured using the op-amp configured in non-inverting configuration with unity gain. The closed loop gain for op-amp configured as Figure 4.9 is. If the value of resistor R1 >> R2, the closed loop gain can be simplify as. For this simulation, the input is voltage pulse with 0.5Vpeak-to-peak and the value for resistor R1 and R2 are 100kÎ© and 1kÎ© respectively.

Rise time is commonly defined as the time for a waveform to go from 10% to 90% of its final value (Nise, 2008). Slew rate is defined as Î”V/tr, where tr is rise time and Î”V is voltage difference measured at 10% to 90% of its final value. While settling time is measured from the voltage begin to rise until it's stabilized.

SR_wave.PNG

Figure 4.10: Slew rate, rise time, settling time transient response

From Figure 4.10, rise time tr is equal to 5.219ns (90%) - 5.072ns (10%) = 0.147ns. Î”V is equal to 1.564V (90%) - 1.251V (10%) = 0.313mV. Slew rate can be obtain by dividing Î”V with tr. Slew rate is equal to 0.313mV/0.147ns = 2.13GV/s or 2.13K/VÂµs and settling time equal to 12.5ns - 5ns = 7.5ns.

## 4.7 Common Mode Input Voltage Range and Maximum Output Voltage

vicm_cir.PNG

Figure 4.11: Common mode input voltage range test circuit

To simulate common mode input voltage range (VICM), the op-amp is connected as non-inverting amplifier with closed loop gain. DC input were given varies from 0V to 3.3V and measure the output. Common mode input voltage range is defined as voltage range that varies the input. Figure 4.12, the output voltage became constant at 1.854V even when we increase the input voltage. Therefore, maximum output voltage is equal to 1.854V. VICM = (2.0V - 1.2V) = 0.8V.

vicm_wave.PNG

Figure 4.12: Common mode input voltage range simulation result

## 4.8 Current consumption

curent_cir.PNG

Figure 4.13: Current consumption test circuit

Current consumptions are measured using circuit configured as Figure 4.13. DC input were given varies from 0V to 3.3V. Current consumptions are measured when the output voltage is equal to 1.2V. From Figure 4.14, the current consumptions for the op-amp are 112mA.

curent_wave.PNG

Figure 4.14: Current consumption simulation result

## 4.9 1.5 Bit Stage Pipeline ADC Simulation

fully_diff_mdac_pic.PNG

Figure 4.15: Fully-differential MDAC

The designed op-amp and CMFB are connected as Figure 4.15 to perform the fully-differential MDAC. MDAC from Figure 4.15 need to be combined with a sub-ADC to create a 1.5 bit stage pipelined ADC as Figure 2.1. Vary the Vin+ from 0.6V to 1.8V and Vin- from 1.8V to 0.6V, the measure the output voltage Vout+ with respect to Vout-. The simulation results are shown in Table 4.5.

The 1.5 bit stage pipelined uses 1.2V voltage reference. Hence, is equal to 0.3V and is equal to -0.3V. Referring to Table 2.1, if the input voltage difference is lower than 0.3V, the comparators will gives output 00. But, if the input voltage difference is in between -0.3V and 0.3V, comparators outputs are 01. Lastly, if the input voltage difference is bigger than 0.3V, the comparators outputs 10. Comparators outputs will determine MDAC operation according to Table 2.1.

Table 4.5: Fully-differential MDAC residue output

Vin+

Vin-

(Vin+) - (Vin-)

(Vout+) - (Vout -)

Region

0.60

1.80

-1.20

-1.0530

00

0.65

1.75

-1.10

-0.9020

00

0.70

1.70

-1.00

-0.7362

00

0.75

1.65

-0.90

-0.5612

00

0.80

1.60

-0.80

-0.3801

00

0.85

1.55

-0.70

-0.1935

00

0.90

1.50

-0.60

0.0000

00

0.95

1.45

-0.50

0.1897

00

1.00

1.40

-0.40

0.3765

00

1.05

1.35

-0.30

0.5570

01

1.10

1.30

-0.20

-0.3775

01

1.15

1.25

-0.10

-0.1903

01

1.20

1.20

0.00

0.0000

01

1.25

1.15

0.10

0.1902

01

1.30

1.10

0.20

0.3774

01

1.35

1.05

0.30

-0.5577

01

1.40

1.00

0.40

-0.3770

10

1.45

0.95

0.50

-0.1903

10

1.50

0.90

0.60

0.0000

10

1.55

0.85

0.70

0.1911

10

1.60

0.80

0.80

0.3782

10

1.65

0.75

0.90

0.5601

10

1.70

0.70

1.00

0.7354

10

1.75

0.65

1.10

0.9012

10

1.80

0.60

1.20

1.0520

10

From the data obtain by simulation; the 1.5 bit stage pipelined transfer function can be plotted as Figure 4.16. Due to gain error, residue outputs from MDAC are slightly different than theoretical calculation.

tranfer function.PNG

Figure 4.16: 1.5 bit stage pipelined transfer function using designed op-amp and CMFB

## CHAPTER 5

## DISCUSSIONS AND CONCLUSIONS

## 5.1 Discussions

The designed op-amp bandwidth is 54.71MHz, which is bigger than target specification of 44MHz. The achieved voltage gain is 41dB, which is close to target specification, 48dB. Increasing voltage gain will reduce the op-amp bandwidth at this point. Gain-bandwidth product is constant, increasing the gain will reduce the bandwidth and vice versa. Designing high gain and high bandwidth requires a very high unity gain bandwidth, which translates to high current consumption.

## 5.1.1 Gain Error

Due to its low voltage gain, the design will have bigger gain error when closed loop gain configuration is used. Consider non-inverting amplifier in Figure 4.11, the closed loop gain can be expressed as (5.1), where AOL is open loop gain and is feedback factor equal to.

From (5.1), multiply the denominator and numerator with

Add at the numerator to simplify (5.2)

Simplify (5.3)

From (5.4), term is called gain error factor. In order to minimize the gain error, open loop gain needs to be very high so gain error factor is equal to zero. The open loop gain for op-amp used in pipelined ADC depends on the resolution requirement. For high resolution application, the open loop gain requirement is very high.

transfer54dB.PNG

Figure 5.1 Comparison of residue voltage plot

Figure 5.1, shows clearly, op-amp with 54dB gain has a better accuracy than the op-amp with 41dB gain. The comparison is to show the gain error effect to low gain design. Gain requirement depends on the application accuracy requirement.

## 5.1.2 Figure of Merit

In order to compare the performance between op-amp, Figure of Merit (FOM) is used. Figure of merit is defined in two types, large signal figure of merit, and small signal figure of merit (Yang and Ge, 2009).

To take into account the effects of power supply scaling, we modify the definitions as:

Table 5.1: Figure of merit result

Item

A

B

Gain (dB)

41

54.85

Bandwidth (MHz)

54.71

1.889

Phase Margin (degrees)

44.81

62.45

G. BW (MHz)

6139

1044

Unity Gain Bandwidth (MHz)

3681

860

Slew Rate (V/Âµs)

2130

798

Capacitor Load (pF)

1

1

Total Current (mA)

112

14

FOMS (MHz.pF/mA)

54.81

74.58

FOML (V.pF/mA.Âµs)

19.02

57

Referring to Table 5.1, op-amp A is the op-amp that has been designed in this work. While, op-amp B is the same as op-amp A, but has higher gain by sacrificing the bandwidth and low current. Op-amp A has low FOM due to its high current compared to op-amp B, but it can still be consider good considering it has bandwidth 28 times bigger bandwidth than op-amp B.

## 5.2 Future Work

Designing high gain and high bandwidth op-amp is very challenging because of the trade off between gain and bandwidth. Higher bandwidth can be achieved with higher current consumption. While, higher gain can be achieved by designing multistage op-amp. Multistage op-amp usually will have stability issues; therefore a better CMFB design is needed.

## 5.3 Conclusions

The focus of the work in this dissertation is to design a telescopic op-amp with CMFB for 1.5 bit/stage pipelined ADC. The design exceeds the bandwidth requirement with 54.71MHz of bandwidth. The design has 41dB voltage gain, which is close to the specification. Increasing the voltage gain above 41dB will decrease the bandwidth severely. Even though the design has 44.81° phase margin but its still consider closed to the specification.

Another objective that has been achieved is to simulate the op-amp characteristics to provide data for op-amp topology comparison.