Measurement Of Juntion Depletion Layer Capacitance Biology Essay

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This assignment represents the basic information and fundamentals about the P-N junction diode and the properties of P-N junction capacitor. The experiment shows the formation of P-N junction depletion layer capacitance properties. This experiment shows the characteristics of depletion layer junction capacitance with respect to the particular voltage. Here we are find out the formation of depletion layer capacitance. We calculate the junction layer capacitance (CA) in various properties with respective to the voltage source.

INTRODUCTION:

This P-N junction diode is having some important characteristics and which is used in many applications in modern electronics. It's having two semiconductors which are farmed by single silicon crystal.

Here P-type semiconductor is having trivalent impurity and the majority carriers are holes. N-type semiconductor is having pentavalent impurity and the majority carriers are electrons and both are semiconductors, but the junction farmed between them is a nonconduction layer. This junction layer is called as depletion layer. This depletion layer occurs the charged particles electrons and holes attract and repulse to each other i.e. recombination of each other. In P-N junction diode flow of current is in only one direction. This can be represented in forward bias & reverse bias where bias indicates application of electric voltage to the p-n junction.

The P-N junction diode characteristics are given by

In P-N junction diode, there are two types of operations are there i.e. forward bias and reverse bias.

FORWARD BIAS:

V-I characteristics of p-n junction diode in reverse bias condition

In Forward-bias case when the p-type semiconductor is connected to the positive terminal of a battery and the N-type silicon is connected to the negative terminal of a battery. Then electrons and holes are attracted both pushed to words the depletion layer. Then the depletion layer width is decreased i.e. very thin, and the potential and voltage are increased then the resistance is decresed.In this case both electrons and holes travel in opposite direction, also they have opposite charges so the overall current is in the same direction on both sides of the P-N junction diode.

Reverse bias:

In reverse bias case when the p-type semiconductor is connected to the negative terminal of a battery and the N-type silicon is connected to the positive terminal of a battery. Then the holes in the P-type region, electrons in the n-type region are pulled away from the junction, and then automatically the depletion layer width increased. The potential barrier increases greatly then increases the electrical resistance against the flow of charge carriers. So there will no current flow in the diode.

Depletion layer capacitance:-

In P-N junction diode which is in the reverse bias case the depletion layer width increased. Due to the more diffusion of the holes into the n-type region and the electrons into p-type. In this case double depletion layer is formed. Here depletion layer capacitance is occur because there will be existence of the opposite layers are formed in the p-n junction diode.

In this power semiconductor devices is have some parameters i.e. breakdown voltage, on resistance, rise and fall times and thermal resistance.

THEORY:

P-N junction semiconductor devices with the help of simple dc characterizations of p-n diode and also control the control factor, reverse saturation current and the diode controlling. In this p-n junction diode we find the junction capacitance only on the ac characterization. Here the frequency response of the depletion layer capacitance is called as junction capacitance. The p-n junction capacitance has categorised in to two i.e. Depletion layer or space charge capacitance and diffusion capacitance. If a p-n junction diode is biased condition at a Dc reverse bias and with a minute ac voltage a charge accumulation takes place at the edge of the dc space charge region comes from ionization or the deionization process of both donor and the acceptor impurity in the depletion layer capacitance. This capacitance is directly related to the bias voltage.

According to abrupt theory the depletion layer of a p-n junction can be in the form as

Equation (1) we can also denoted as

Where V -applied bias voltage

V0- contact potential

Equation(1)we can also denoted as

The above equation same as the Y=mX+C, then we have to plot the graph between V and 1/Ca2

to same as shown below. Here the given values the area of diode is 1.27 cm2 and єr =12

Єo =8.854*10-12 F/M, e=1.6*10-19 C.

Graph:-

The capacitance per unit area by using the experiment is given

Where Cmeas -measured Capacitance of the depletion layer

Ccir-circuit capacitance of the circuit.

AIM:

To measure the depletion layer capacitance of a silicon p+ -n diode as a function of applied bias voltage, to test the validity of the abrupt junction theory.

D C P To measure the depletion layer capacitance of a silicon p+ -n diode as a function of applied bias voltage, to test the validity of the abrupt junction theory.

ower

supply

Wayne Kerr

Bridge

Dvm

Circuit diagram

EXPERIMENTAL PROCIDURE:

(1)Connect the circuit as shown in above diagram. Before switching on the power supply we have to adjust the minimum output voltage. In reverse bias case the voltage does not exceeds -30 V.

(2)Take readings of the bias voltage and the Cmeas values in the case of reverse bias voltage is -30 to -2 volts and we have to take the values from -2V to 0V in the interval of 0.5V.

(3)Then we are remove the diode and take the measurements for various bias voltages and circuit capacitance (Ccir).To convert measured junction capacitance Cmeas, and we are find out the value CA.

PRECAUTIONS:

(1)Avoid the loose connections, the connections should arrange as per the circuit diagram.

(2)If we get any negative readings we have to change the connection of the DVM .This is called parallax error.

RESULTS:

Here we can find the values of Cmeas, Ccir with respective to voltage and find the value of 1/CA2 . then apply the graph and tabular form between voltage and 1/CA2.

Reverse Bias Voltage (V)

Junction Capacitance, Cmeans (F)

CA (F/m2)

1/(CA)2 (m2/F2)

D.C Power Supply

Digital Voltage Meter (DVM)

30

-29.33

6.29E-10

28

-27.49

6.47E-10

26

-25.49

6.70E-10

4.58E-06

24

-23.51

6.93E-10

4.77E-06

22

-21.54

7.19E-10

4.97E-06

20

-19.59

7.49E-10

5.21E-06

18

-17.62

7.84E-10

5.48E-06

16

-15.67

8.25E-10

5.80E-06

14

-13.70

8.73E-10

6.18E-06

12

-11.74

9.33E-10

6.66E-06

10

-9.80

1.00E-09

7.18E-06

8

7.83

1.10E-09

7.97E-06

6

-5.86

1.24E-09

9.07E-06

4

-3.90

1.45E-09

1.07E-05

2

-1.95

1.88E-09

1.41E-05

1.5

-1.45

2.08E-09

1.57E-05

1

-0.96

2.38E-09

1.81E-05

0.5

-0.47

2.90E-09

2.21E-05

0

-0.18

3.48E-09

2.67E-05

Table (a) :Junction capacitance, Cmeans value with diode

Reverse Bias Voltage (V)

Capacitance of the Circuit, Ccir (F)

D.C Power Supply

Digital Voltage Meter (DVM)

-30.00

-29.60

8.68E-11

-28.00

-27.66

8.74E-11

-26.00

-25.69

8.74E-11

-24.00

-23.71

8.74E-11

-22.00

-21.73

8.75E-11

 

-20.00

-19.80

8.76E-11

 

-18.00

-17.87

8.77E-11

 

-16.00

-15.81

8.78E-11

 

-14.00

-13.82

8.78E-11

 

-12.00

-11.86

8.78E-11

 

-10.00

-9.86

8.78E-11

 

-8.00

-7.93

8.79E-11

 

-6.00

-5.99

8.79E-11

 

-4.00

-3.99

8.70E-11

-2.00

-1.97

8.75E-11

-1.50

-1.48

8.75E-11

-1.00

-0.99

8.75E-11

-0.50

-0.54

8.75E-11

0.00

-0.07

8.75E-11

Table (b) : Junction Capacitance, Ccir value

without diode

Then we have to represent the graph shown in below

From the above graph we are find out the value of the slope

m=5.578*10-10

Also the negative bias voltage is

V0=1.023 V

We can find the slope value by using graph we can use the below formula

. m(slope)=(Y2-Y1)/(X2-X1)= 5.578*10-10

Then we can be find out the value of ND

According to equation 2 we can demonstrate the slope is

m=

But NA>>ND then we are neglected the ND value

Then the above equation is changed as

The resulted ND value ND=6.562*1019

Here V0 is negative bias voltage.

Then we are find out the total depletion layer width using below equation

W=

Here VO= 1.08, ND=6.562*1019 atom cm-3

But Na>>Nd then the above equation is changed as below

W=

then the total width of the junction depletion layer(W) at -30 V is

W=2.508*10-5

After completion of width total we have to represent in a table

Reverse Bias Voltage (-V)

Width (W)

30.00

2.48E-05

28.00

2.40E-05

26.00

2.31E-05

24.00

2.23E-05

22.00

2.14E-05

20.00

2.04E-05

18.00

1.94E-05

16.00

1.84E-05

14.00

1.73E-05

12.00

1.61E-05

10.00

1.48E-05

8.00

1.34E-05

6.00

1.18E-05

4.00

1.00E-05

2.00

7.80E-06

1.50

7.14E-06

1.00

6.41E-06

0.50

5.59E-06

0.00

4.62E-06

Then the graph between the total width and reverse bias voltage

We can assume a large reverse bias voltage in this case V>>V0 then find the value CA at -0.5 reverse bias voltage

Then the junction depletion layer capacitance is

CA

Then the value of CA is 1.879*10-5 .This value is approximately equal to the previous value of CA the condition of equation.

Abrupt junction behaves like a parallel plate capacitor, that's why we can use this application in VARACTOR DIODE.Varactor diode operates in microwave range. These diode properties are as same as the P-N junction diode. Because it is also depends on the junction layer capacitance which is depends on the voltage. This diode is used in many application i.e. in amplifier it produced very low noice; it is a basic component in a parametric amplifiers.

CONCLUSION:

We already know about power semi conductor devices. Here we are discussed about the P-N junction depletion region. The abrupt junction theory hold good for the depletion region. Here P-N junction diode in forward bias the depletion layer width increased in reverse bias condition the depletion layer width is decreased, in reverse bias condition we are getting this depletion layer capacitance. All the P-n junction diode depletion layer capacitance results and calculations are investigated.

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