Interconnects Using Carbon Nanotubes Biology Essay

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Interconnect in an integrated circuit distributes clock and other signals as well as provides power/ground to various circuits on a chip .Carbon nanotubes (CNTs) have fascinated the scientific world with their unique qualities. Tougher than steel, as flexible as plastic, capable of conducting heat and transferring energy efficiently, CNTs have the potential to transform many industries. For example, CNTs can be used to create super-fast transistors, powerful and energy-efficient computers, thinner and cheaper liquid crystal display monitors, plasma screens, nanowires for electronic circuits and many more. This article examines the state of the art in CNT applications with focus on CNT interconnects.


Carbon nanotubes are the strongest and stiffest materials discovered in terms of tensile HYPERLINK ""strength (>60GPa) and elastic HYPERLINK ""modulus (~ 1 TPa) respectively. This strength results from the covalent bonds formed between the individual carbon atoms. The increasing resistivity of copper with scaling and demands for higher current density are the driving forces behind the research on new wiring solutions for deep nanometer scale VLSI technologies.


(a) A cut-out part of the graphite lattice (b) Single walled CNT (c) Multi-walled CNT (d) SWCNT bundle

A CNT is a one atom thick sheet of graphite (called graphene) rolled up into a seamless cylinder with diameter in the order of a nanometer [4]. The two types of CNTs are single-walled carbon nanotube (SWCNT) and multi-walled carbon nanotube(MWCNT). If several SWCNTs with varying diameter are nested concentrically inside one another, the resulting structure is called a multi-walled carbon nanotube (MWCNT) [1] .Several SWCNT can be clubbed together to form SWNT bundles.

It is observed that individually, both single-wall carbon nanotubes (SWCNTs) and multi-wall carbon nanotubes (MWCNTs) exhibit characteristics that can be better exploited when a combination of these CNTs is used in the form of a CNT bundle that plays a vital role in interconnect applications [7,8]. When a graphene sheet is rolled up to form the nanotube, its conductive properties are determined by its diameter, helicity and chirality which in turn depend on how the sheet is wrapped up. Depending on the wrapping, the nanotubes can be categorised into two types: Armchair and Zigzag.

Owing to the variation in the rolling process of the CNTs, each tube has different electrical properties. An armchair arrangement of the nanotube makes it behave like a metal. Whereas a zigzag arrangement makes the nanotube behave like a semiconductor [4].



(a) Arm chair arrangement (b) Zig-zag arrangement

Metallic carbon nanotubes (CNTs) are promising candidates that can potentially address the challenges faced by copper, and thereby extend the lifetime of electrical interconnects. Semiconducting CNTs can be used to fabricate low power transistor with high efficiency.



(a) Voids in interconnects b) Replaced by CNT

Fig.4 Multilayer CNT interconnects

During Cu layer deposition, there are several factors which contribute to the deformities in interconnects as shown in Fig.3(a) .Such voids can be prevented by replacing Cu interconnects by CNT as shown in Fig 3(b). Fig.4 illustrates multilayer CNT interconnects.

Table 1

The reliability data set of a pair of carbon nanotubes vs equivalent Cu wires measured at 250oC for 350 hours [1].



Cu-wire 1





8.6 nm

8.6 nm

15.3 nm

15.3 nm







10.4 mA


10 mA



2.4 kΩ

5.6 kΩ

1.7 kΩ

1.0 kΩ

Current density





Data for copper wires are not available for these dimensions, instead the calculated resistances for Cu-wires are shown in the above table.

Electrical properties of CNT

CNTs have the capability to fulfill the requirements of high current carrying capability and resistances comparable to or better than copper in vias or tungsten in contact holes. As shown in Table 1, CNTs can withstand current densities up to 1010 A/cm2, exceeding copper by a factor of 1000. With respect to resistance, CNTs are favorable in high aspect ratio structure like vias, where also the highest current densities are expected.

Fig.5 An array of SWCNTs would give the lowest resistance.

Fig.5 gives a rough estimate for obtainable resistances for CNTs as compared to copper. Depending on the diameter, a via can be filled with a single MWCNT, a densely packed array of MWCNTs or densely packed arrays of SWCNTs , which would give the lowest resistance. Additional doping of the CNTs can lower the curves for MWCNTs by at least a factor of 0.5 because higher sub-bands can contribute to the conductance.

CNT Growth process

A catalyst particle which facilitates the growth and determines the diameter of the CNT is usually required to grow CNTs, although there have been some reports of catalyst free formation of CNTs by microwave and template assisted growth methods. Filling via structures with nanotubes requires one or more particles at the bottom of the via which then allow CNT growth by chemical vapor deposition (CVD) at 450-800°C with a carbon containing gas. The CVD process can be supported by plasma enhancement (PECVD) and bias voltage. The catalyst material (Fe, Ni, Co or combinations of them with Mo) is usually deposited as a thin film by physical vapor deposition (PVD) or from solutions [1].

Particle formation occurs during the heating step, which breaks up the thin film into clusters. Ion bombardment in plasmas supports this particle formation. Careful material and interface design in combination with low temperature budget and time dependent diffusion phenomena, needs to be taken into account to guarantee CNT growth [6].

The interaction between catalyst layer and supporting metal electrode needs to be low, in order to suppress inter diffusion and allow particle formation in the restricted temperature regime. Metals with a natural thin oxide layer (Ta, Al, Ti, Cu, Cr) show low wetting behavior for some catalyst materials and are therefore suitable as electrode materials.

Currently two different approaches have been proposed called bottom up approach, shown in Fig 6. Here, the CNT via is grown on the metal 1 layer before the deposition of the inter-metal dielectric (IMD). Lithographically defined nickel spots act as catalyst particles, from where carbon fibers are grown. As a prerequisite, the fibers need to be aligned perpendicular to the surface. This is achieved by PECVD and an applied bias voltage, which aligns the fibers almost perpendicular to the wafer. Subsequently, SiO2 is deposited and the wafer is planarized with chemical wafer polishing (CMP). The last step also opens the nanotube ends for contacts with metal 2 layer [5].

Fig.6 Bottom up approach

A very high resistance of ~ 300 kΩ per CNT interconnect has been evaluated for this approach, which may be attributed to the imperfect structure of PECVD grown MWCNTs. The approach is especially suited for single MWCNT fillings because high density growth could not be demonstrated. In addition, this approach can also be used to create high aspect ratio capacitor electrodes for DRAM applications [1].

Fig.7 Buried catalyst approach

The more conventional approach of etching the vias down to metal 1 layer and growing the CNTs by a buried catalyst approach shown in Fig.7, where the dry etching of the via has to stop on the thin Ni- or Co-catalyst layer . Arrays of MWCNTs have been grown in ~2µm diameter vias by hot-filament CVD (HF-CVD). A resistance of ~134 kΩ per MWCNT has been achieved, a value which can be attributed to the quality of the tubes grown by HF-CVD. In contrast, we have used a pure CVD approach to grow high quality tubes in vias exhibiting resistances of ~10 kΩ per MWCNT [3]. In order to manage the via etch stop on a ~2 nm catalyst layer, a catalyst multilayer stack has been developed, which allows proper landing on the catalyst layer with reliable growth of MWCNTs with a density varying between 100 - 1000/µm2.

20 nm node CNT interconnect

CNT interconnects for the 20 nm node have been fabricated, using the buried catalyst approach. The procedure, dimensions and resulting MWCNT via is shown in Figure 8. A catalyst layer consisting of a triple stack of (3 nm Fe, 5nm Ta) has been deposited on metal 1 prior to the deposition of 150- 200 nm SiO2. Electron beam lithography in combination with a hard mask technique has been used to define the vias. The 20 nm diameter vias have been etched in an MERIE reactor. Subsequently, MWCNTs have been grown by CVD at 450-700°C. The quality and yield of the CNT-vias rises with growth temperature[6].

Before deposition of the top contact (metal 2 layer), the MWCNTs have been encapsulated by a ~20 nm thin SiO2 either by spin-on-glass or PECVD deposition. The end of the MWCNT is revealed again by removing excess SiO2 by CMP or a back etch. This step prevents metallic whisker formation during top contact preparation which may affect the resistance measurements.Various metals such as titanium, palladium and tungsten can be used as top contacts for CNTs.

Fig. 8:. A 20 nm diameter MWCNT is protruding from the via.

Future CNT Transistor Prototype

Fig.10 Carbon Nanotubes Transistor

Due to the improved electrical characteristics of the CNT, there is a possibility of designing future transistors completely made up of CNTs[2]. A single nanotube has a diameter not greater than approximately 1 nm,is metallic or semi conductive depending on atomic array of the carbon in the tube, and can be doped with impurities. In the nanotube transistor shown in Fig.10, a bundle of carbon nanotubes is used as a base part of the transistor, one single line or a few lines of carbon nanotubes are used as the emitter and the collector respectively [3].The future CNT transistors may revolutionize the design of the semiconductor devices to greater extent .