This essay has been submitted by a student. This is not an example of the work written by our professional essay writers.
Practical guidelines for the implementation of back drilling plated through hole(PTH) vias in multi-gigabit board applications. Back drilling is a technology that can solve the problem of stub length.
Transport data rates of 3.125Gb/s are now common place in board-to board applications. As data rates increase to 5, 6.25 or 10Gb/s the entire channel topography will need to be re-examined. A typical transmission channel includes signal traces, connectors, and plated through hole vias. New connectors are entering the market with better impedance matching and improved shielding techniques to accommodate the sharper rise times associated with the faster data rates. Likewise laminate suppliers continue to develop new board materials with lower loss tangents to reduce the signal attenuation due to laminate
loss. Using equalization circuits and signal pre-emphasis, device suppliers are driving solutions to improve signal fidelity at increased data rates. A piece of the transmission path which cannot be neglected, is the plated through hole or via. Plated through holes or PTH's are a means to transport signals into interior layers of a multi layer PC board. PTH
vias are used in this way under the pad array of the device package, and in the launch of separable connector interface into boards. The PTH is common to various device packages such as a ball grid array (BGA) and connector types including press fit and surface mount right angle board-to-board, mezzanine and cable connectors. In the case of a typical backplane system, the signal passes through at least six vias or PTH's while traveling from driver to receiver, and the board thickness in such a system can result in relatively long plated through holes.
The PTH portion of the signal path becomes more "visible" to the signal as increased frequency content is needed to produce sharp rise and fall times of the digital pulse.
Figure 1: Typical signal path.
The actual rise time and frequency content of digital pulses may vary. The frequency spectrum of a PRBS digital data stream typically consists of bands centered around a fundamental and its odd harmonics. The fundamental frequency of the spectrum occurs at one half of the data rate. At 2.5Gbits/sec, this means that the fundamental frequency would occur around 1.25GHz with some contribution around the third (3.75 GHz) and fifth (6.25Ghz) harmonics. The transmission vs. frequency response will be shown for various via geometries, together with eye patterns which incorporate the effects of the higher harmonics. A PTH or through via joining a surface pad or connector to an inner layer strip line trace, can behave as a parasitic element or transmission line discontinuity. It acts as a notch filter centered around a frequency primarily determined by the unused portion of the hole, sometimes referred to as a resonant stub. As a signal transitions into a
plated through hole, some of the energy is reflected back to the source from the impedance discontinuity. The remaining energy proceeds through the via. The energy that is transitioning through the plated through hole uses the hole as a transmission line element whose parameters are defined by the physical dimensions of the structure
(pad size, anti-pad size, etc.) It then reaches an impedance matched stripline layer. Some of the energy is transmitted into this layer and some continues to travel down the remaining via. Any portion of the plated through hole below the exiting stripline layer can be looked at as an open transmission element referred to as a stub. The energy that passes the exiting stripline layer proceeds to the end of the stub and encounters an open circuit, and it is reflected back towards the source or converted to radiation. At low frequencies a PTH element could simply be modeled as a lumped capacitor. At higher frequencies the round trip delay for this PTH element approaches the signal rise time and the simple capacitive approximation no longer holds. The length of the stub could be over 8mm in a backplane. As an example, in our 0.220" thick test board, the maximum
stub was 5.0mm. The delay of pure FR4 is approximately 7ps/mm or 175ps/inch. The calculated delay from the open end of the stub to the strip line layer is approximately 38ps. The calculated quarter wavelength frequency of this open stub element resembling an antenna is approximately 7 GHz. The actual observed frequency is always somewhat lower due to excess fringing capacitance and other effects from the details of the structure. For example, in the test board shown in Figure 2, the notch was measured at 4.5Ghz. If the notch created by this resonance occurs at a frequency, which is close to the fundamental frequency, only a percentage of the transmitted signal would make it past the filter created by the stub.
Figure 2: signal propagation
2.0 Experimental Measurements
A simple single PTH test fixture was created to focus on the PTH effect independent of any connector or device package as shown in Figure 2.
Figure 3:PTH stub counter boring test fixture
In order to isolate which physical feature could be altered to change or tune the resonant behavior of the via, measurements and simulations were done to determine the variation of this approximate notch frequency (Ff) as a function of the ground plane relief (anti pad), the laminate material, the via diameter, and finally the via stub length.
Regarding the anti-pad effects shown in figure:4 of the test board clearances of .048", .070" and .095" diameter ground plane clearances were measured. It could be seen that even increasing the anti-pad diameter to .095" moves the notch up approximately 1.5 GHz, not enough to ensure good transmission over the zero to 6 GHz bandwidth that is required for a 6 Gb/s signal. It should be noted that anti pads of this size could not be used under a BGA, or within a high-density connector footprint.
Changing the board laminate material will also affect the notch frequency., Ff only moves a few hundred MHz due to laminate alone when the via diameter and length are held constant. This is primarily due to the change in electrical length of the via due to a change in dielectric constant where the propagation velocity Vp = c/sqrt (Er), where Er is the dielectric constant of the medium and c is the speed of light. By changing to a laminate with a lower dielectric constant, you will have a larger effect on notch frequency due to the reduced board thickness shown in figure 5.
The notch frequency Ff was then studied in relationship to PTH diameter while holding the other variables constant. In this case a combination of measurements and simulations were needed to limit the number of test fixtures required. Simulation was done using finite difference time domain (FDTD) full wave solver by Remcom, Inc. Correlation of this simulation tool to the original test fixture is shown in Figure 6. This figure contains measured values for a .018 via, and simulations for .012, and .018 vias. The simulated notches are sharper because dielectric and conductor losses were neglected. Although the via diameter has the effect of moving Ff by approximately 200 MHz from the minimum
to maximum via studied, this change by itself will not be enough to fully mitigate the stub effect. This implies that simply changing the termination method for a high-speed connection from press fit to surface mount or a pressure interface may not negate the stub effect of the associated PTH or Via. As a first approximation, stub effects are present in any PTH where the combination of material and geometry move the notch into the frequency of interest. Although other variables show some effect the stub notch
frequency is primarily a function of its length.
2.1 Optimizing Stubs
The first step in minimizing the impact from stubs is to keep their length as short as possible. In a multilayer board, one way of keeping stub lengths short is by limiting the signal layer transitions. In an extreme case, high-speed signals will only be routed on the top and bottom layers so that any via between these layers will have no stub at all. A slight amendment to this design guideline might be to limit any high-speed signal transitions from near a top layer to near a bottom layer. This will limit the length of a via from the surface to the lowest signal layer. If you can't make a via stub shorter, then the next knob to tweak is to increase their impedance by decreasing their capacitance. This can be accomplished by:
Use as narrow a barrel diameter as possible.
Reduce cross talk in foot print by alternating back drilled vias.
Match long trace lengths with shortest via stub.
Minimize the size of capture pads on the top and bottom surfaces
Remove all non functional pads on all intermediate layers
Increase the clearance holes through all planes as much as possible.
2.2 Back Drilling Stubs
Blind and buried vias are an alternative method which can be used to control the maximum length of a PCB stub. An alternative is to back drill the via stub to remove the conductive barrel. Back drilling or counter boring the via is an alternative technique to minimize the stub. Back drilling is simply drilling out the unused portion of a via to a controlled depth on the same type of equipment used to initially produce the board. Back drilling has become a conventional process that most fab shops routinely do with only a small price premium. The through hole via is manufactured in the conventional way, and then a drill bit with a diameter a few mils larger than the barrel is used to drill out the stub from one side of the board. This requires controlled depth drilling, which can typically be controlled to within 5-10 mils.Using back drilling, residual via stubs can easily be kept to less than 20 mils, which enables good signal quality for even 15 Gbps signals. Many backplanes have demonstrated more than 10 Gbps operation with conventional FR-4, preemphasis and equalization and with back drilled vias.
To understand how this type of information could be used as a first cut design guideline, two examples are shown. Because digital pulse transmission is broadband, containing a number of frequency bands, the single notch frequency Ff is not adequate to determine the effect on a received eye pattern in a system. The width of the notch, or "Q" can also cause excessive attenuation in useable frequency bands. Loss will be looked at in the frequency band of a fundamental frequency up to 2 times the fundamental to account for the notch width.
Two examples are shown, one at 3.125Gb/s and one at 6.0 Gb/s. Remaining stub lengths of 0.0220" and 0.090 with a .018" PTH were compared at these rates in a fixture containing 12"of FR4, and 2 SMA's.
For 3.125 Gb/s, the delta between the FR4 reference trace and the .090" stub is 0.5 db at 1.5 Ghz. This deviation from reference is 1.2 db for the .220" stub. Over a band of 50 Mhz to 3Ghz, the maximum attenuation of a .090" stub 1.2 db and the .220" stub is 7 db. Comparing measurements in the time domain for these cases, we see that the .220" stub has had a noticeable effect on the measured eye diagrams shown in Figure 7.
For a 6 Gb/s data stream the fundamental frequency is 3 GHZ , at 3 GHZ the difference between the reference trace and the .090" stub is still 1.2 db and 7 db for the .220" stub. The maximum attenuation of the .090" stub is 3 db and the maximum attenuation of the .220" stub is 27 db for the band of 50 MHz to 6 GHz ( 2 times the fundamental or 6 Ghz.) The notch frequency is now within this band so severe degradation could be expected in the received eye. Measured eye patterns shown in Figure 8 show this effect.
2.3 Bare Board Fabrication Process
Back drilling or controlled depth counter boring is a process where plating is removed from the unused portion of the via multi layer printed wiring boards are processed in a standard manner adding a secondary drilling operation after plating, using PWB CNC drilling equipment with controlled depth enhancements. CNC drill files created from customer data allow this process to be automated and repeatable.
2.3.1 Over Drill Diameter: One important parameter is the secondary drill diameter. This drill diameter must be greater in diameter than the primary drill to allow removal of all the electrodeposited plated metal, typically copper with an additional surface finish. Minimization of this diameter is important to avoid reduction of routing channels which
compromise hole to trace spacing in the pin fields. A controlled experiment was done by varying the over drill diameter to 5, 7, 10 and 13 mils above original drill size to determine the presence of residual plating. Ten holes from each corner of 4 panels drilled on 4 spindles in one pass were cross-sectioned and evaluated for complete plating removal and internal spacing. No residual plating or spacing violations were observed on any over drill hole size.Current recommendation is 7 mils over original drill diameter.
2.3.2 Back drill Depth: Back drilling is a trade off between manufacturing cost and electrical performance. Contributors to back drill depth variation have been characterized which affect yield and cost. Optimized setup process achieves a 3 sigma overall variation of +/- 5 mils to nominal target depth. This comes from two components: Mechanical depth and Layer position. It is recommended that at least a 10mil target nominal depth before the last layer connected.
Figure 9: Back drilling dimensional configurations.
2.3.3 Bare Board Reliability Testing: A forced failure designed experiment was conducted, intentionally varying process parameters, which took the PTH integrity to extremes. Parameters varied were Drill Hole Quality, Electroless Copper etch back Rate, and Copper Plating Thickness. Test vehicles were subjected to thermal cycling and 6 x solder shock testing. As expected, no failures were observed on either normal PTH's or back drilled PTH's on boards processed under standard conditions. Failures due to cracking were observed on both hole types exhibiting poor drilled hole quality and thin copper plating conditions
Cost Model: A cost model developed at Teradyne factors in set up time, run time, and drill bit cost. Application of this model to various board designs results in an average increase of 7 % added to the bare board price. For example, a typical board requiring fifteen hundred back drilled holes would result in an additional cost of about $50 per
2.4 Surface Finishes and Exposed Cu
ÂÂ· For Electrolytic Deposited Surface Finishes (re-flowed PbSn, Gold) TCS currently would perform back drilling after that process resulting in exposed copper at the end of the stub.
ÂÂ· Back drilling can be done before Immersion Surface Finishes resulting in no exposed bare copper at the end of the stub.
ÂÂ· Immersion Tin for Back drilled backplanes is preferred.
2.5 Assembly Level Reliability Verification Testing
To evaluate back drilled via structures various reliability testing sequences applicable to PCB vias were performed in accordance with the Telcordia GR-1217-Core and GR-2969-Core requirements for telecommunication hardware. The test plan includes bare board
sequences and testing to evaluate press fit termination. This testing has been performed to quality level III. In addition, to the reliability testing testing, temperature rise and solder shock testing was also performed. Via's were evaluated both with and without anchoring pads at the bottom of the plated hole or back drilled end of the via. See Figure 17 for test
The following reliability test groups were chosen to assess the plated through hole integrity: 1.) Compliant Pin Performance, 3.) DWV dielectric withstanding voltage. 2.) Current Rating, 4-6) humidity cycling and thermal shock, 7.) Mixed flowing gas, 8.) Electro-migration,. The humidity cycling and thermal shock group was chosen evaluate the effects of thermally stressing the via structure, in order to look for de-lamination between the copper plating and the drilled hole. The mixed flowing gas group was performed to accelerate the corrosion rate between the compliant pin interface and the plated through hole. The purpose of the electro-migration group was to analyze the metallic material growth between the plated through hole and the exposed copper layers. The compliant pin performance testing was performed to mechanically stress the via structure and to evaluate the performance of the compliant pin. The purpose of mechanically stressing the via structure was to see if the copper hole would de-laminate
from the drilled hole wall. A portion of that particular group was also tested to failure, meaning that the pins were purposely pushed through the hole to try to cause the copper to de-laminate. Since back drilling removes copper from the via, the current rating of the via was also tested to evaluate the current capacity. All of the test vehicles had two different via structure, one with anchoring pads and the other without anchoring pads to evaluate the mechanical stability of the via structure.
Figure 4 : frequency response of antipad effect.
In this .048", .070" and .095" diameter ground plane clearances were measured.
Figure 5 : frequency response of laminate effect .
In this a 20 signal layer board with .008" traces impedance matched to 100 Ohm would be .230 thick in FR4 and .182" thick in alaminate with Er=3.2. This length effect will be treated separately.
Figure 6 : frequency response of stub effect.
This figure contains measured values for a .018 via, and simulations for .012, and .018 vias.
ffigure 7 : eye pattern for 3.125Gb/s
Figure 8: Eye pattern for 6.0Gb/s.
3.2 Future scope
Looking forward, on-going effort will be required on seamless implementation of the design rules, evaluating the electrical and reliability effects of plated through hole used in an SMT application, and further refining the design rules based on other structures.
The technique of back drilling is being used in production today to tune the characteristics of a plated through hole in a printed circuit board. The decision of when to back drill depends primarily on the signal frequency content and the length of the stub.
A tiny via stub, less than 150 mils long, can affect the performance of a high-speed serial link much more than an entire 50 inch long interconnect. The stub can be tamed by keeping its length short. Using the combination of careful design guidelines in the physical design of a via and restricting signal layer transitions, along with technology options such as back drilled vias, a high-speed designer should not hesitate to incorporate vias in multigigabit designsAlthough efforts to reduce stub effect can be accomplished through various techniques such as using lower dielectric material to reduce thickness or routing high speed signals to the bottom of the board, eventually higher frequency designs and increased board thickness will force some treatment of the stub. It is also important to remember that the package or connector is critical to the signal path but independent of the stub effect, and for this reason changing the termination from press fit to SMT may not resolve the inherent stub induced signal loss.