High Leakage Currents On Sram Cell Biology Essay

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Reduction of leakage current is significant in low power applications. Because these leakage currents increase the total power consumption of the circuit. In this paper, various existing leakage reduction techniques for memory cells are discussed and also a new 12T SRAM cell is proposed. These 12T SRAM cell has high stability and low power consumption compared to other cells. Some of the leakage reduction techniques discussed in this paper are dynamic VDD, multiple Vth, dual power supply scheme, SVL (Self- Controllable Voltage Level) and AVL( Adaptive Voltage Level). These techniques are applied on different SRAM cells such as 6T, 7T, 8T, 10T and proposed 12T SRAM cell and the results are compared. For simulation, MICROWIND 3.1 tool is used.

Keywords-Leakage reduction, write ability, SRAM, leakage power.

I.INTRODUCTION

High leakage currents on SRAM cell plays a major role in total power consumption of the low power memory cells. These leakage currents occur as a result of scaling of the threshold voltage, channel length and gate oxide thickness. As technology scales down, the supply voltage, gate oxide thickness and channel length must be reduced. In future, the gate oxide thickness may be as low as 0.5nm for CMOS technologies [1]. As a result, the reduction in gate oxide thickness increases gate leakage current. The gate tunnelling current is also predicted to increase at a rate of 500 times per technology whereas the sub-threshold current increases by only 5 times [1].

As a result of high drain voltage and negative gate voltage, field crowding occurs at drain edge causing gate induced drain leakage (GIDL). And also this high drain voltage application to a short channel device results in lowering of barrier height and shifting of point of maximum barrier to the left causing drain induced barrier lowering (DIBL).

If the supply voltage is below the threshold voltage, the process parameters and the variability of the SRAM increase severely [2]. Some of the SRAM stability issues are process-induced device variation, decreasing ION / IOFF and threshold voltage random variation [3].

Due to increase in Vt fluctuations and process variations, SRAM cell cannot be operated at further scaled supply voltages without functional failures causing yield loss. A low-power 6T SRAM cell [4] shown in fig.1 could reduce access delay and write power but could not improve read stability. A single-ended 6T SRAM cell [5] suffers from write delay.

File:SRAM Cell (6 Transistors).svg

Fig.1. Basic 6T SRAM cell structure

The paper is organized as follows:

Section II explains about various leakage currents occurring in the transistor of SRAM cell. Section III presents various leakage current reduction techniques. In Section IV, the proposed 12T SRAM cell is discussed. Section V presents the simulation results of the proposed techniques. Finally, conclusion is given in Section VI.

II. LEAKAGE CURRENTS ON SRAM

The leakage currents taking place on the SRAM cells are sub-threshold leakage current and gate leakage current, negligible amount of DIBL and GIDL.

A) SUB-THRESHOLD LEAKAGE CURRENT:

Fig.2. Sub-threshold leakage current of MOSFET

The sub-threshold leakage current takes place between the drain and the source of the transistor. These leakage current happen when the gate voltage (Vg) is less than that of the threshold voltage (Vth). The curve between gate source voltage (VGS) and the sub-threshold current (ISUB) is shown in fig. 2.

B) GATE LEAKAGE CURRENT:

The sub-threshold leakage occurs only on the inactive (standby) condition. But, the gate leakage current shown in fig. 3 takes place on both ON and OFF state.

As the technology scaling results in the reduction of gate oxide thickness, a high electric field and tunnelling of electrons between the substrate and gate takes place. And this results in the gate oxide tunnelling current.

If positive bias is applied to the gate, the tunnelling current flows from substrate to gate. If negative bias is applied, tunnelling occurs from gate to substrate.

G:\Gate current components flowing between NMOS terminals[1].jpeg

Fig.3. Gate leakage current

C) DIBL:

The source and drain separation is large for long channel devices. In long channel devices, the Vth is independent of the channel length and the drain voltage. But, in the short channel devices, the Vth is dependent on drain voltage i.e, Vth varies with respect to the drain voltage. This is known as Drain induced Barrier Lowering (DIBL).

D) GIDL:

Gate Induced Drain Leakage (GIDL) arises due to the high electric field occurring in the drain junction of the transistor. It mainly happens in the OFF state.

The high drain voltage and the negative gate voltage develop field crowding at the drain edge. This process results in gate induced drain leakage known as IGIDL.

III. LEAKAGE CURRENT REDUCTION TECHNIQUES

The different techniques employed for reducing the leakage current in SRAM cells are a) Dynamic VDD b) Multiple Vth c) Dual Power Supply Scheme d) SVL e) AVL.

A) Dynamic VDD Technique:

In the dynamic VDD scheme, normal supply voltage is given to the circuit during the active mode. But in the standby condition, reduced supply voltage is given. For this process, an extra peripheral circuitry known as the efficiency voltage converter is needed [6]. These reduced supply voltage decreases the leakage current. But the supply voltage reduction, results in low SNM (Static Noise Margin) and also causes data flipping failures.

B) Multiple Vth Scheme:

The multiple Vth scheme consists of both high and low threshold transistors in the same chip which can be used for dealing the leakage problem. The high threshold transistors are used for suppressing the sub-threshold leakage current and the low threshold transistor is used for achieving good performance.

The following methods are used for achieving multiple threshold voltages: i) Multiple channel doping ii) Multiple oxide CMOS iii) Multiple channel length iv) Multiple body bias.

C) Dual Power Supply Scheme:

The technology scaling requires the supply voltage to be reduced in order to reduce the power consumption. But, the lowering of supply voltage results in worsened SRAM stability. In order to overcome this problem, extra power supply was used in many designs [12][13].

Fig.4 Circuit for dual power supply scheme

In 6T SRAM cell, the cell with higher VDD have better read stability but worsened write stability. In order to improve the write ability, word line compensation technique is combined with dual power supply scheme [11]. Two global power supplies namely VSM and VDD are used in the fig.4.

D) SVL Scheme:

The SVL (Self controllable Voltage Level) circuit employed on 10T SRAM cell is shown in the fig. 5.

The basic concept is that when the SRAM cell is in active mode, the leakage current is low. And there is no degradation in noise margin. During standby mode, leakage current is high and hence reduced supply voltage is given to the SRAM cell. This reduces the leakage current and also reduces noise margin.

The major drawback of this technique is that it cannot able to reduce the gate leakage current.

Fig.5. 10T SRAM cell with SVL circuit

E) AVL Scheme:

The AVL (Adaptive Voltage level) scheme can able to reduce both the sub-threshold leakage as well as gate leakage current.

In this technique, an AVL circuit is attached to the SRAM cell for controlling the effective voltage across it. The AVL switch can be inserted either at the ground node (AVLG) or supply node (AVLS).

The AVLG circuit will provide 0V at ground node during the active mode and increased voltage during the standby mode [7]. This scheme is similar to that of the diode footed cache design scheme for controlling the leakages in SRAM. In that, a diode is designed with high threshold transistor for raising the ground level in standby mode [8]. The 10T SRAM cell with AVLG circuit is shown in the fig. 6. And the 10T SRAM cell with AVLS circuit is shown in fig. 7.

Fig.6 10T SRAM cell with AVLG circuit

Fig.7. 10T SRAM cell with AVLS circuit

IV. PROPOSED 12T SRAM CELL

The basic SRAM cell consists of storage cell having four transistors (M1- M4) and two control transistors M5 and M6. In the proposed 12T SRAM cell, eight transistors for storage cell and four for access control is proposed. These can be used for multiport application, as it can accept multiple inputs at a time. The 12T SRAM cell is shown in the fig.8.

C:\Users\Hema\Desktop\paperregconference\12t.png

Fig.8 Proposed 12T SRAM cell

V. SIMULATION RESULTS

The simulation results of the proposed techniques (AVL and SVL) are discussed in this section. These techniques are employed on the proposed SRAM cells.

Power consumption of the conventional (6T, 7T, 8T and 10T) SRAM cells is shown in the table 1. Simulation results are simulated on MICROWIND tool under different supply voltages.

Table.1. Power consumption of various SRAM cells

CELL TYPE

SUPPLY

VOLTAGE

(V)

TOTAL

POWER

(W)

AVERAGE DRAIN CURRENT

(A)

6T SRAM

1.2

0.19 m

0.16 m

0.5

1.45 µ

0.003 m

0.25

0.03 µ

0

7T SRAM

1.2

0.19 m

0.16 m

0.5

0.64 µ

0.001 m

0.25

0.02 µ

0

8T SRAM

1.2

0.43 m

0.39 m

0.5

1.96 µ

0.004 m

0.25

0.04 µ

0

10T SRAM

1.2

0.21 m

0.18 m

0.5

0.93 µ

0.002 m

0.25

0.02 µ

0

12T SRAM

1.2

0.11m

0.092m

0.5

0.363 µ

0.001m

0.25

0.023 µ

0

The power consumption of the AVL (AVLG & AVLS) and SVL (SVL lower & upper) techniques is shown in the table 2.

Table.2. Power consumption of Proposed SRAM cell using various techniques

TECHNIQUE

SUPPLY

VOLTAGE

(V)

TOTAL POWER

(W)

AVERAGE DRAIN

CURRENT

(A)

AVLG

1.2

0.14 m

0.12 m

0.5

0.91 µ

0.002 m

0.25

0.02 µ

0

AVLS

1.2

0.50 µ

0.005 m

0.5

0.06 µ

0.001 m

0.25

0.02 µ

0

SVL upper

1.2

4.69 µ

0.006 m

0.5

0.14 µ

0.001 m

0,25

0.03 µ

0

SVL lower

1.2

0.14 m

0.12 m

0.5

0.84 µ

0.002 m

0.25

0.03 µ

0

The output waveform of the 10T SRAM cell is shown in fig. 9. In the waveform, three control lines are used namely bit (in1), bit_ (in2) and word (in3) as shown in fig.5. If the in3 is 0, both Q and nQ (out1 and out2) will be zero.

When in3 is 1, in1 is 0 and in2 is 1, out2 will be high and write operation is performed. When in3 is 1, in2 is 0 and in1 is 1, out1 is high and read operation is performed.

Fig.9. Output waveform of 10T SRAM cell

The layout of 10T SRAM cell is shown in the fig. 10.

Fig.10. Layout of 10T SRAM cell

The voltage and current waveforms of 10T SRAM cell is shown in the fig.11. The power consumption is about 0.210mW and average drain current (Idd) is 0.175mA.

Fig.11. Voltage and current waveforms of 10T SRAM cell

The layout of 10T SRAM cell with AVLG is shown in the fig.12.

Fig.12. Layout of 10T SRAM cell with AVLG

The voltage and current waveforms of 10T SRAM cell with AVLG is shown in fig.13. The power consumption is about 0.141mW and the average drain current (Idd) is 0.118mA.

Fig.13. Voltage and current waveform of 10T SRAM cell with AVLG circuit

The layout of 10T SRAM cell with AVLS is shown in fig.14 and its voltage and current waveforms are shown in fig.16. The power consumption is about 0.504µW. These results show that the power consumption of the 10T SRAM cell reduces much with the AVLS technique compared to AVLG technique. The average drain current (Idd) is also reduced to 0.005mA compared to the conventional SRAM cells.

Fig.14. Layout of 10T SRAM cell with AVLS

Fig.15. Voltage and current waveform of 10T SRAM cell with AVLS circuit

The voltage vs time waveforms of 10T SRAM cell with SVL lower and upper is shown in fig.16 and 17. The power consumption is about 0.142mW and 4.699µW and the average drain current (Idd) is 0.119mA and 0.006mA.

Fig.16. Voltage vs time waveform of 10T SRAM cell with SVL lower circuit

Fig.17. Voltage vs time waveform of 10T SRAM cell with SVL upper circuit

The layout of 10T SRAM cell with SVL lower and upper is shown in fig.18 and 19.

Fig.18. Layout of 10T SRAM cell with SVL lower

Fig.19. Layout of 10T SRAM cell with SVL upper

VI. CONCLUSION

Many researches have been conducted on SRAM leakage current reduction and stability improvement. Some techniques focus only on one part of the problem and introduce another problem. The drawbacks of the various techniques are also mentioned in this paper. Of the several leakage reduction techniques discussed in this paper, SVL and AVL techniques show greater leakage suppressing capability. For the stability improvement of SRAM, bit interleaving technique improves both write and read ability of the SRAM in a better way compared to other techniques. The proposed 12T SRAM cell consumed low power compared to other cells.

VII. REFERENCES

International technology Roadmap for the Semiconductors [online]. Available: http://public.itrs.net.

S. Hanson, B. Zhai, K. Bernstein,L.Chang, D.Blaauw , A. Bryant, K.K. Das, W. Haensch, E.J. Nowak and D.M. Sylvester, "Ultralow-Voltage minimum-energy CMOS," IBM J.Res.Develop.,vol. 50, no. 4/5, pp. 469-490, jul./sep. 2006.

H. Yamauchi, "A discussion on SRAM circuit design trend in deeper nanometer-scale technologies," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 18, no. 5, pp. 763-774, May 2010.

H. Mizuno and T. Nagano, "Driving source-line cell architecture for sub- 1-V high-speed low-power applications," IEEE J. Solid-State Circuits, vol. 31, no. 4, pp. 552-557, Apr. 1996.

J. Singh , D. K. Pradhan , S. Hollis, and S.P. Mohanty, "A single ended 6T SRAM cell design for ultra-low-voltage applications," IEICE Electron. Exp., vol. 5, no. 18, pp. 750-755, Sep. 2008.

G. Fukano, K. Kushida, A. Tohata, Y. Takeyama, K. Imai, A. Suzuki, "A 65nm 1Mb SRAM macro with dynamic voltage scaling in dual power supply scheme for low power SoCs," International Conference on Memory Technology and Design, Opio, pp. 18-22.

Monika Yadav, Shyam Akashe, Yogesh Goswami, " Analysis of leakage reduction techniques on different SRAM cells," International Journal of Engg. Trends and Tech., vol.2, issue 3, pp. 78-83, 2011.

Amit Agarwal, Hai Li and Kaushik Roy, "DRG-Cache: A data retention gated-ground cache for low power", Proceedings of the 39th Design Automation conference, June 2002.

K. Nii, M. Yabuuchi, Y. Tsukamoto, "A 45-nm bulk CMOS embedded SRAM with improved immunity against process and temperature variations," IEEE J. Solid-State Circuits, vol. 43, pp. 180-191, Jan. 2008.

K. Nii, M. Yabuuchi, Y. Tsukamoto,, "A 45-nm single-port and dual-port SRAM family with robust read/write stabilizing circuitry under DVFS environment," in Proc. VLSI Circuits Symp., pp. 212-213, Jun. 2008.

O. Hirabayashi, A. Kawasumi, A.Suzuki, "A process-variation tolerant dual-power-supply SRAM with 0.179mm2 cell in 40nm CMOS using level-programmable wordline driver," ISSCC Dig. Tech. Papers, pp. 458-459, Feb. 2009.

K. Zhang, U. Bhattacharya, Z. Chen, "A 3-GHz 70-Mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply," IEEE J. Solid-State Circuits, vol. 41, pp. 146-151, Jan. 2006.

Saibal Mukhopadhyay, Rahul M. Rao Jae-Joon Kim, and Ching-Te Chuang, "SRAM Write-Ability Improvement With Transient Negative Bit-Line Voltage," IEEE trans. On VLSI systems, vol. 19, no. 1, pp. 24-32, Jan. 2011.

Ming-Hung Chang, Yi-Te Chiu and Wei Hwang, "Design and Iso-Area Vmin Analysis of 9T Sub-threshold SRAM With Bit-Interleaving Scheme in 65-nm CMOS," IEEE trans. on ckt. & systems, vol. 59, no. 7, Jul. 2012.

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