Scaling rules will finally reach fundamental limits of both materials and devices currently being using in CMOS devices. To keep with this international technology roadmap for semiconductors projections, (ITRS), considering the number of issues with continued MOSFET scaling [37,38] several numbers of innovative materials, device and alternative process techniques will become increasingly important. To maintain the device scaling reduction of gate oxide thickness is necessary, including threshold voltage and capacitance. For high performance devices in 2006 ITRS an equivalent gate oxide thickness (ETO) of less than 1nm is needed. However, the fundamental limit of the CMOS process will be reached in the near future and quantum mechanical effects need to consider. The gate leakage current increases rapidly due to the direct tunnelling when the device size decreases. And also poly-silicon boron penetration effect in to the channel and gate control reduces become significant for PMOSFETs . SiO2 and poly-silicon materials are effected by the primary issues for the scaled devices, for continuous scaling alternative materials are necessary to achieve low ETO and gate electrode characteristics. For advance devices both high dielectric constant (k) oxides and metal gate electrodes are necessary. The issues of high-k dielectrics and metal gates will be discussed in detail in the following sections [40,41].
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Dual metal electrodes like Ru, Ru-Ta alloy, TaN and TaSiN on low EOT single layer HfO2 and stacked HfO2/SiO2 gate dielectrics will be presented. We know that HfO2, HfO2/SiO2 and SiO2 have a similar work function. In this chapter we are going to discuss the properties of different metal alloys with underlain electrodes.
As we discussed earlier metal gate electrodes are needed to reduce the gate depletion problems which are associated with usual poly silicon gates. And poly silicon gates also suffer from Fermi level pinning on high-K dielectrics . This leads to introduction of metallic gate electrodes on high-K dielectrics. For bulk CMOS devices, the work function of metals should be near the conduction and valence band edge of silicon, i.e ~5.2eV for PMOS and 4.1 eV for NMOS devices .
3.1 Alternative Gate Dielectric Materials
As discussed in the previous section, as the channel length of MOSFETs scales down to sub-70 nm feature size, a corresponding SiO2 gate oxide with a thickness less than 1.5 nm will be required. At this thickness, the conventional thermally grown SiO2 gate oxide will approach its physical thickness limit due to three major problems: exponential increase in tunnelling leakage current with decreasing film thickness, poor reliability, and undesirable boron diffusion from the poly-Si gate through the oxide. New gate dielectric material with a high dielectric constant (k) to replace the SiO2 will allow the use of a physically thicker gate dielectric layer while maintaining the same control of inversion charge. With a thicker insulating layer, the concern of a high tunnelling current through the gate oxide and other reliability issues may be solved efficiently. using a 3.0 nm thick high-k gate dielectric layer may improve the capacitance by 60% and decrease the leakage current density by 2 orders of magnitude.
High-k dielectrics materials like BaSrTiO3 and SrTiO3 suffers from very small band gaps but they produce very high gate capacitances.  and also high-k dielectrics are not suitable for use in MOSFETS because materials with high dielectrics constant can leads to field induced barrier lowering (FIBL) which can degrade the shot channel effect further . Other high-k materials like Ta2O5 and TiO 2 also have lower barrier heights and also we have to concern that at high temperature there is a large interaction with poly-silicon or metal gate electrodes. [46,47]
The dielectrics such as Al2O3 CeO2 and Y2O3 do not provide significant advantages over SiO2 or Si3N4 because they are relatively low dielectric constants. [48,49] The reports shows that some of the high-k dielectrics are positive candidates for MOS gate dielectrics. These include dielectrics such as La2O3, HfO2 and ZrO2, which have all been proven to be thermodynamically stable on silicon. However, as discussed above, these materials are good diffusers of oxygen resulting in the formation of interfacial layers. Up on temperature annealing another group of dielectrics that have been considered as strong potential candidates involve silicates namely HfSixOy, SrTaO6, ZrSiO4 and ZrSixOy. These multi-elemental oxide are compatible with silicon substrate and are thus stable on it.
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HfO2 and ZrO2 appeared as gifted high-k dielectrics used for ultra-thin gate dielectric application at the same time and it was reported that both films have promising characteristics such as low leakage current, good interface properties (Dit~10 11/eV-cm2 and and excellent reliability properties [51,52]. However, during the past several years, hafnium
based metal oxides and silicates have received significant attention as the most promising
candidates for alternative high-k dielectric applications due to high dielectric constant, large
barrier offsets, and thermal, chemical stability with poly silicon gates. In addition, an ultra thin HfO2 gate dielectric with an effective oxide thickness of 0.9 nm was obtained. Lee et al. reported that their HfO2 film maintained its high quality after a high temperature boron dopant activation (950°C for 30seconds) and also showed very good leakage current behaviour (0.23 mA/cm2 at Vg = 1 V) [53,54]. Hafnium silicates, with a dielectric constant around 11 are also being pursued as gate dielectric candidates for the 45 nm gate length CMOS technology .
Even though many research efforts have aggressively studied and solved several issues associated with the high-K dielectric, there are still many challenges for the process and integration of high k dielectrics.
3.2 Alternative Gate Electrode:
From several decades polysilicon is used as a gate electrode in MOSFET devices. However, due to the aggressive scaling of CMOS technology the polysilicon gate technology faces many problems when the gate is biased to inversion mode a depletion layer is formed at the gate oxide and polysilicon interface and this depletion region is added to the total oxide thickness which can decrease the gate capacitance and also decrease the device current and transcoductans. If a thinner dielectric is used the depletion layer associated with capacitance at the poli-Si/gate dielectric interface become significant.
Another issue is increase in sheet resistance of the polysilicon gate which reduces the speed of the circuit. the depletion level of polysilicon gate has been increased to reduce the depletion capacitance and sheet resistance but the doping level of polysilicon is limited to 1021 cm-3 which may not possible to recover the capacitance. As the MOS device scaling is continues further, boron penetration in to the gate dielectric also occur with effects the device's threshold voltage. The Fermi level pinning problems also occur when polysilicon gate electrodes are deposited on high K dielectrics. To avoid this problem metal gates are required to replace polysilicon gate electrodes .
3.3 New Dual metal gate:
New metal gates have to obey many requirements which include appropriate work functions, good thermal/chemical interface stability with underlying dielectric and high carrier concentration and process compatibility with current and future CMOS. A metal gate should have an appropriate work function for NOMOS or PMOS devices. This implies a work function of NMOS as ~4eV for NMOS devices and ~5eV for PMOS devices. For CMOS processing midcap metal gates and dual metal gates can be used however with a more complex process integration scenario. due to the easy of integration the midcap work function metals are considered, which are not suitable for the bulk CMOS device scaling due to the high threshold voltage which cannot be reduced by lowering the substrate doping which leads to difficult in controlling the shot-channel effects. Due to this reason we required two different gate metals with work function near to the conduction and valence band edges of Si . And also perform good thermal stability with the dielectric. In addition oxygen diffusivity should be low and other dopents of the metal gate are necessary. And moreover candidates should have high carrier concentration to avoid gate depletion effect.
Research on alternative metal gate electrodes is going on in different metals including elemental, nitrides, silicates, and alloys [55-58]. Metal gate electrodes have been successfully incorporated into the CMOS process with high carrier concentration and they are no gate depletion effect. Reports also explain that metal films have above 1022cm-3  carrier concentration higher than the poly-Si films.
Candidates with work function near to 4eV for NMOS such as Al, Ta, Mo, Zr, Hf, V and Ti work function near to 5eV for PMOS such as Co, Pd, Ni, Re, Ir, Ru and Pt. There are also several metal oxides such as RuO2, IrO2, ZnO, MoO2, ReO2, In2O3 SnO2, OsO2, and metal nitrides like TiNx, MoNx, WNx, TaNx, TaSixNy. Typically metal oxide work function is higher than the corresponding metal because of the Fermi level change.
3.4 Dual metal gate electrodes:
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From recent reports Fermi level pinning is occurred when the reaction between the poly
Silicon gated and a metal gated electrode with the underlying dielectric. And in the future the threshold voltage shift in MOSFET devices. Fermi level pinning occurs when states at the interface are charged and causes dipole which drives the band alignment to change so that a zero dipole will exist. This tends to shift the Fermi level towards the charge neutrality level and hence pinning of the Fermi level occurs at the interface. For Hf-based dielectrics, the interfacial Si-Hf bonds are believed to be the main mechanism creating dipoles. This dipole pins the Fermi level just the poly-Si conduction band and thus increases the threshold voltage for both NMOS and PMOS devices [61-62]. And also positive charge formation is also a major problem which reduces reliability for CMOS technologies. The main focus of the project is to study the impact of positive charge formation on HfO2/SiO2 stacks. Dual metal electrodes are introduced and replaced instead of polysilicon. Which eliminate poly-Si depletion and boron penetration problems and also this metal alloys are stable at high temperatures up to 1000oC. There gate insulation properties, work function (Ñ„m). Different types of gate alloys with their properties are explained in detail.
3.5 Different type of metal alloys with their properties:
For low ETO single layer HfO2 and HfO2/SiO2 gate dielectrics the dual metal electrodes such as Ru, Ru-Ta alloy, TaN and TaSiN were investigated. HfO2 and SiO2 the work function values were similar. All these metals have good electrical properties on SiO2 gate dielectrics. These properties provided the justification of analyzing them on high-k dielectrics.
Ru has high work function 5.1 eV, very low resistivity 6.7Î©Âµcm, high melting point 2334oC. Thermal expansion coefficient is 6.4x 10-6oC Its atomic mass and radius is 101.1 and 1.30A.[61,62] and have HCP structure with lattice parameter of a= 2.71A c=4.18A it has been extensively studied for DRAM research, forms metallic oxide, it have been well suitable to research in DRAM, it forms metallic oxide, easily etched. It has problems on SiO2/HfO2 at high and low temperatures and also forms toxic RuO4 forms at the oxidation state when Ru is exposed to air/H2O at the room temperature to 200oC, a thin oxide
Ta is bcc structured material with atomic radies of 1.45A and mass of 180.9, lattice parameter of 3.30A. and thermal expansion coefficient of 6.3x10-6/oC it has many advantages for metal gates such as high melting point 3017oC,low resistance 6.7Î©Âµcm,work function 4.2eV and low work function 4.2eV it is easy to etched and easily alloyed however bad contact and high reactive with underling dielectrics. Tantalum nitride appeared to have the correct combination of properties required of a gate electrode of the metal nitrides . Ta1-xNx with x=0.5 to 0.6 found to have the work function of 4.5-4.6eV on SiO2 about 0.25eV larger than that of Ta. Thermal stability on SiO2 can be improved by nitrogen inclusion from 400- 500oC for pure Ta to above 800oC for TaN films. Ta also reduces the thickness of dielectric and reacted with Si forming TaSi2. Thermal stability also improves by the incorporation of nitrogen on SiO2 from 400-500oC for pure Ta to above 800oC for TaN films.
The nitrogen within the dielectric was propositional to the N2 during the deposition of the gate. During sputtering nitrogen was introduced in to the dielectric tends to diffuse to the SiO2/Si interface causes negative shift in the flatband voltage under rapid thermal anneals. When the oxide layer is less than 35A the Ta1-xNx film can diffused through oxide since the Ta-N bond also be reduced by the Si substrate. However this mechanism cannot be happened when we use lower N content with thicker dielectrics. The drawback of Ta1-xNx films is providing thermal stability near midgap work function which is not appropriate for bulk devices. However these materials are still useful for 1. SOI gate electrodes, 2. Capping layers for CMOS bulk devices. But still investigation is going on high-k dielectrics under Fermi level pinning and thermal stability of TaN gate problems.
it has been reported that the TaSixNy metal electrodes are compatible with NMOS devices, provides the right competitive is achieved . It was found that work function 4.2v~4.4v is provided when TaSixNy films on SiO2 and also compatible with NMOS devices and give good thermal stability up to 1000oC in minimum change of EOT, while demonstrating low leakage current. The stability of TaSixNy gates are improved because of the presences of Si and N in the gate electrode, which improves the diffusion barrier properties and also improves the film microstructure at the gate-dielectric interface. 
3.6 Problems effecting dual gate electrodes performance
3.6.1 Electron and hole traps:
As the device size is reduced the electric field in the device increases. These make damage to the oxide and the interface with silicon which have become a key reliability concern for the CMOS technology.,
Earlier work focus on "as-grown" or "background" impurity traps they are three types of impurities 1. Sodium 2. Implants 3. Hydrogen/water.[68,69]
Sodium generates deep and shallow level of electron traps in the oxide by using ultra thing oxide CMOS technology these are negligible. The implants commonly used are arsenic(As),phosphorus(P), and boron(B) both As and P generates traps in the oxide but B wont. The traps concentration was reported as 0.7-1 times of the ion density in the oxide. These traps are generally not implanted for the modern CMOS processes with the careful control of implantation.
Elimination of hydrogen/water from the device is very difficult. It will play a key role in the feature device instability Nicollian et al. when H2O diffusion in to the oxide create traps when aluminium(Al) used as a gate with a capture cross section(Ïƒ) in the order of 10-17cm2. When polysilicon used as gate hydrogen also introduce some traps at the rate of Ïƒ=10-18cm-2 However these traps are absent. When thin gate oxide is used in the current technology during stress electron traps are generated rather than as grown hole traps.
When Hf based dielectrics are used as a gate insulator for the CMOS technology [72,73]. Hf dielectrics hurt from lower carrier mobility and higher instability than compared with SiON.
electron traps generated during the stress and statistically uniformly distributed. both electron trapping and the positive charging occurs in Hf -based dielectrics on instability. The electron trapping can be reduced when the Hf dielectrics become thinner. . Electron trapping have more attention than stress-induced positive charge. In nMOSFETs the positive charge effect is less because of masking effect of positive charge. But it adds negative bias temperature instability (NBTI) in pMOSFET.
3.6.2 Hole traps:
Different types of defects are recognized during gate oxide breakdown interface states electron traps and hole traps. Recent work show electron traps and hole traps are generated during stress. Hole traps are located close to the oxide/Si interface. As the downscaling continuous the positive charge occur near the interface have more importance. Positive charges formed in the oxide is not only due to the hole traps and also due to the other mobile and fixed positive charges introduced in the oxides when it is exposed to high temperature(>1000oC), an anneal in H2 at 450oC or however these mobile and fixed positive charges won't exist in industrial-grade gate oxides, there are two different types of positive charges are generated when holes are trapped. One is cyclic positive charge (CPC) and the other is anti-neutralization positive charges (ANPC). Under negative gate bias both charges are recharged positively without need of external hole injection. When gate polarities are positive the neutralization and charge of CPC is in same speed.
The gate depletion can be removed by the metal gates and allows equivalent oxide thickness of downscaling. The device reliability was unknown when the gate is changed from poly-Si to metal. The main focus of the experiment is how the positive charge formation is effected by the HfO2/SiO2 stacks when TaN gate is used. According to  hole traps leads to the formation of positive charge and non-reactive hydrogen species in the device. However hole trapping occurs during annealing. The hole traps in a typical oxide is of the order of 1012 cm-2 and this traps are located near the oxide-Si interface. During electrical stresses and irradiative positive hydrogen species are formed.
The objective of this work is to study the behaviour of positive charge formation in different gate bias stresses in HfO2/SiO2 stacks. The experimental results shows when positive gate bias stresses is applied on both gate samples positive charge formation is significantly higher in metal gate than in poly-Si gate sample and formation of positive charge is similar in both gate samples under negative bias stress.
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