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3D ICs using through Silicon Via are the latest trend in the market. TSV can be used for 3D stacking at different integration levels: from via first (front end process) to via last (back end process). The electrical performance of the device, refill materials and cost are affected by the type of via integration that is chosen. The paper discusses the Deep Reactive Ion Etching (DRIE) process as applied to design vias of different sizes, shapes and depth. Using the DRIE technique, very high aspect ratios may be achieved in the via first approach as the width of the via is limited. In via last approach however, via is wider which in turn reduces the aspect ration but allows for higher etch rates.
The Through-hole silicon via (TSV) has been accepted as the viable solution to form 3D ICs and emerged as a critical technique to ensure continued scaling, miniaturization, higher density for high performance devices. The advantage of TSV is that, integration of both homogeneous and heterogeneous chips are possible in a single package. The 3D IC industry is moving from the R&D stage to the commercialization stage and hence the economic costs will hold a greater sway on the technology being adopted for mass production. TVS, typically requires some additional process steps which are as follow. (i) Dry etching of vias or holes using DRIE. (ii) Dielectric isolation layer deposition. (iii) Via filling using Cu electroplating, followed by CMP. (iv) Wafer thinning and bonding. Usage of via first, via last or via middle is largely application dependent. Though via last and via middle are mostly in use today, efforts are in progress to gravitate to the via first process from a cost-effective point of view. Several techniques are available for via hole drilling like laser drilling, DRIE and photolithography. Amongst these, the DRIE is the most widely used technique to achieve high aspect ratio. This paper discusses the use of DRIE to form each of the different via integration
Deep RIE is a process that is used to achieve etch depth of hundreds of microns with almost vertical sidewalls. Two techniques may be used for high rate DRIE: cryogenic and Bosch process. However, only the Bosch process is used for production. In Bosch process, two different gas compositions are alternated in the chamber. Plasma containing sulphur hexafluoride (SF6) ions is used to achieve a faster anisotropic etch, while octaflurocyclobutane (C4F8) is used to deposit the chemically inert passivation layer. C4F8 creates the polymer on the surface of the substrate, while SF6 etches the surface. During the physical etching, the polymer is sputtered away on the horizontal surface, leaving the sidewalls intact. Since the polymer dissolves slowly, it builds up and protects the sidewalls during chemical part of etching. Hence this process provides for very high aspect ratio of around 50 to 1. The etch and deposit steps are repeated to form a large number of very small isotropic steps at the bottom of the etched pits. Cycle time may be adjusted optimally. Short cycles give smoother walls while longer ones provide higher etch rates.
Fig. 1. Profile of a DRIE trench with exaggerated scallop effect.
VIA FIRST BEFORE BEOL
The via first integration process is used to form the TSV in wafer fab during the front end process. The via formed using this method are usually small in size with feature size ranging from 2-5 um diameter to 30-50 um depth . These high aspect ratio vias are used for higher density interconnects.
Fig. 2. Via first before FEOL
From left to right: DRIE, Oxidation, Poly-silicon refilling
After the via formation, the wafer will undergo further processing steps. The refilling material has to be such that, it can withstand temperatures greater than 1000 degrees. Hence generally poly-silicon is used for this purpose. The advantage of poly-silicon process is that it does not require any seed layer and the isolation layer may be deposited using the conventional oxidation processes. On the other hand, poly-silicon refilling process is possible only for via widths lower than 5 um. To achieve etch depths of around 150 um or high aspect ratio of 30, we need to use the DRIE with a modified Bosch process. Also, taper, tilt, and the sidewall roughness have to be tightly controlled to ensure the subsequent processes are not affected. For optimum results, fluidic ion and neutral density are believed to be important. An advanced plasma source based on ICP, to provide a combined solution on RF coupling, gas injection, magnetic confinement, materials, geometry etc. is used in with a P type Electrostatic chuck to provide angle deviations less than 0.2 degrees.
Fig. 3. Angle deviation across a 200 nm wafer
For the process to be repeatable, the camber has to be clean, so that there is no build up of process materials along the chamber walls and etch process contamination is avoided. The advantage of via first before FEOL is that only a single DRIE equipment need to be added to the process flow and hence itââ‚¬â„¢s a cost effective integration.
VIA FIRST AFTER BEOL
The vias fabricated using this method are typically larger with sizes ranging from 10-40 um diameter to 70-120 um depths. These vias also used to be referred to as via middle.
Fig. 4. Via first after BEOL
From left to right: DRIE, Oxidation, Cu refilling
The greatest advantage of this process is that vias are formed after the CMOS processing steps, which means a refilling material like copper( as opposed to poly-silicon), with better electrical and thermal properties may be used, without the concern of exposure of wafer to high temperature processes. Fabrication requirements are similar to via first before FEOL however, the dielectric layers that were a part of the FEOL process have to be removed using commonly used dielectric etch processes.
Fig. 5. Via first after BEOL after DRIE and after refilling
After the refilling step has been carried out, a barrier layer and seed layer have to be deposited using PVD and CVD, which is an expensive and time consuming process. Usually a taper of 83 to 85 degrees is required to provide a good step coverage for metal. An alternative method that has been developed to meet the above requirements while also being fast and inexpensive is, the ââ‚¬Å“open mouth processââ‚¬. This process involves creating a feature that enlarges the via entrance hole. This proposed process uses the SF6 and C4F8 mixture initially to create a 70 degree taper for a depth of about 30 um. Then Bosch process is applied for anisotropic etch to obtain a taper angle of 88.8 degrees up to a depth of 180 um.
Fig. 6. Top: Ideal profile; Bottom: open mouth profile
An average etch rate of around 12 um/min may be obtained with uniformities of +/- 2.5 % using this combined process as shown in fig. 7.
Fig. 7. 60umX180um via hole
Since the wafer will be subjected to further thinning, the etch depth is normally limited to 100 um. As the aspect ratio in such cases will be low (5 to 10), a high etch rate may be obtained.
High etch rate
To achieve high etch rates and a high selectivity for photo resist, high dissociation using high plasma density and low plasma potential for high selectivity are needed. Standard RIE systems are not well suited for this purpose as they inherently have a high DC bias which in turn means low selectivity. The Inductively Coupled Plasma (within High Density Plasma sources) is an appropriate choice as it can generate HDP (1011 to 1012 ions/cm-3), provide high gas dissociation and low potential at very high pressures. The fluorine radicals move to the silicon surface within gas phase and react with it to produce volatile SiF4 which are then pumped out from the system.
Si(s) + 4F(g) Ã SiF4(g) + G0 (eq 1)
Parameters like flow rate, pressure and ICP power may be set to obtain a specific partial pressure (F) needed to remove Silicon. The Si etch rate is known to be directly proportional to the number of fluorine radicals reaching the surface.
Fig. 8 Fluorine radical flux rate Vs Si etch rate
Very high etch rates of 50 um/min may be obtained by this method. But as etch rate increases, effective control to obtain an uniform etch throughout the wafer decreases. Hence a P type Electrostatic chuck is used to give a uniform temperature distribution of +/- 0.15 degree over the wafer.
IV.VIA LAST AFTER BEOL
In the integration schemes described previously, vias are etched blind up to a certain specified depth from the device side. However, in the via last approach, since, vias are created after the bonding and thinning, they have to be etched from the backside of the wafer. The dimension of the via is larger than that formed by the via last technique being 5-50um diameter and 30-150 um depth. The vias are etched to a stop layer, usually the first dielectric layer of the FEOL device.
Fig. 9. Via last after BEOL
From left to right: DRIE, Oxidation, Cu refilling
During the operation, the device wafer is temporarily bonded to the wafer carrier, which is usually glass. This wafer bonding restricts further steps to a temperature of 180 to 200 degrees.
DRIE for high aspect ratio oxide etch
A major issue in via last approach is that the backside via metallization should be in contact with the metal pad. To overcome this, the insulating oxide layer should be dry etched to the metal pad after DRIE. After this a con formal dielectric layer should be deposited at low
temperature and the dielectric layer
should be cleared from the bottom via so that the barrier may be deposited and the seed layer may be in contact with the metal pad. The dielectric etch step can be carried out without much difficulty if the via profile is almost vertical. If the profile is tapered, photolithography step needs to be additionally carried out to remove the dielectric layer from the bottom of via but at the same time keeping a thick sidewall to provide good electrical isolation. This requirement for a very specific lithography for a very high aspect via is a major limitation for the acceptance of the via last approach. However, the available technology, i.e., HDP dielectric etcher, used to remove insulating layers beneath metal pads may be extended to be applicable for high aspect ratio etching of the buried oxide layer after DRIE of Si as shown in Fig. 10.
Fig. 10. Etching profile of buried oxide layer below Si layer.
The buried Oxide layer was removed at an etch rate of 500 um/min, with a 10:1 selectivity as compared to the photo resist mask used to define the feature.
Different integration schemes like Via first(prior to FEOL), Via first(after BEOL) and Via last(after BEOL) were examined and the challenges in the etching processes of each of these vias were addressed. The available technology was further extended and applied to buried oxide layer etch. The existing Bosch process was applied with minor modifications as suited to each via integration process requirement, to either facilitate greater aspect ratio, or higher etch rate as required.