# Construct And Test A Voltage Amplifier Biology Essay

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Apply the voltage divider biasing method to set the DC operating point (VGSq , IDSq) . Verify the estimated DC operating point with the measured data.

Investigate the effect of frequency changes on the voltage gain of the amplifier, measure its frequency response and obtain its operating bandwidth.

Investigate the capacitance effect on the frequency response of the common source JFET amplifier

## Important Notes

All related calculation questions that does not require experimental data must be answered before coming to the lab. You are required to show all the calculation steps when requested by the lab instructor. During the evaluation session, your lab instructor may request you to demonstrate how the measurement data is obtained and explain your experimental results.

You are advised to attempt the theoretical questions asked in the lab sheet before coming to the lab. The lab session is only 3 hours and will be mostly spend on collecting experiment data, analyzing result and comparing the data with the calculated value. Before coming to the lab, you will also need to study the related theory from lecture material of chapter 1 and topics involving JFET device characteristic, JFET biasing and JFET amplifier from the textbook. This is important so that you know what result will be expected from the experiment. In order to answer the questions in the labsheet, you also need to make reading preparation.

## Background Theory

An amplifier is a circuit that increases/decrease the input signal value and in this experiment the signal to be amplified is the voltage. In this experiment you are going to investigate frequency response characteristic of a voltage amplifier circuit using the N-channel JFET device

Most amplifiers have relatively constant gain over a certain range of frequencies. This range of frequencies is called the bandwidth of the amplifier. The bandwidth for a given amplifier depends on the circuit component values, the type of active components and the dc operating point of the active component. When an amplifier is operated within its bandwidth, the current gain, voltage gain, and power gain values are referred to as midband gain values. A simplified frequency-response curve that represents the relationship between amplifier gain and operating frequency is shown in Figure 1.

Ap drops at lower frequencies

Ap drops at higher frequencies

fc1

fc2

Bandwidth

0.5Ap(mid)

Ap(mid)

Frequency

Power Gain

Mid-band

Figure 1: A simplified frequency response curve

As the frequency-response curve shows, the power gain of an amplifier remains relatively constant across a band of frequencies. When the operating frequency starts to go outside this frequency range, the gain begins to drop. Two frequencies of interest, and , are the frequencies at which power gain decreases to approximately 50% of . The frequencies labeled and are called the lower and upper cutoff frequencies of an amplifier, respectively. These frequencies are considered to be the bandwidth limits for the amplifier and thus bandwidth BW is given by

## .

The geometric average of and is called the geometric center frequency fo of an amplifier, given by

## .

When the operating frequency is equal to , the power gain of the amplifier is at its maximum value.

Frequency response curves and specification sheets often list gain values that are measured in decibels (dB). The dB power gain of an amplifier is given by

## .

Positive and negative decibels of equal magnitude represent reciprocal gains and losses. A +3dB gain caused power to double while a -3dB gain caused power to be cut in half.

Using the basic power relationships, and , the power gain may be rewritten as

The voltage component of the equation is referred to as dB voltage gain. When the amplifier input and out resistances are equal

## . ()

Thus, when the voltage gain of an amplifier changes by -3dB, the power gain of the amplifier also changes by -3dB.

## Low Frequency Response of FET Amplifier

In the low frequency region of a single stage FET amplifier as shown in Figure 2(a), it is the RC combinations formed by the network capacitors and the network resistive parameters that determine the cutoff frequency. There are three capacitors - two coupling capacitor and , and one bypass capacitor, . Let us assume that , and are arbitrarily large and can be represented by short-circuit. The total resistance in series with is given by

where is the input impedance of the amplifier circuit. The power supplied by the signal generator is . However, the reactance XCG of capacitance is not negligible at very low frequencies. The frequency at which Pin is cut in half is when . Thus the lower half-power point for gate circuit occurs at frequency

R1

RS

R2

RL

RD

CD

CS

CG

RG

+VDD

Vgen

D

S

G

Vin

Figure 2(a): Schematic diagram of a JFET amplifier.

R1||R2

RS

RL

RD

CD

CS

CG

RG

Vgen

VG

D

S

G

Vin

Figure 2(b): JFET amplifier low-frequency ac equivalent circuit

CD

VD

D

gmVgs

RD

RL

S

Figure 2(c): Approximate drain circuit of JFET amplifier (assuming the resistance of the JFET drain terminal, rd, is much larger than RD).

When and are arbitrarily large and can be represented by short-circuit, the drain circuit of the JFET amplifier is as shown in Figure 2(c). At high frequency where CD can also be represented by a short-circuit, the output power to load resistor RL is . At low frequencies where the reactance XCD of capacitance is not negligible, Pout is cut in half when . Thus the lower half-power point for drain circuit occurs at frequency

At the half-power point, the output voltage reduces to 0.707 times its midband value. The actual lower cutoff frequency is the higher value between fLG (determined by CG) and fLD (determined by CD).

## High Frequency Response of FET Amplifier

The high frequency response of the FET is limited by values of internal capacitance, as shown in Figure 3(a). There is a measurable amount of capacitance between each terminal pair of the FET. These capacitances each have a reactance that decreases as frequency increases. As the reactance of a given terminal capacitance decreases, more and more of the signal at the terminal is bypassed through the capacitance.

R1

RS

R2

RL

RD

CD

CS

CG

RG

Cgd

Cgs

Cds

Vgen

+VDD

CL

Figure 3(a): JFET amplifier with internal capacitors that affect the high frequency response.

R1||R2

Cout(M)

RG

Vgen

Cin(M)

Cgs

Cds

CL

RL||RD

Figure 3(b): FET amplifier high frequency ac equivalent circuit.

The high frequency equivalent circuit for the FET amplifier in Figure 3(a) is shown in Figure 3(b), including all the terminal capacitance values. is replaced with the Miller equivalent input and output capacitance values given as

and

AV

Cgd

AV

Cin(M)

G

D

G

D

Cout(M)

Figure 4: Miller equivalent circuit for a feedback capacitor

Note the absence of capacitors , , and in Figure 3(b), which are all assumed to be short circuit at high frequencies. From this figure, the gate and drain circuit capacitance are given by

and

where is the input capacitance of the following stage. In general the capacitance is the largest of the parasitic capacitances, with the smallest. The high cutoff frequencies for the gate and drain circuits are then given by

and

where and . At very high frequencies, the effect of is to reduce the total impedance of the parallel combination of , , and in Figure 3(b). The result is a reduced level of voltage across the gate-source terminals. Similarly, for the drain circuit, the capacitive reactance of will decrease with frequency and consequently reduces the total impedance of the output parallel branches of Figure 3(b). It causes the output voltage to decrease as the reactance becomes smaller.

## Procedures

Before connecting the circuit of Figure 5, measure the actual resistance of R1, R2, RD, RS and RL as accurate as possible with a digital multimeter (set it to the best resistance range) and record the measured values.

Connect the common source JFET amplifier circuit as shown in Figure 5 using a breadboard (refer to Appendix C). Do not connect the power supply and the function generator to the circuit yet. Keep the connecting wires on the breadboard as short as possible (< 3 cm) to reduce unwanted inductance and capacitance in your circuit.

Set the power supply output to +12V. Connect its output to the circuit and measure its voltage VDD(meas) as accurate as possible with the multimeter. Calculate the gate DC voltage VG(cal) using the voltage-divider rule.

Measure the DC voltages VG, VD and VS at G, D, and S pins of the transistor as accurate as possible. Note that the measured VG should be closed to the calculated VG(cal), and VS should be > VG since VGS must be < 0 V for N-channel JFET.

Before connecting the function generator to the circuit, use an oscilloscope to measure the output voltage of the generator and set it to 200 kHz sine-wave with a peak-to-peak voltage of 0.1V. Press the attenuation button (ATT) of the generator for easy adjustment of its output voltage.

Connect the generator output to the circuit. Using Channel 1 (CH1) of the oscilloscope (set at AC input coupling), probe the input voltage vin. Using Channel 2 (CH2) of the oscilloscope, probe the load resistor RL, as shown in Figure 5. Set the trigger source of the oscilloscope to CH2. Adjust the trigger level on the oscilloscope to obtain stable waveforms. Make sure the variable (VAR) knobs of the oscilloscope are set at the calibrated (CAL'D) positions.

## G

Figure 5: A common source JFET amplifier

Adjust the Volts/div and Time/div to display the waveforms on the oscilloscope screen as big as possible with one to two cycles. Sketch the input AC voltage (vin) and the load voltage (vL) waveforms on the graph. Record the Time/div and Volts/div used. Note that the input and output waveforms should be approximately 180o out of phase.

From your graph, determine VL(pp) and Vin(pp) which are the peak-to-peak voltages of vL and vin, respectively. Calculate the voltage gain (Av) of the JFET amplifier circuit at 200 kHz. Ask the instructor to check all of your results. You must show the oscilloscope waveforms to the instructor.

Sweep the frequency of the function generator from 1 kHz to 550 kHz (use smaller frequency steps near the half-power point while larger steps can be used at mid-band frequencies). Record the peak-to-peak voltages of vin (CH1) and vL (CH2) and calculate the dB magnitude of the voltage gain Av. Use both coarse and fine adjustment knobs of the function generator for frequency adjustment.

Plot a curve of Av versus frequency.

Calculate the lower cutoff frequency fLD(cal) (use the measured RD and RL values). Set the frequency to 20 kHz. To measure the lower cutoff frequency (fLD), decrease the generator frequency until VL(pp) decreases to 0.707VL,mid-band(pp), where VL,mid-band(pp) is the VL(pp) value in the mid-band.

Set the frequency to 300 kHz. To measure the upper cutoff frequency (fHD), increase the generator frequency until VL(pp) decreases to 0.707VL,mid-band(pp).

Determine the bandwidth (BW) and the geometric center frequency (fo) of the amplifier from the above measurements. Ask the instructor to check all of your results. You must show the oscilloscope waveforms at 550 kHz to the instructor.

Design or modify the circuit in Figure 5 in order to measure the parameter of the device, namely Gate-Source Cutoff Voltage (VGS(off) or Vp ) and Zero-Gate Voltage Current (IDSS) . These two values can be used in the Shockley equation ID = IDSS ( 1 - VGS/Vp)2 . Hint: You can use a potentiometer and/or negative power source in the circuit. By solving the simultaneous equation of the Shockley equation and the load line equation, you can obtain the calculated value for the Q point VGSQ, VDSQ, IDQ. . Compare this with the measured value.

## Report Submission

Submit your report on the same day immediately after the experiment.

## Appendix A - Designing Voltage-Divider Bias for JFET

Similar to designing a bipolar transistor circuit, a JFET needs to be biased at the correct dc operating point before it can function properly as an amplifier. There are a number of biasing configurations available, such as gate bias, self-bias, and voltage-divider bias. The self-bias and the voltage-divider bias use negative dc feedback to stabilize the operating point of the JFET against parameter variation of the JFET. DC operating point in this context refers to the drain-to-source voltage VDS and the drain current ID of the JFET. A stable operating point means VDS and ID do not change much with temperature and when we change one JFET with another JFET of similar part number. A voltage-divider bias employing the general purpose N-channel JFET 2N5457 is shown in Figure A1.

2N5457

Figure A1 - Schematic of the dc bias using voltage-divider bias scheme

## A.1 JFET Large Signal Parameters

From the datasheet of 2N5457, the following parameters are given at temperature of 25oC.

Table A1 - Minimum and maximum large signal parameter for 2N5457

## Maximum

Gate Source Cutoff Voltage (VT)

-0.5V (VTmin)

-6.0V (VTmax)

Zero-Gate Voltage Drain Current (IDSS)

1.0mA (IDSSmin)

5.0mA (IDSSmax)

## A.2 Transconductance Curve

When the JFET is biased in its active region, the channel between drain and source terminals is in "pinched-off" state. The drain current will be largely independent of the drain-source voltage VDS and will only depend on the gate-source voltage VGS. Thus unlike the bipolar transistor which is a current controlled device (the collector current IC is a function of base current IB in active region), the JFET or FET in general is a voltage controlled device. The relationship between VGS and ID in the active region is given by:

(1)

Plotting (1) for the two sets of large signal parameter (VTmin, IDSSmin) and (VTmax, IDSSmax) results in the curves of Figure A2. These curves are known as transconductance curves because they relate current to voltage.

VGS

IDmax

IDmin

Note:

IDmax refers to the curve when parameters is given by (VTmax, IDSSmax) while IDmin for parameter (VTmin, IDSSmin).

IDSSmax

IDSSmin

Figure A2 - The transconductance curve for the JFET 2N5457

## A.3 Determining the Load Line

From Figure A1, (2)

and (3)

Since (4)

Substituting (3) into (4), we obtain the load line relationship:

(5)

Equation (5) is in the form

So it is a straight line where m is the gradient of slope of the line and c is the intercept point of the line with the ID axis.

Let us select (ID_max, VGS_max) and (ID_min, VGS_min) to be the two desired operating points on the maximum and minimum transconductance curves. This is shown in Figure A3. A straight line can be drawn joining these two points; this line will be our dc load line. The slope and intercept point of the line will determine the value of biasing resistors R1, R2 and RS. The value of ID_max and ID_min are selected based on the allowable change in drain current due to parameter variation in the JFET.

VGS

(VGS_max,ID_max)

(VGS_min,ID_min)

IDmax

IDmin

Allowable change in drain current ID due to parameter variation.

Figure A3 - Required maximum and minimum operating points and the dc load line

The only requirement for the two operating points would be:

|ID_max| > |ID_min| (6)

## A.4 Finding the Values of Bias Resistors

The procedure of designing the voltage-divider bias for JFET is now summarized as follows:

## Step 1

Fix ID_max and ID_min, the drain current at the maximum and minimum transconductance curves. This will determine the allowable change in drain current.

## Step 2

Find VGS_max and VGS_min.

(7a)

(7b)

## Step 3

Determine the slope and intercept point for dc load line, from (5).

(8a)

(8b)

(9)

(10)

Arbitrary choosing a suitable R2. Then R1 is given by , from (2):

(11)

## Step 4

Choose a suitable value for RD. Find the corresponding drain voltage.

(12a)

(12b)

## Example - For this Lab Experiment

From Figure A3, we would like the dc load line to intercept the maximum and minimum transconductance curves when VGS is negative. From Equation (6), let us choose:

## ID_min = 0.85mA

From (7a) and (7b):

## VGS_min = -0.039V

From (8a) and (8b):

Hence from (9):

And from (10):

## VG = 3.46V

Finally from choosing R2 = 10.0kï- :

from (11), R1 = 24.7kï-

If we choose a drain resistance of RD = 3.3kï-, from (12a) and (12b)

## VD_min = 7.05V

Percent error in drain voltage;

## Error = (9.20 - 7.05)/ 7.05 = 22.33%

A plot of the load line is shown in Figure A4.

VGS

ID