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This paper represents a new enhanced Colpitts oscillator which is designed based on gm-boosting of a conventional Colpitts oscillator. The proposed topology increases the negative resistant and enhances the start-up difficulty of the conventional Colpitts oscillator. This enables the Colpitts oscillator to operate in low-power consumption. Moreover, it's differential and balanced structure helps limit even-order harmonics and degrades the common mode noise effects in output. The proposed circuit is designed using TSMC 0.18μm technology and is simulated under 1.8V supply voltage in ADS. Simulations show the output phase noise of -140 dBc/Hz at 1MHz offset frequency when the operating frequency is 1GHz.
Key words: Colpitts Oscillator, gm-boosting, Oscillation frequency, Phase noise
Oscillators are important building blocks of any communication transceiver-receiver system. They have different functionalities and applications such as local oscillators for up-down conversion of the information-bearing signals, and carrier signal generators for modulations. Oscillators can be implemented in different structures such as ring oscillators, LC-tank oscillators, distributed resonator based oscillators, voltage controlled, etc. Fully integrated oscillators are very essential parts in any radio frequency (RF) integrated transceivers for carrier generation. Digital systems and also transceivers in modern communication systems need to high purity oscillators for low jitter clock generation. (Aparicio and Hajimiri, 2002; Hajimiri and Lee, 1998; Dunn and et al., 2003; Vaananen, Metsanvirta, andTchamov, 2001).
Today, by advances in communication systems, modern communication systems have to be design to be compatible with different communication standards and operate in different frequency bands. Therefore the design criteria and necessities for the oscillators are getting tougher. For example, nowadays mobile phones support multiple standards for wireless communications. Modern phones are being designed to cover different frequency bands and multiple communication standards such as GSM, PCS/DCS and also Bluetooth with minimum chip area.
The most important design challenge of a fully integrated CMOS LC voltage-controlled oscillator (VCO) is to design it with minimum phase noise and power consumption. On the other hand, the quality factor of the LC tank will be decreased by widening the tuning range of the VCO; therefore it is needed to have design the active network with higher trans-conductance and this in turns causes to higher power consumption.
Several optimized structures for oscillators and VCOs are designed to fulfill the need for low power and low phase noise. Among these architectures, the differential cross coupled oscillators attracted much interest due to their ease of implementation and differential output which results in a good phase noise behavior. But, on the other hand, the single ended Colpitts oscillators despite their superior phase noise performance were rarely used as integrated circuits because of their single-ended output and poor startup condition that leads higher power consumption. Alternatively, the cross coupled differential oscillators have a higher loop gain and therefore lower power consumption but the phase noise behavior of them is worse.
In order to overcome the difficult startup condition of the Colpitts oscillators a new gm-boosted differential Colpitts oscillator is proposed in this paper that enhances the startup condition and therefore minimizes the power consumption. The proposed Colpitts structure meets both of the phase noise and power requirements in RF integrated circuits.
The design flow and analysis of the proposed structure will be explained in next sections. The rest of this paper is as follows: In section II, the design procedure of the proposed topology through gm-boosting technique will be described. Section III, analyses the phase noise behavior of the proposed oscillator. In
Fig. 1. (a) Gate-Drain feedback Colpitts oscillator (b) small signal model.
section IV, the designed VCO type of the proposed circuit will be introduced. Simulation results are presented in section V and finally section VI gives the conclusions.
2. DESIGN PROCEDURE
A conventional Gate-Drain feedback (G-D) Colpitts oscillator is shown in Fig. 1.a (Razavi, 2001). The circuit oscillates if the negative resistant seen from the Gate-Drain terminal compensates the inductor losses (Razavi, 2001). To achieve the condition needed for oscillation, we should calculate the impedance seen from the Gate-Drain terminal. This impedance can be easily calculated using the small signal model of Fig. 1.b. Writing KCL at nodes Vgs and VD, results in:
And the impedance seen from the Gate-Drain will be calculated as:
Considering s=jω, the real value of Z is:
Therefore, the oscillation startup condition can be written as follow where RL is the series resistant of the inductor.
From (5), in order to have a larger negative resistant, we should increase the gm value by choosing a larger value of Ib that leads to a higher power consumption that is not desirable. Therefore, the negative resistant should be increased in another way.
Fig. 2.a shows the proposed gm-boosted Colpitts oscillator topology. As seen, a negative resistant of is added in drain to increase the negative resistant. Now from the small signal model of Fig. 2.a and writing KCL at nodes Vgs and VD, the impedance seen from the Gate-Drain terminal will be calculated as:
Fig. 2. (a) Proposed gm-boosted Colpitts topology (b) small signal model.
Fig. 3. Simulated effective real value of Z for the conventional G-D Colpitts oscillator of Fig. 1 and the proposed topology of Fig. 2. (C1=C2=4nF, gm=7.13-10-3 mho)
Also, the real value of Z is:
From (8), the negative resistant of the proposed topology is larger than that of the conventional Colpitts oscillator if the following condition is satisfied:
It should be mentioned that in both of the Fig. 1 and Fig. 2 topologies the oscillation frequency is:
The simulated real values of the impedances seen from the Gate-Drain terminal of the conventional G-D Colpitts oscillator and the proposed topology are plotted with respect to frequency in Fig. 3. As seen in this figure, the proposed topology has a larger negative resistant with respect to the conventional configuration and therefore it improves the startup condition and decreases the power consumption (Li, Shekhar, and Allstot, 2005).
Fig. 4 shows the final structure of the proposed enhanced differential oscillator. As seen, in this structure, the current sources are replaced by the cross-coupled PMOS transistors M3 and M4 which provide the negative resistant at drains of M1 and M2 and enhance the startup condition. Also, replacing the current
Fig. 4. The proposed enhanced differential CMOS Colpitts oscillator.
sources with cross-coupled transistors leads to differential oscillation and reduces the phase noise that will be discussed in next section.
3. PHASE NOISE DISCUSSION
As seen in Fig. 4, the proposed structure has a differential structure which reduces the effects of common mode noises like substrate noise on the output of the oscillator. In this section, we will perform the comparison between phase noise behavior of the proposed oscillator and the conventional G-D Colpitts oscillator of Fig. 1.
By using the cross-coupled configuration in drains of the transistors M1 and M2, the oscillation amplitude can be increased up to VDD which decreases the phase noise (Andreani, Wang, Vandi and Fard, 2005). Now, referring to a general oscillator, it is known that the presence of a noise source between one of the oscillator nodes and ground causes a phase noise L at the offset frequency Δω, given by (Aparicio and Hajimiri, 2002):
where qmax is the maximum amount of the electrical charge that will be loaded onto the capacitance of the node, across an oscillation period. is power density of the noise current and is the ISF of the noise source (Andreani, Wang, Vandi and Fard, 2005).
In order to have a fair comparison, suppose that both of the proposed enhanced Colpitts oscillator and the conventional G-D Colpitts oscillators have the same circuit parameters (C1, C2, L, M,…). In this situation, the phase noise produced by the LC tank and the switch transistor (M1 or M2) is the same for both of the topologies. But, the most important phase noise difference of the two topologies is resulted from the bias current source in conventional Colpitts oscillator and the PMOS cross-coupled transistors in the proposed circuit. Assuming that the current source transistor in conventional G-D Colpitts oscillator and the PMOS cross-coupled transistors have the same size, the amount of channel noise is the same in both of the topologies and is calculated from the following equation:
where k is the Boltzmann constant, T is temperature and gmp is the trans-conductance of the PMOS transistor. Now, assuming that the current source PMOS transistor in conventional Colpitts oscillator operates in saturation region all the times, the trans-conductance of it can be assumed to be constant all the time and its ISF can be expressed as (Andreani, Wang, Vandi and Fard, 2005):
Fig. 5. A typical waveform and ISF of the bias current and PMOS cross-coupled transistors of the G-D Colpitts oscillator and the proposed enhanced oscillator (Andreani, Wang, Vandi and Fard, 2005).
But the cross-coupled PMOS transistor in the proposed topology has not a constant trans-conductance and its trans-conductance is expressed by the following equation:
Valid for where A is the oscillation amplitude and:
Therefore, the effective ISF for the PMOS cross-coupled transistors is expressed as:
And the square rms value of is calculated as:
The square rms value of can be easily calculated and is equal to 0.5. A typical plot of the and is shown in Fig. 5. As can be easily understood from the Fig. 5 and also shown in (Andreani, Wang, Vandi and Fard, 2005), the rms value of is much larger than the rms value of . Therefore, as mentioned before, because it is assumed that both of the proposed enhanced and the G-D conventional topologies have the same circuit parameters and from (11), (13), (16) and Fig. 5, the phase noise of the proposed enhanced Colpitts oscillator is smaller than the conventional G-D Colpitts oscillator and this means that the proposed topology has a superior phase noise behavior.
4. VCO PROTOTYPE OF THE PROPOSED OSCILLATOR
In many applications such as Phase Locked Loops (PLLs) we need a voltage controlled oscillator (VCO). The proposed Colpitts architecture can be easily designed to act as a voltage controlled oscillator. It can be done by adding two varactors between the outputs (drains of the switch transistors M1 and M2). The designed VCO version of the proposed oscillator is shown in Fig. 6.
Fig. 6. VCO type of the proposed enhanced Colpitts oscillator.
And because in differential oscillation Cvar is used in place of C2, the oscillation frequency of the designed VCO is:
5. SIMULATION RESULTS
The proposed gm-boosted enhanced differential Colpitts oscillator and conventional G-D Colpitts oscillator have designed and simulated in Advanced Design System (ADS) software. The parameters of the designed circuits are shown in Table I. In order to have a fair comparison between the performance of the proposed oscillator and the conventional G-D Colpitts oscillator, the two circuits are designed using the same parameters.
Table 1. The design parameters of the proposed oscillator and the conventional G-D topology
Switch Transistors (M1, M2) Size (W/L)
Cross-coupled PMOS Transistors Size (W/L)
Fig. 7 shows a sample transient differential output waveform of the proposed oscillator. As it can be seen in this figure, the oscillator has a relax startup which is a superior performance with respect to the single output G-D Colpitts oscillator.
Fig. 7. Startup operation of the proposed differential Colpitts oscillator.
Phase noise is the most important metric of an oscillator. The phase noise performances of the proposed Colpitts structure and the conventional G-D topology have been studied section III and it has been shown that the proposed topology has a better phase noise performance with respect to the conventional topology due to a lower rms value of the cross-coupled transistors ISF. A comparison between the phase noise of the proposed oscillator and the conventional G-D Colpitts oscillator is shown in Fig. 8. As seen, this figure proves our analysis of the phase noise behavior.
Another important metric of a voltage controlled oscillator (VCO) is its tuning curve which is plotted in Fig. 9 for the proposed topology. The tuning curve shows the output frequency range that the VCO can generate versus the input tuning signal. The slope of the tuning curve describes the tuning sensitivity KVCO which is an important parameter in designing of the RF building blocks such as phase locked loops (PLLs). In ideal cases, KVCO is a constant parameter but in practice it is not the case especially when the frequency is closed to the minimum or maximum of the tuning curve as is shown Fig. 9.
Fig. 8. Comparison between the phase noise of the proposed oscillator and the conventional G-D Colpitts oscillator.
Fig. 9. Simulated tuning curve of the designed voltage controlled oscillator.
In this paper, a new configuration for the MOS differential Colpitts oscillator is presented that has a better startup behavior than the conventional Colpitts oscillator. This is done using a negative resistant in drain of the conventional G-D Colpitts oscillator in place of the bias current. The VCO type of the proposed topology is also designed. The proposed oscillator circuit is analyzed from different aspects such as phase noise and startup condition. The simulations all show the better performance of the proposed new topology with respect to the conventional configuration.