A Led Is A Semiconductor P N Junction Biology Essay


The fabrication process of the nano-LED devices is explained in this chapter. The process includes making nanogap devices and growing ZnO nanostructures between the nanogaps. Sharp tips are formed on the top silicon layer of the wafer by wet chemical etching. The silicon tips are then suspended by removing the SiO2 underneath. The tips are covered with Ni after evaporation and they act as the electrical contact for the nano-LED. The nanogap between the tips is filled with Zn after another evaporation process. The Zn is converted to ZnO by thermal oxidation, which is the semiconductor part of the nano-LED for emitting light.

2.1 Fabrication of Nanogap Devices

The nanogap devices are fabricated on a SOI wafer by optical lithography and anisotropic wet chemical silicon etching with a unique double-layer etch mask72.

The substrate of the SOI wafer consists of a layer of Si with the thickness of 3μm on the top, a layer of silicon dioxide (SiO2) with the thickness of 5μm in the middle and a bottom layer of Si with the thickness of 500μm. Before fabrication, a thermally grown SiO2 film with the thickness of 0.27μm and a low stress LPCVD silicon nitride (SiN) film with the thickness of 0.5μm are deposited on the substrate. The SiN and SiO2 films are used as masks for potassium hydroxide (KOH) etching. The structure of the substrate before fabrication is shown in Figure 2-1-1.

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Figure 2-1-1. Wafer structure before fabrication.

The overall fabrication process includes three times of optical lithography, with the first one for SiN etching and the following two for Si etching.

To begin the lithography, the wafer is cleaned using piranha (H2SO4 and H2O2) solution and dehydrated on the hot plate at 300°C for five minutes. Haxamethyldisilazane (HMDS) vapors are applied to the wafer to enhance the adhesion of photoresist (PR) to the surface. The wafer is then coated with a layer of photoresist and soft baked on the hot plate at 110°C for one minute. After being exposed to UV light with the first layer of the etch mask aligned on the top for 12 seconds, the wafer is then put into the developer to dissolve the exposed part. The remaining photoresist function as the mask for the SiN etching using tetrafluoromethane (CF4) plasma in a vacuum chamber for 20 minutes. Figure 2-1-2 shows the top view of the device after the first lithography.

Figure 2-1-2. Top view of the device after the first lithography: (a) before SiN etching;

(b) after SiN etching.

Another lithography process is conducted for the first step of Si etching. After being coated with photoresist and soft baked at 110°C for one minute, the wafer is aligned under the second layer of the etch mask and exposed to UV light for 8 seconds. The second time of baking is conducted at 130°C for two minutes before the wafer is exposed to UV light without the etch mask for 30 seconds. After developing, the remaining photoresist has the pattern of the inverse image of the etch mask. The exposed portion of the SiO2 is removed with buffered oxide etch (BOE) solution and the bare underlying Si is etched by KOH solution. The KOH solution has the concentration of 30% and the etch rate is 0.31μm per minute at 60°C. Figure 2-1-3 shows the structure of the device after the second lithography. The KOH solution keeps etching the Si layer until the width of the Si cantilever beam on the top Si layer is about 2.5 to 3μm. A thermal oxidation process is conducted and a layer of SiO2 is formed on the surface of the exposed part of the Si layer in order to prevent the Si from being further etched in the second KOH etching.

Figure 2-1-3. Top view of the device after the second lithography: (a) before SiO2 etching; (b) after SiO2 etching; (c) after removing photoresist;

(d) after Si etching by using KOH solution.

The next step of fabrication is the third lithography. The processes of wafer cleaning, photoresist coating and soft baking are similar as those in the first lithography. The second layer of the etch mask is used during the exposure to the UV light for 20 seconds. After development, the remaining photoresist has the exact copy of the pattern on the etch mask. The uncovered SiO2 is etched using BOE solution and the Si underneath is etched by KOH solution for about 1 hour. After etching, the surface layer of the bare Si is converted to SiO2 by another oxidation process. The purpose of the oxidation is to protect the Si from being etched during the following SiN etching. Then the SiN layer is removed by phosphoric. The SiO2 layer under the SiN and the uncovered portion of the SiO2 on top of the bottom Si are both removed by BOE solution. Figure 2-1-4 shows the structure of the device after the third lithography.

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Figure 2-1-4. Top view of the device after the third lithography: (a) before SiO2 etching; (b) after SiO2 etching; (c) after removing photoresist and Si etching

by KOH solution; (d) after removing SiN and SiO2.

The nanogap device is shown in Figure 2-1-5. As can be seen in the figure, sharp tips are fabricated on the top Si layer of the device. The tips are formed by the (111) silicon crystal plane created during the first KOH etching and (100) plane created during the second KOH etching. There are nanoscale gaps between the sharp tips and the average size of the gaps is a few tens of nanometers.

Figure 2-1-5. Top view of the S1 nanogap device and close up view of the nanogap.

Four different designs of nanogap devices are fabricated together on one wafer. The configuration shown in Figure 2-1-5 is named as S1 device. Figure 2-1-6 shows the configuration of the S2 nanogap device.

Figure 2-1-6. Top view of the S2 nanogap device and the close up view of the nanogap.

The size of the nanogap can be estimated using Simmon's Model. A MATLAB program has been made to calculate the gap size. Details about the Simmon's Model and the program are in the appendix.

2.2 Growth of ZnO Nanostructures between Nanogaps

ZnO nanostructures are synthesized between the nanogaps by the thermal evaporation of Ni and Zn and the thermal oxidation of Zn.

After making nanogap devices, a layer of Ni with the thickness of 30nm and a layer of Zn with the thickness of 50nm are thermally evaporated on the devices in a vacuum of ~10-7 Torr. After that, the Zn film on the devices is oxidized to ZnO film in a quartz tube furnace with an oxygen flow of 5 sccm at 350℃ (Figure 2-2-1). Figure 2-2-2 shows the cross-sectional view of the device before and after the metal evaporation and the Zn oxidation.

Figure 2-2-1. Lindberg/Blue M quartz tube furnace.

Figure 2-2-2. Cross-sectional view of the device: (a) nanogap device; (b) device after evaporation of Ni and Zn; (c) device after oxidation.

Different kinds of metals have been considered as the electrode material for the nano-LED devices. However, alloy may be formed between Zn and other metals like aluminum and copper during the thermal oxidation process because of the high temperature. Compared with them, Ni react less with Zn at elevated temperature. As a result, Ni is preferred to perform the electrical contact for our device.

The images of the nanogap taken by scanning electron microscope (SEM) are shown in Figure 2-2-3.

Figure 2-2-3. SEM images of the nanogap: (a) close-up view of the gap;

(b) after evaporation and oxidation.

As can be seen in the picture, the nanogap is filled with ZnO after the evaporation of Ni and Zn and the Zn oxidation.