14 Bit Digitally Controlled Ring Oscillator Biology Essay

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Abstract-This paper present a 14-bits digitally controlled ring oscillator (DCO) with operating frequency up to 2.4 GHz in 0.18 mm CMOS Technology. Digital control is employed for controlling transistor operation to get low phase-noise. Sub-feedback topology is used to increase the frequency output. The DCO has a frequency tuning from 523 MHz until 2.402 GHz. Phase Noise at 4 MHz offset is -133.94 dBc/Hz (-119.72 dBc/Hz @ 1MHz). FOM is -168.58 dBc/Hz which is improvement of -8 dBc/Hz compared to the previously published result.

I. INTRODUCTION

Oscillator is the critical component in the PLL, which is an importance part in various applications such as in wireless applications. Due to the reason of tuning range and size which is needed to be wide and compact, ring oscillator become a choice of many RF circuit designers [1-12].

Technology scaling in CMOS design has improved the performance of the oscillator [2], but because the supply voltage that became smaller too, there have been difficulty in method for controlling it's tuning, since it uses analog intensive and require large power supply. Low supply voltage also increases phase-noise [11-12], especially for wireless applications. It is because low supply voltage limiting the output swing, which will degrading its phase noise performance that has been worsen by the use of analog intensive frequency control method.

To improve the phase noise, transistor should be operated in triode region and diode connected transistor in delay cell should be removed. This method has been reported to increase output swing and reduce the conduction time of delay cell transistor, which is needed to improve the phase noise [7,10].

In this paper, digitally controlled tuning is proposed to improve phase noise performance. Control Transistor is operated in triode region to get higher output voltage swing. A 14 bits control is used to achieve wide tuning range, low phase noise and high switching speed. It designed in 0.18 um technology.

This paper organized as follows. Section II will discuss the ring oscillator design. In Section III, there will be outline of the design and implementation of the DCO. Section IV will present the analysis of phase noise by using Hajimiri model. Measurement results will be presented in Section V, and finally, Section VI will conclude the paper.

II. RING OSCILLATOR DESIGN

General topology of the digitally controlled ring oscillator with a loop sub-feedback is shown in Figure 1. It is consisting of one main loop that have 4 inverters (I1-I4) and 4 sub-feedback loops (f1-f4). The number of feedback loops is the result of an optimization to produce high frequency output [1].

Figure 1. General Topology and Delay Cell's Schematic.

The schematic of the proposed oscillator core is also shown in Figure 1, where the wiring detail of inverters (I1-I4) is drawn in upper side and the schematic of an inverter is laid in lower side. I1-I4 make a chain of main loop that works as common ring oscillator, while the f1-f4 act as a second loop to reduce the transition time.

Each inverter consists of 4 transistors. Transistor M1 and M2 create a digital inverter which is acts as inverter in the main loop and on the other hand, transistor pairs M3, M4 and M5 serve as inverter in the second loop. M5 is used to control the voltage on M3 drain. When the input of the main loop inverter below its CMOS voltage threshold, main inverter's CMOS transistor will still OFF, while the second loop inverter which has input few stages from the main loop's input will have already ON. This make the output rises faster or in the other word, the time transition from high to low or from low to high is decreased. The decrease of the transition time will improve the phase noise performance and increase the frequency output. M3 is made very large compared to the M4 and M5 which are small in size, but the size of M4 and M5 cannot be too small since it has to pull the voltage at M3 drain. The value of the M3 has to be optimized to get the maximum output frequency [1].

III. RING OSCILLATOR DESIGN

Deep sub-micron technology has made tuning becomes more difficult, because it uses small supply voltage. Small supply voltage will produce small output swing and narrow tuning range. In order to keep the tuning range wide with that shrinking supply voltage, the CMOS transistor must be operated in triode and saturation region. But this technique has disadvantages; it will reduce output signal power and exacerbating the noise performance. In addition, CMOS operated in saturated region will also generate flicker noise (1/f) [3]. To overcome this problem, digital control lines are used to ON and OFF the CMOS transistor in order to reduce the flicker noise.

During the ON state, the CMOS transistor is pushed into deep triode region. This condition will form a thick and uniform line below the oxide layer which significantly reduces the possibility to trap the carrier in the oxide. Trapped carrier will be released during OFF condition of the CMOS. This will increase the output signal swing that increases the noise performance [2].

Tuning is done by using the digital control that uses a coupled block of CMOS transistor in series with M1 in the main loop and the other block connected in parallel with the M4 and M5 in the fast loop. Controlling is made from 3 control blocks; Coarse Tuning Block (CTB), Fine Tuning Block (FTB) and Acquisition Block.

CTB consist of 6 transistors (Mt5-Mt10) that connected to the drain of M1. It is controlled using 3 bits control code (23) to cover the complete tuning range. All transistors will turn off for control code 000, on the contrary, for control code 111, all transistors will turn on. CTB transistor sizes are chosen to keep to the same step, because the step size in the LSB (lease significant bit) is quite large for low frequencies and very small at high frequency. In the binary weighted scheme, it is difficult to maintain the same size throughout the tuning range. PMOS transistor operation is illustrated in Table I [6].

FTB has 5 transistors that are realized with 5 bits using binary weighted scheme. There is no logic implemented to turn ON and OFF the transistors in this block, because fast switching does not require it.

Coarse Tuning Block Operation

D6

D7

D8

Mt6

Mt7

Mt8

Mt9

Mt10

0

0

0

OFF

OFF

OFF

OFF

OFF

1

0

0

OFF

OFF

OFF

OFF

OFF

0

1

0

ON

OFF

OFF

OFF

OFF

1

1

0

OFF

ON

OFF

OFF

OFF

0

0

1

OFF

OFF

ON

OFF

OFF

1

0

1

OFF

OFF

OFF

ON

OFF

0

1

1

OFF

OFF

OFF

OFF

ON

1

1

1

ON

ON

ON

ON

ON

Acquisition Block is used to shift the frequency range to obtain a very small frequency steps. This is done by placing the 6 PMOS (Mt10-Mt15) in parallel with the M4 and M5, to create variations in drain voltage of M3. The lowest frequency output is achieved when whole block are set to zero or logic low, conversely the highest output frequency is obtained when all bits in this block is set to logic high In analog circuit, structure of the CTB and the FTB is a current starved structure [5]. This structure makes the output swing decline so that the noise increase, but with digital control that operates in the triode region, the output swing is maintained not to down. Digital control makes the circuit steadier because the transistor operating regions cannot be changed drastically. Delay at each stage is controlled by a digital control bit to control the charging current. The higher the input code, the higher the current through the output node, and the higher the oscillation frequency.

V. PHASE NOISE ANALYSIS

Phase-noise analysis is performed using Hajimiri model [7], which is given by equation (1),

(1)

Grms is the impulse sensitivity function (ISF) which is a periodic normalization phase distortion in a different instant in the period of 2p when an impulse current is injected; N is the number of delay cells; ∆w is the frequency offset; in2/∆w is the device noise power spectral density; while qmax is the maximum charge swing in side band power.

Equation (1) shows that the phase noise improvement can be achieved by reducing the rms value of the ISF and increasing the voltage swing on the output node. ISF value is ​​calculated using Eq. (2). [7]

(2)

Where Gi is the ISF, fi(x) is the normalized function of oscillating voltage at node i. Meanwhile, fi'(x) is the first derivative and fi" is the second derivative.

Another factor that plays a role in reducing the phase noise of the proposed ring oscillator is the thermal noise bandwidth of the oscillator. As the capacitance at the gate of the inverter acts as a low-pass filter for thermal noise, then the design with a larger gate would show better results, especially if the output frequency and power dissipation constant. To reduce 1/f noise, proposed design uses Digital control channel to make the transistors ON and OFF. During the ON state, Transistors is Driven in the deep triode region, where, unlike in the saturation region, the uniform and thick channel is formed in the bottom of the oxide. It can significantly reduce

Fig. 2. Chip Photograph

.

IV. EXPERIMENT RESULT

the possibility to trap the carrier in the oxide. These trapped carriers released during the OFF state of the transistor. These ideas improve the output signal swing which results in increased noise performance.Proposed 14-bit DCO is fabricated in 0.18um CMOS technology. The core oscillator and digital control circuits chip without bonding pads occupy only 0.032 mm2. Chip photograph is shown in Figure 3.

Figure 3 shows the output frequency waveform at 2.402 GHz, whereas Figure 4 shows the measured DCO tuning range. In figure 4, six bits data acquisition was set to 1 which gives highest frequency output. If data acquisition was sets to 127 or the whole bits in acquisitions block is given logic 1, the lowest frequency output can be obtained. The change in the code of data acquisition is going to make the frequency range shifted. Three bits CTP produce 8 pieces of graphs (C0-C7). Each graph shows the result of variations in 5 bits FTC which are plotted on the x-axis. Tuning range with data acquisition set from 0 (Figure 4) is measured from 662 MHz to 2.402 GHz, while when data acquisition is set to 1, the output will be from 524 MHz to 2239 GHz. All were using 2V voltage supply.

The picture of phase-noise measurement is shown in Fig.7. The phase-noise is measured as big as -133.94 dBc/Hz at 4 MHz offset frequency (or -119.78 dBc/Hz at 1 Mhz) from 2.402GHz carrier frequency. Power dissipation is 62mA. The simulation`s phase noise was -126.74 dBc/Hz at 4 MHz offset frequency (-111.58 dBc/Hz at 1 MHz) with power dissipation of 77.9 mA from 2.67 GHz carrier frequency. This difference could be caused by additional parasitic due to fabrication process which degrade the frequency but decrease the phase-noise. The differences also could be caused by the differences in calculation, which is done using a single DC operating point in simulation while actual operating point varies during cycle.

comparison with published result

Ref

Output Frequency

(GHz

Tech. (um)

Phase-noise

(dBc/Hz)

Freq. Offset

(Mhz)

Pdc

(mW)

FOM (dBc/Hz)

[1]

0.1 - 3.5

0.18

-106

4

16

-152.7

[2]

9.8 - 11.5

0.18

-94

2

75

-153.1

[3]

0.5 - 1.2

0.18

-94

1

0.71

-155.5

[4]

1.82 - 10.18

0.18

-88.4

1

5

-156.6

[5]

5.16 - 5.93

0.18

-99.5

1

27

-160.4

This work

0.52- 2.4

0.18

-133.9

4

62

-168.6

The measured phase-noise is better than previously published work [1-5] by -28 to -31 dBc/Hz. It is because of digital control which gives large voltage swing. Measured output spectrum is shown in figure 7 and 8 for 2.4GHz and 523 MHz respectively. Power spectrum is -4.65 dBm without compensation on the losses from cables and other measurement components. The power spectrum can be increased by increasing the Supply Voltage of Output Buffer. This Measurements use 1.8V for buffer supply.

Table III compares the performance of proposed DCO design with published results. Proposed DCO has a low phase-noise, high speed switching, and width tuning range. FOM of the DCO design achieved -168.58 dBc/Hz for 4 Mhz offset.

Fig. 3. Quadrature Output Wave Form.

Fig. 4. Measured Tuning Curve

Fig. 5.Measured Phase Noise of Proposed DCO.

Fig. 7. Measured Output Frequency Spectrum at 2.4 GHz.

Fig. 8. Measured Output Frequency Spectrum at 523 MHz.

V. CONCLUSION

Digital control using 14-bit control and ring oscillator core is presented. Proposed DCO has an improved phase-noise. Its digital control transistors have small voltage drop which reduces phase-noise. Transistor Operation in the triode region managed to reduce 1/f noise. Measurement`s result achieved a Phase-noise of -133.94 dBc/Hz at 4 Mhz offset from 2.4 GHz center frequency. FOM is calculated as big as -168.58 dBc/Hz, which is an improvement of - 8 dBc / Hz compared to the previous published result. Its better performance and flexibility make it suitable for ADPLL applications

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